diff options
| author | Yuval Peress <peress@google.com> | 2021-09-22 21:06:35 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-27 23:09:07 +0000 |
| commit | b6afc9e875cc6494ed6adb79c579f73093cff0c2 (patch) | |
| tree | f93f7472135fd9b127b52bf6298a6d61334f1712 /zephyr/shim/chip/npcx/system_external_storage.c | |
| parent | 4c58dc54f65e9dde3363a62f027d023d26b991f3 (diff) | |
| download | chrome-ec-b6afc9e875cc6494ed6adb79c579f73093cff0c2.tar.gz | |
zephyr: convert fwctrl register to syscon driver
Note that currently CONFIG_SYSCON=y is required. There's an ongoing
PR (https://github.com/zephyrproject-rtos/zephyr/pull/38762) to remove
that requirement in favor of simply detecting an enabled node in DT
via the compatible string.
BRANCH=none
BUG=b:179900857, b:165777478, b:200642229
TEST=zmake testall
Signed-off-by: Yuval Peress <peress@google.com>
Change-Id: Idad1f53afbda503e0e0b2fdf2931d5267a391d4d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3177749
Reviewed-by: Sam Hurst <shurst@google.com>
Diffstat (limited to 'zephyr/shim/chip/npcx/system_external_storage.c')
| -rw-r--r-- | zephyr/shim/chip/npcx/system_external_storage.c | 43 |
1 files changed, 30 insertions, 13 deletions
diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index b53db04e18..373a4a48f7 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -3,6 +3,9 @@ * found in the LICENSE file. */ +#include <devicetree.h> +#include <drivers/syscon.h> + #include "clock_chip.h" #include "common.h" #include "rom_chip.h" @@ -11,10 +14,19 @@ /* TODO (b:179900857) Make this implementation not npcx specific. */ -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) +static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc)); + +#ifdef CONFIG_SOC_SERIES_NPCX7 +#define NPCX_FWCTRL 0x007 #define NPCX_FWCTRL_RO_REGION 0 #define NPCX_FWCTRL_FW_SLOT 1 +#elif defined(CONFIG_SOC_SERIES_NPCX9) +#define NPCX_FWCTRL 0x009 +#define NPCX_FWCTRL_RO_REGION 6 +#define NPCX_FWCTRL_FW_SLOT 7 +#else +#error "Unsupported NPCX SoC series." +#endif void system_jump_to_booter(void) { @@ -97,18 +109,20 @@ uint32_t system_get_lfw_address() enum ec_image system_get_shrspi_image_copy(void) { - /* TODO (b:179900857) Make this implementation not npcx specific. */ - if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION)) { + uint32_t fwctrl = 0; + + syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl); + if (IS_BIT_SET(fwctrl, NPCX_FWCTRL_RO_REGION)) { /* RO image */ #ifdef CHIP_HAS_RO_B - if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT)) + if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT)) return EC_IMAGE_RO_B; #endif return EC_IMAGE_RO; } else { #ifdef CONFIG_RW_B /* RW image */ - if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT)) + if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT)) /* Slot A */ return EC_IMAGE_RW_B; #endif @@ -118,23 +132,26 @@ enum ec_image system_get_shrspi_image_copy(void) void system_set_image_copy(enum ec_image copy) { - /* TODO (b:179900857) Make this implementation not npcx specific. */ + uint32_t fwctrl = 0; + + syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl); switch (copy) { case EC_IMAGE_RW: - CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); - SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT); + CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); + SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); break; #ifdef CONFIG_RW_B case EC_IMAGE_RW_B: - CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); - CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT); + CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); + CLEAR_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); break; #endif default: /* Fall through to EC_IMAGE_RO */ case EC_IMAGE_RO: - SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); - SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT); + SET_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); + SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); break; } + syscon_write_reg(mdc_dev, NPCX_FWCTRL, fwctrl); } |