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| author | Jun Lin <CHLin56@nuvoton.com> | 2021-09-10 13:36:17 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-17 10:11:45 +0000 |
| commit | 20222d48571fa44c76fdb0ededd0ed042e9f8244 (patch) | |
| tree | cf3980940a27dadd13e2912d1eb92724f4287c1e /zephyr/shim/chip/npcx/system_external_storage.c | |
| parent | cec869cd82bee052362a1e3e292854163a25fd88 (diff) | |
| download | chrome-ec-20222d48571fa44c76fdb0ededd0ed042e9f8244.tar.gz | |
npcx: correct the image copies indication bits for npcx9
In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'zephyr/shim/chip/npcx/system_external_storage.c')
| -rw-r--r-- | zephyr/shim/chip/npcx/system_external_storage.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index b53db04e18..bce82b8841 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -12,9 +12,17 @@ /* TODO (b:179900857) Make this implementation not npcx specific. */ #define NPCX_MDC_BASE_ADDR 0x4000C000 +#ifdef CONFIG_SOC_SERIES_NPCX7 #define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) #define NPCX_FWCTRL_RO_REGION 0 #define NPCX_FWCTRL_FW_SLOT 1 +#elif defined(CONFIG_SOC_SERIES_NPCX9) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x005) +#define NPCX_FWCTRL_RO_REGION 1 +#define NPCX_FWCTRL_FW_SLOT 2 +#else +#error "Unsupported NPCX SoC series." +#endif void system_jump_to_booter(void) { |