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| author | Wealian Liao <whliao@nuvoton.corp-partner.google.com> | 2021-06-29 10:56:07 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-30 03:52:43 +0000 |
| commit | c6a07db427015c4ccc64fb2394315e82b31344fb (patch) | |
| tree | 353eccb8424f4a2ac54488429e901a7f3a2a63c6 /zephyr/shim/chip/npcx | |
| parent | 1d46cb0e6f2c172efa7b0b8b1b8c75dd5caaa923 (diff) | |
| download | chrome-ec-c6a07db427015c4ccc64fb2394315e82b31344fb.tar.gz | |
zephyr: npcx: Fix NPCX_PWDWN_CTL redefine warning
UPSTREAM has NPCX_PWDWN_CTL definition. This CL transfers to use
UPSTREAM NPCX_PWDWN_CTL macro to fix the redefine warning.
BRANCH=none
BUG=none
TEST=build byra without warning
TEST='sysjump RW' is correct
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ib92f2263f3e10cae5d8b0ebd4f3b274c8c7359a0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994229
Reviewed-by: Yuval Peress <peress@chromium.org>
Diffstat (limited to 'zephyr/shim/chip/npcx')
| -rw-r--r-- | zephyr/shim/chip/npcx/system_download_from_flash.c | 22 |
1 files changed, 3 insertions, 19 deletions
diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c index bf50f736cd..28ec22962c 100644 --- a/zephyr/shim/chip/npcx/system_download_from_flash.c +++ b/zephyr/shim/chip/npcx/system_download_from_flash.c @@ -2,10 +2,12 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include <dt-bindings/clock/npcx_clock.h> #include <stdnoreturn.h> #include <sys/__assert.h> #include "common.h" +#include "soc.h" #include "system_chip.h" /* Modules Map */ @@ -41,24 +43,6 @@ #define NPCX_LPRAM_CTRL REG32(0x40001044) /******************************************************************************/ -/* Power Management Controller (PMC) Registers */ -#define NPCX_PWDWN_CTL_ADDR(offset) (((offset) < 6) ? \ - (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ - (NPCX_PMC_BASE_ADDR + 0x024)) -#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) - -/* PMC enumeration */ -enum NPCX_PMC_PWDWN_CTL_T { - NPCX_PMC_PWDWN_1 = 0, - NPCX_PMC_PWDWN_2 = 1, - NPCX_PMC_PWDWN_3 = 2, - NPCX_PMC_PWDWN_4 = 3, - NPCX_PMC_PWDWN_5 = 4, - NPCX_PMC_PWDWN_6 = 5, - NPCX_PMC_PWDWN_7 = 6, - NPCX_PMC_PWDWN_CNT, -}; - /* Sysjump utilities in low power ram for npcx series. */ noreturn void __keep __attribute__ ((section(".lowpower_ram2"))) __start_gdma(uint32_t exeAddr) @@ -124,7 +108,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, __ASSERT_NO_MSG(exeAddr != 0x0); /* Enable power for the Low Power RAM */ - CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6); + CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_BASE_ADDR, NPCX_PWDWN_CTL6), 6); /* Enable Low Power RAM */ NPCX_LPRAM_CTRL = 1; |