diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2021-03-09 17:21:34 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-11 23:24:08 +0000 |
| commit | 97e22d467763dace5df64c9869cd8d4984f4ab39 (patch) | |
| tree | 0abf2af92c18a2e67221a7a8c090cea04f708dd6 /zephyr/shim/chip | |
| parent | dd6abb2055e4ba979a02e52459aeb9b10167f8f3 (diff) | |
| download | chrome-ec-97e22d467763dace5df64c9869cd8d4984f4ab39.tar.gz | |
zephyr: npcx: clock: add clock turbo/normal functions
Implement the following functions in Zephyr:
1. clock_turbo
2. clock_normal
3. clock_enable_module
With these, the CPU clock can speeds up when computing the hash value
and goes back to normal when the computation is done.
BRANCH=none
BUG=b:182224114
TEST=Volteer no longer watchdog resets and can boot up to ChromeOS
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I419cf68c4212fdc588b9fd2a08331c4e81ccf0a0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2748197
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr/shim/chip')
| -rw-r--r-- | zephyr/shim/chip/npcx/clock.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c index d70ac43e0f..24ae45d107 100644 --- a/zephyr/shim/chip/npcx/clock.c +++ b/zephyr/shim/chip/npcx/clock.c @@ -12,9 +12,14 @@ #include <zephyr.h> #include "clock_chip.h" +#include "module_id.h" LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); +#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) +#define HAL_CDCG_REG_BASE_ADDR \ + ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) + int clock_get_freq(void) { const struct device *clk_dev = device_get_binding(NPCX_CLK_CTRL_NAME); @@ -34,4 +39,31 @@ int clock_get_freq(void) void clock_turbo(void) { + struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; + + /* For NPCX7: + * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since + * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. + */ + cdcg_base->HFCGP = 0x01; + cdcg_base->HFCBCD = BIT(4); +} + +void clock_normal(void) +{ + struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; + + cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL); + cdcg_base->HFCBCD = (FIUDIV_VAL << 4); +} + +void clock_enable_module(enum module_id module, int enable) +{ + /* Assume we have a single task using MODULE_FAST_CPU */ + if (module == MODULE_FAST_CPU) { + if (enable) + clock_turbo(); + else + clock_normal(); + } } |