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| author | Yuval Peress <peress@chromium.org> | 2021-01-29 10:16:24 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-01 18:43:13 +0000 |
| commit | 4202400f14c6bd4239834c1c3774333c403ab0e9 (patch) | |
| tree | 4dddd92dead24e196ffef021dbc1d8da7e80de61 /zephyr/shim/include/bbram.h | |
| parent | 025b35ffdf3d474e8a853c73abe4e336c7a8edf6 (diff) | |
| download | chrome-ec-4202400f14c6bd4239834c1c3774333c403ab0e9.tar.gz | |
zephyr: Add battery-backed RAM constants for npcx
Bring in the battery-backed RAM layout for npcx. This change
includes a TODO to migrate these values to devicetree registers
but since system.c is on the critical path, this will be a good
step in the right direction.
BRANCH=none
BUG=b:176828988, b:174481378
TEST=zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: Ib84bf4f680c74a95a8549f57c30dab7fca3db42c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659681
Commit-Queue: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'zephyr/shim/include/bbram.h')
| -rw-r--r-- | zephyr/shim/include/bbram.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/zephyr/shim/include/bbram.h b/zephyr/shim/include/bbram.h new file mode 100644 index 0000000000..95e15d6f84 --- /dev/null +++ b/zephyr/shim/include/bbram.h @@ -0,0 +1,40 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef ZEPHYR_SHIM_INCLUDE_BBRAM_H_ +#define ZEPHYR_SHIM_INCLUDE_BBRAM_H_ + +/** + * Layout of the battery-backed RAM region. + * TODO (b:178807203) Migrate these values to devicetree registers. + */ +enum bbram_data_index { + /** General-purpose scratchpad */ + BBRM_DATA_INDEX_SCRATCHPAD = 0, + /** Saved reset flags */ + BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, + /** Wake reasons for hibernate */ + BBRM_DATA_INDEX_WAKE = 8, + /** USB-PD saved port0 state */ + BBRM_DATA_INDEX_PD0 = 12, + /** USB-PD saved port1 state */ + BBRM_DATA_INDEX_PD1 = 13, + /** Vboot EC try slot */ + BBRM_DATA_INDEX_TRY_SLOT = 14, + /** USB-PD saved port2 state */ + BBRM_DATA_INDEX_PD2 = 15, + /** VbNvContext for ARM arch */ + BBRM_DATA_INDEX_VBNVCNTXT = 16, + /** RAM log for Booter */ + BBRM_DATA_INDEX_RAMLOG = 32, + /** Flag to indicate validity of panic data starting at index 36. */ + BBRM_DATA_INDEX_PANIC_FLAGS = 35, + /** Panic data (index 35-63)*/ + BBRM_DATA_INDEX_PANIC_BKUP = 36, + /** The start time of LCT(4 bytes) */ + BBRM_DATA_INDEX_LCT_TIME = 64, +}; + +#endif /* ZEPHYR_SHIM_INCLUDE_BBRAM_H_ */ |