diff options
| author | Andrew McRae <amcrae@google.com> | 2022-03-10 17:33:03 +1100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-03-11 12:54:56 +0000 |
| commit | 52236bd5ef3d1b267ddecd8f5f7958a948bcdcf4 (patch) | |
| tree | 4f6fd35da9229af59494ebcc9db56547ffb0d0bf /zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c | |
| parent | afec0de57ff93841bbd2aee66e887829fda0d24c (diff) | |
| download | chrome-ec-52236bd5ef3d1b267ddecd8f5f7958a948bcdcf4.tar.gz | |
zephyr: Add complete AP API interface
Detach the AP API interface from the legacy API,
create a new equivalent API, and connect it via
a shim.
BUG=b:223715700
TEST=zmake build nivviks; flash and run
BRANCH=none
Signed-off-by: Andrew McRae <amcrae@google.com>
Change-Id: I09072084bb118f1814ac707809fd360475771e15
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3515426
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Diffstat (limited to 'zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c')
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index a428a4b834..2dd836dd26 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -112,7 +112,7 @@ void pwr_sm_set_state(enum power_states_ndsx new_state) pwrseq_ctx.power_state = new_state; } -void chipset_request_exit_hardoff(bool should_exit) +void request_exit_hardoff(bool should_exit) { pwrseq_ctx.want_g3_exit = should_exit; } @@ -125,7 +125,7 @@ static bool chipset_is_exit_hardoff(void) void apshutdown(void) { if (pwr_sm_get_state() != SYS_POWER_STATE_G3) { - new_chipset_force_shutdown(); + ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3); pwr_sm_set_state(SYS_POWER_STATE_G3); } } @@ -157,7 +157,7 @@ int check_pch_out_of_suspend(void) } /* Handling RSMRST signal is mostly common across x86 chipsets */ -__attribute__((weak)) void rsmrst_pass_thru_handler(void) +void rsmrst_pass_thru_handler(void) { /* Handle RSMRST passthrough */ /* TODO: Add additional conditions for RSMRST handling */ @@ -181,7 +181,7 @@ static int common_pwr_sm_run(int state) switch (state) { case SYS_POWER_STATE_G3: if (chipset_is_exit_hardoff()) { - chipset_request_exit_hardoff(false); + request_exit_hardoff(false); return SYS_POWER_STATE_G3S5; } @@ -231,7 +231,7 @@ static int common_pwr_sm_run(int state) break; case SYS_POWER_STATE_S5G3: - new_chipset_force_shutdown(); + ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3); return SYS_POWER_STATE_G3; case SYS_POWER_STATE_S5S4: @@ -254,7 +254,7 @@ static int common_pwr_sm_run(int state) case SYS_POWER_STATE_S4S3: if (!power_signals_on(IN_PGOOD_ALL_CORE)) { /* Required rail went away */ - new_chipset_force_shutdown(); + ap_power_force_shutdown(AP_POWER_SHUTDOWN_POWERFAIL); return SYS_POWER_STATE_G3; } @@ -272,7 +272,7 @@ static int common_pwr_sm_run(int state) /* AP is out of suspend to RAM */ if (!power_signals_on(IN_PGOOD_ALL_CORE)) { /* Required rail went away, go straight to S5 */ - new_chipset_force_shutdown(); + ap_power_force_shutdown(AP_POWER_SHUTDOWN_POWERFAIL); return SYS_POWER_STATE_G3; } else if (signals_valid_and_off(IN_PCH_SLP_S3)) return SYS_POWER_STATE_S3S0; @@ -283,7 +283,7 @@ static int common_pwr_sm_run(int state) case SYS_POWER_STATE_S3S0: if (!power_signals_on(IN_PGOOD_ALL_CORE)) { - new_chipset_force_shutdown(); + ap_power_force_shutdown(AP_POWER_SHUTDOWN_POWERFAIL); return SYS_POWER_STATE_G3; } @@ -294,7 +294,7 @@ static int common_pwr_sm_run(int state) case SYS_POWER_STATE_S0: if (!power_signals_on(IN_PGOOD_ALL_CORE)) { - new_chipset_force_shutdown(); + ap_power_force_shutdown(AP_POWER_SHUTDOWN_POWERFAIL); return SYS_POWER_STATE_G3; } else if (signals_valid_and_on(IN_PCH_SLP_S3)) return SYS_POWER_STATE_S0S3; @@ -401,7 +401,7 @@ void ap_pwrseq_task_start(void) static void init_pwr_seq_state(void) { init_chipset_pwr_seq_state(); - chipset_request_exit_hardoff(false); + request_exit_hardoff(false); pwr_sm_set_state(SYS_POWER_STATE_G3S5); } |