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| author | Paul Fagerburg <pfagerburg@google.com> | 2021-01-22 09:56:01 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-22 23:13:46 +0000 |
| commit | 3a00c91522337c6bc79271d5b0fddd2852459c37 (patch) | |
| tree | c5153bce0342afb3348345d3320092f9f19c56fb /zephyr/test/accel_cal/prj.conf | |
| parent | 5215f4c6dceef2d259f27d2732b2fab3e18ab5c7 (diff) | |
| download | chrome-ec-3a00c91522337c6bc79271d5b0fddd2852459c37.tar.gz | |
test: port accel_cal to Ztest
BUG=b:172240633
BRANCH=none
TEST=build for both EC and Ztest:
`TEST_LIST_HOST=accel_cal make runhosttests`
`zmake configure --test -B build/accel_cal zephyr/test/accel_cal`
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie787403b36d775d4185cafad8ca134561a97794b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2645198
Tested-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'zephyr/test/accel_cal/prj.conf')
| -rw-r--r-- | zephyr/test/accel_cal/prj.conf | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/zephyr/test/accel_cal/prj.conf b/zephyr/test/accel_cal/prj.conf new file mode 100644 index 0000000000..648eb63dd7 --- /dev/null +++ b/zephyr/test/accel_cal/prj.conf @@ -0,0 +1,24 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_ZTEST=y +CONFIG_HAS_TEST_TASKS=y +CONFIG_POLL=y + +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_I2C=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_HOSTCMD=n +CONFIG_PLATFORM_EC_TIMER=n + +CONFIG_CROS_EC=y +# Define necessary program memory locations. These are meaning less though +CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10090000 +CONFIG_CROS_EC_RAM_BASE=0x200c0000 +CONFIG_CROS_EC_DATA_RAM_SIZE=0x00010000 +CONFIG_CROS_EC_RAM_SIZE=0x0000f800 +CONFIG_CROS_EC_RO_MEM_OFF=0x0 +CONFIG_CROS_EC_RO_SIZE=0xb000 +CONFIG_CROS_EC_RW_MEM_OFF=0xb000 +CONFIG_CROS_EC_RW_SIZE=0x75000 |