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| author | Andrew McRae <amcrae@google.com> | 2022-03-13 16:58:25 +1100 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-29 23:09:31 +0000 |
| commit | 6ea4239b2caa21e1588a15078bfdba9b00a0a2a0 (patch) | |
| tree | 2b062b22a7c02157546de615d8c854e9be9f72b2 /zephyr | |
| parent | 2bd5b88f7f77c5a3f4613bf48fe7e53de49e0813 (diff) | |
| download | chrome-ec-6ea4239b2caa21e1588a15078bfdba9b00a0a2a0.tar.gz | |
nissa: Add Nivviks ADC power signal handling
Split from chromium:3389663
Adds ADC signal processing for 3.3V and 1.05V rails.
Depends-on:
- https://github.com/zephyrproject-rtos/zephyr/pull/43398
- https://github.com/zephyrproject-rtos/zephyr/pull/41515
BUG=b:216667527
TEST=zmake build nivviks; flash and run
BRANCH=none
Signed-off-by: Andrew McRae <amcrae@google.com>
Change-Id: I55203f1c18ae5fca059cd3ff988cea025614ae74
Signed-off-by: Perez Priego, Bernardo <bernardo.perez.priego@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3518911
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Diffstat (limited to 'zephyr')
| -rw-r--r-- | zephyr/projects/nissa/nivviks_power_signals.dts | 44 | ||||
| -rw-r--r-- | zephyr/projects/nissa/prj_nivviks.conf | 6 | ||||
| -rw-r--r-- | zephyr/projects/nissa/src/board_power.c | 3 |
3 files changed, 49 insertions, 4 deletions
diff --git a/zephyr/projects/nissa/nivviks_power_signals.dts b/zephyr/projects/nissa/nivviks_power_signals.dts index 5aed901783..6d89d57fd0 100644 --- a/zephyr/projects/nissa/nivviks_power_signals.dts +++ b/zephyr/projects/nissa/nivviks_power_signals.dts @@ -126,14 +126,50 @@ enum-name = "PWR_ALL_SYS_PWRGD"; }; pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Temporary override for ADC PWR_DSW_PWROK"; + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; }; pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Temporary override for ADC PWR_PG_PP1P05"; + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; }; }; diff --git a/zephyr/projects/nissa/prj_nivviks.conf b/zephyr/projects/nissa/prj_nivviks.conf index 7a39218435..3e68eb3158 100644 --- a/zephyr/projects/nissa/prj_nivviks.conf +++ b/zephyr/projects/nissa/prj_nivviks.conf @@ -31,3 +31,9 @@ CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y # Charger driver and configuration CONFIG_PLATFORM_EC_CHARGER_RAA489000=y CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n +CONFIG_TACH_NPCX=n diff --git a/zephyr/projects/nissa/src/board_power.c b/zephyr/projects/nissa/src/board_power.c index d4576f1f67..78fd49cebc 100644 --- a/zephyr/projects/nissa/src/board_power.c +++ b/zephyr/projects/nissa/src/board_power.c @@ -121,11 +121,14 @@ int board_power_signal_get(enum power_signal signal) * Temporary workaround for ADC signal. * Assume always on. */ + +#ifdef CONFIG_BOARD_NEREID case PWR_DSW_PWROK: return 1; case PWR_PG_PP1P05: return 1; +#endif } } |