zephyr: mchp: Support 512KB SPI image generation

Adjust configurations to fit SPI image generation

BUG=none
BRANCH=main
TEST=zmake testall

Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I06da9b78fd3b3f42855ef197a37a18bc11ec3711
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3686761
Reviewed-by: Al Semjonovs <asemjonovs@google.com>

5 files changed, 78 insertions, 13 deletions

diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header
index e5c137b99e..931d7dbaf1 100644
--- a/zephyr/Kconfig.header
+++ b/zephyr/Kconfig.header
@@ -16,6 +16,7 @@ config PLATFORM_EC_RO_HEADER
 
 config PLATFORM_EC_RO_HEADER_OFFSET
 	hex "Offset in memory for the location of the header"
+	default 0x1000 if SOC_SERIES_MEC172X
 	default 0x0
 	help
 	  The offset (in bytes) of the header relative to the start address of
@@ -24,7 +25,6 @@ config PLATFORM_EC_RO_HEADER_OFFSET
 config PLATFORM_EC_RO_HEADER_SIZE
 	hex "Size of the RO header"
 	default 0x40 if SOC_FAMILY_NPCX
-	default 0x140 if SOC_SERIES_MEC172X
 	default 0x0
 	help
 	  The size of the RO header in bytes. This values should come from the
diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
index 998116c243..9e37b6a534 100644
--- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
+++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
@@ -20,16 +20,18 @@ if SOC_SERIES_MEC172X
 config CROS_EC_PROGRAM_MEMORY_BASE
 	default 0xc0000
 
+# Data SRAM base
 config CROS_EC_RAM_BASE
-	default 0xc0000
+	default 0x118000
 
-# Data size: 64K - 2K, top 1KB is persistent
+# Total data SRAM size
 config CROS_EC_DATA_RAM_SIZE
-	default 0x00F800
+	default 0x010000
 
-# Code + Data: Top 1KB is peristent
+# Top 2KB reserved for PUF leaving 62KB
+# 61KB for data + 1KB persistent across chip reset.
 config CROS_EC_RAM_SIZE
-	default 0x067800
+	default 0x00f800
 
 config FLASH_SIZE
 	default 512
@@ -37,8 +39,9 @@ config FLASH_SIZE
 config CROS_EC_RO_MEM_OFF
 	default 0x0
 
+# was 0x40000
 config CROS_EC_RO_SIZE
-	default 0x40000
+	default 0x3F000
 
 # RW firmware in program memory - Identical to RO, only one image loaded at a
 # time.
diff --git a/zephyr/boards/arm/mec1727/mec1727.dts b/zephyr/boards/arm/mec1727/mec1727.dts
index c88e61b692..d371f8a2dc 100644
--- a/zephyr/boards/arm/mec1727/mec1727.dts
+++ b/zephyr/boards/arm/mec1727/mec1727.dts
@@ -8,8 +8,7 @@
 #include <cros/microchip/mec1727.dtsi>
 #include <cros/thermistor/thermistor.dtsi>
 #include <dt-bindings/gpio_defines.h>
-#include <microchip/mec172xnsz.dtsi>
-#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
+#include <microchip/mec1727nsz.dtsi>
 
 / {
 	model = "MEC1727";
diff --git a/zephyr/include/cros/microchip/mec1727.dtsi b/zephyr/include/cros/microchip/mec1727.dtsi
index b388f456d2..340cff1956 100644
--- a/zephyr/include/cros/microchip/mec1727.dtsi
+++ b/zephyr/include/cros/microchip/mec1727.dtsi
@@ -5,13 +5,76 @@
 
 /dts-v1/;
 
-#include <cros/microchip/mec172x.dtsi>
+#include <cros/binman.dtsi>
+#include <microchip/mec1727nsz.dtsi>
 
 / {
+	chosen {
+		cros-ec,adc = &adc0;
+		cros-ec,bbram = &bbram;
+		cros-ec,espi = &espi0;
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &fiu0;
+		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,watchdog = &wdog;
+		cros,rtc = &crtc;
+	};
 
-	soc {
+	named-bbram-regions {
+		compatible = "named-bbram-regions";
 
+		scratchpad {
+			offset = <0x00>;
+			size = <0x04>;
+		};
+		saved-reset-flags {
+			offset = <0x04>;
+			size = <0x04>;
+		};
+		wake {
+			offset = <0x08>;
+			size = <0x04>;
+		};
+		pd0 {
+			offset = <0x0c>;
+			size = <0x01>;
+		};
+		pd1 {
+			offset = <0x0d>;
+			size = <0x01>;
+		};
+		try_slot {
+			offset = <0x0e>;
+			size = <0x01>;
+		};
+		pd2 {
+			offset = <0x0f>;
+			size = <0x01>;
+		};
+		ramlog {
+			offset = <0x20>;
+			size = <0x01>;
+		};
+		panic_flags {
+			offset = <0x23>;
+			size = <0x01>;
+		};
+		panic_bkup {
+			offset = <0x24>;
+			size = <0x1c>;
+		};
+		lct_time {
+			offset = <0x40>;
+			size = <0x04>;
+		};
+		ec_img_load {
+			offset = <0x44>;
+			size = <0x01>;
+		};
 	};
 
+	fiu0: cros-flash {
+		compatible = "microchip,xec-cros-flash";
+		label = "INTERNAL_FLASH";
+	};
 };
-
diff --git a/zephyr/zmake/zmake/output_packers.py b/zephyr/zmake/zmake/output_packers.py
index c09c6cc84c..78ee7649e6 100644
--- a/zephyr/zmake/zmake/output_packers.py
+++ b/zephyr/zmake/zmake/output_packers.py
@@ -237,7 +237,7 @@ class MchpPacker(BinmanPacker):
     """Packer for RO/RW image to generate a .bin build using FMAP.
 
     This expects that the build is setup to generate a
-    zephyr.npcx.bin for the RO image, which should be packed using
+    zephyr.mchp.bin for the RO image, which should be packed using
     Microchip's loader format.
     """