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authorWai-Hong Tam <waihong@google.com>2021-09-15 16:57:06 -0700
committerCommit Bot <commit-bot@chromium.org>2021-09-16 23:02:46 +0000
commitac36a80c3206c55d365804f561cc89ab1550e99f (patch)
tree073ccc519196c923c061501704e8e0fc885125c0 /zephyr
parente740b27b1dc5b8065b9c618950823c3054ea2bb0 (diff)
downloadchrome-ec-ac36a80c3206c55d365804f561cc89ab1550e99f.tar.gz
herobrine: Always enable the 5V rail
Prepare the next hardware revision. It has a PPC chip which requires 5V rail in S5. The 5V rail enable pin should be turned on whenever the EC is powered. Since the existing 5V rail enabling is done inside the qcom power sequence. Trogdor and Herobrine both shares this qcom power sequence. For Trogdor, this CL moves the 5V rail enabling from the qcom power sequence to the board level hook. For Herobrine, this CL updates the GPIO name and modifies the default level to HIGH. The CONFIG of 5V control should be disabled. As no board level hook to modify the 5V rail, the 5V is always on. BRANCH=None BUG=b:199804198 TEST=Booted both Zephyr and EC-OS images on Herobrine. Checked the 5V rail is enabled in S0 and S5. TEST=Booted both Zephyr and EC-OS images on Lazor. Checked the 5V rail is enabled in S0 and disabled in S5. Change-Id: Ifa98ee0c4e970dd89952e94cc6a0e289798e6a57 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3163918 Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr')
-rw-r--r--zephyr/projects/herobrine/herobrine_npcx9/gpio.dts6
-rw-r--r--zephyr/projects/herobrine/herobrine_npcx9/prj.conf1
2 files changed, 4 insertions, 3 deletions
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts b/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
index 639fe30a3b..1f5052af04 100644
--- a/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
+++ b/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
@@ -157,10 +157,10 @@
enum-name = "GPIO_SWITCHCAP_ON";
label = "SWITCHCAP_ON";
};
- en_pp5000_s3 {
- gpios = <&gpio7 3 GPIO_OUT_LOW>;
+ en_pp5000_s5 {
+ gpios = <&gpio7 3 GPIO_OUT_HIGH>;
enum-name = "GPIO_EN_PP5000";
- label = "EN_PP5000_S3";
+ label = "EN_PP5000_S5";
};
ec_bl_disable_l {
gpios = <&gpiob 6 GPIO_OUT_LOW>;
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
index 95f4005857..75a1e79702 100644
--- a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
+++ b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
@@ -45,6 +45,7 @@ CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
# Power Sequencing
CONFIG_PLATFORM_EC_POWERSEQ=y
CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y