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authorSimon Glass <sjg@chromium.org>2021-01-14 13:30:07 -0700
committerCommit Bot <commit-bot@chromium.org>2021-01-16 03:18:16 +0000
commit2f2fa696cea36e1a6b370bf154d17914fa59c471 (patch)
tree5959517cb1c5c0d095d7c665160a2ffe251cc305 /zephyr
parent51367e5614961ad124ed2e3abea30dbd0c22ecc7 (diff)
downloadchrome-ec-2f2fa696cea36e1a6b370bf154d17914fa59c471.tar.gz
zephyr: Enable USB3.2 support
Provide this option so that the extra facilities of the USB3.2 standard can be used by a connected device. BUG=b:175434113 BRANCH=none TEST=make BOARD=volteer -j30 With a zephyr-chrome CL, build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I7459eb6769842f11f09d065e3df5a3d225457894 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2631092 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'zephyr')
-rw-r--r--zephyr/Kconfig.usbc9
-rw-r--r--zephyr/shim/include/config_chip.h5
2 files changed, 14 insertions, 0 deletions
diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc
index 3b8e773ec4..a5bc6897e2 100644
--- a/zephyr/Kconfig.usbc
+++ b/zephyr/Kconfig.usbc
@@ -309,6 +309,15 @@ config PLATFORM_EC_USB_PD_ALT_MODE_UFP
USB4 and ThunderBolt operation when the Chromium OS data role
resolves to the UFP role.
+config PLATFORM_EC_USB_PD_USB32_DRD
+ bool "Port is cable of operating as an USB3.2 device"
+ default y
+ help
+ Enable this if the board's USB Power Delivery Downward Facing Port is
+ able to support the USB3.2 standard. This is advertised to the
+ other end so that it can potentially take advantage of the additional
+ features available.
+
choice "VBUS detection method"
prompt "Select the method to detect VBUS"
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 7db0ca55dd..c9b8afc019 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -547,4 +547,9 @@ enum battery_type {
#define CONFIG_USBC_PPC_VCONN
#endif
+#undef CONFIG_USB_PD_USB32_DRD
+#ifdef CONFIG_PLATFORM_EC_USB_PD_USB32_DRD
+#define CONFIG_USB_PD_USB32_DRD
+#endif
+
#endif /* __CROS_EC_CONFIG_CHIP_H */