zephyr: npcx9: add __start_gdma function to .lowpower_ram2 section

This function is needed for the flash api workaround.

BRANCH=none
BUG=b:188605676
TEST=build brya

Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I3ddd72e7664755f07bc967695b1502a43af3e57a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936008
Reviewed-by: Keith Short <keithshort@chromium.org>

4 files changed, 81 insertions, 6 deletions

diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt
index 79d81f720e..c7cca9939a 100644
--- a/zephyr/shim/chip/npcx/CMakeLists.txt
+++ b/zephyr/shim/chip/npcx/CMakeLists.txt
@@ -12,4 +12,6 @@ zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
 
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
         system_external_storage.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API
+        system_download_from_flash.c)
 zephyr_library_sources_ifdef(CONFIG_PM_POLICY_APP     power_policy.c)
diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h
index e2e9d5379d..44a60b47b5 100644
--- a/zephyr/shim/chip/npcx/include/system_chip.h
+++ b/zephyr/shim/chip/npcx/include/system_chip.h
@@ -6,6 +6,13 @@
 #ifndef __CROS_EC_SYSTEM_CHIP_H_
 #define __CROS_EC_SYSTEM_CHIP_H_
 
+#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
+
+/* TODO(b:179900857) Clean this up too */
+#undef IS_BIT_SET
+#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
+
 /*****************************************************************************/
 /* Memory mapping */
 #define CONFIG_LPRAM_BASE	0x40001400 /* memory address of lpwr ram */
diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c
new file mode 100644
index 0000000000..9e80df8f2d
--- /dev/null
+++ b/zephyr/shim/chip/npcx/system_download_from_flash.c
@@ -0,0 +1,71 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <stdnoreturn.h>
+
+#include "common.h"
+#include "system_chip.h"
+
+/* Modules Map */
+#define NPCX_GDMA_BASE_ADDR	0x40011000
+
+/******************************************************************************/
+/* GDMA (General DMA) Registers */
+#define NPCX_GDMA_CTL		REG32(NPCX_GDMA_BASE_ADDR + 0x000)
+#define NPCX_GDMA_SRCB		REG32(NPCX_GDMA_BASE_ADDR + 0x004)
+#define NPCX_GDMA_DSTB		REG32(NPCX_GDMA_BASE_ADDR + 0x008)
+
+/******************************************************************************/
+/* GDMA register fields */
+#define NPCX_GDMA_CTL_GDMAEN                         0
+#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
+#define NPCX_GDMA_CTL_DADIR                          4
+#define NPCX_GDMA_CTL_SADIR                          5
+#define NPCX_GDMA_CTL_SAFIX                          7
+#define NPCX_GDMA_CTL_SIEN                           8
+#define NPCX_GDMA_CTL_BME                            9
+#define NPCX_GDMA_CTL_SBMS                           11
+#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
+#define NPCX_GDMA_CTL_DM                             15
+#define NPCX_GDMA_CTL_SOFTREQ                        16
+#define NPCX_GDMA_CTL_TC                             18
+#define NPCX_GDMA_CTL_GDMAERR                        20
+#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
+
+/* Sysjump utilities in low power ram for npcx series. */
+noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
+__start_gdma(uint32_t exeAddr)
+{
+	/* Enable GDMA now */
+	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
+
+	/* Start GDMA */
+	SET_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_SOFTREQ);
+
+	/* Wait for transfer to complete/fail */
+	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
+			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+		;
+
+	/* Disable GDMA now */
+	CLEAR_BIT(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAEN);
+
+	/*
+	 * Failure occurs during GMDA transaction. Let watchdog issue and
+	 * boot from RO region again.
+	 */
+	if (IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+		while (1)
+			;
+
+	/*
+	 * Jump to the exeAddr address if needed. Setting bit 0 of address to
+	 * indicate it's a thumb branch for cortex-m series CPU.
+	 */
+	((void (*)(void))(exeAddr | 0x01))();
+
+	/* Should never get here */
+	while (1)
+		;
+}
\ No newline at end of file
diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c
index 4c4c5c0e6c..4b77a3972f 100644
--- a/zephyr/shim/chip/npcx/system_external_storage.c
+++ b/zephyr/shim/chip/npcx/system_external_storage.c
@@ -7,6 +7,7 @@
 #include "common.h"
 #include "rom_chip.h"
 #include "system.h"
+#include "system_chip.h"
 
 /* TODO (b:179900857) Make this implementation not npcx specific. */
 
@@ -14,12 +15,6 @@
 #define NPCX_FWCTRL                       REG8(NPCX_MDC_BASE_ADDR + 0x007)
 #define NPCX_FWCTRL_RO_REGION             0
 #define NPCX_FWCTRL_FW_SLOT               1
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-
-/* TODO(b:179900857) Clean this up too */
-#undef IS_BIT_SET
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
 
 void system_jump_to_booter(void)
 {