zephyr/drivers: it8xxx2: add cros_bbram driver

This module provides 192 bytes of battery-backed memory area.

BUG=b:185202623
BRANCH=none
TEST=read and write the memory is normally.

Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: Iee606e8f6117d9cb3339def3a3fa51f5a83975c6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794022
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>

3 files changed, 86 insertions, 0 deletions

diff --git a/zephyr/drivers/cros_bbram/CMakeLists.txt b/zephyr/drivers/cros_bbram/CMakeLists.txt
index b96b76949f..5a539a5e61 100644
--- a/zephyr/drivers/cros_bbram/CMakeLists.txt
+++ b/zephyr/drivers/cros_bbram/CMakeLists.txt
@@ -2,4 +2,5 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+zephyr_library_sources_ifdef(CONFIG_CROS_BBRAM_IT8XXX2	cros_bbram_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_CROS_BBRAM_NPCX	cros_bbram_npcx.c)
diff --git a/zephyr/drivers/cros_bbram/Kconfig b/zephyr/drivers/cros_bbram/Kconfig
index 43850b032a..033d7926d6 100644
--- a/zephyr/drivers/cros_bbram/Kconfig
+++ b/zephyr/drivers/cros_bbram/Kconfig
@@ -22,3 +22,10 @@ config CROS_BBRAM_NPCX_INIT_PRIORITY
 	  SYSTEM_PRE_INIT_PRIORITY & lower than CROS_SYSTEM_NPCX_INIT_PRIORITY.
 
 endif # CROS_BBRAM_NPCX
+
+config CROS_BBRAM_IT8XXX2
+	bool "ITE IT81202 battery backed RAM driver for Zephyr"
+	depends on SOC_FAMILY_RISCV_ITE
+	default y
+	help
+	  This module provides 192 bytes of battery-backed memory area.
diff --git a/zephyr/drivers/cros_bbram/cros_bbram_it8xxx2.c b/zephyr/drivers/cros_bbram/cros_bbram_it8xxx2.c
new file mode 100644
index 0000000000..de8d8bf992
--- /dev/null
+++ b/zephyr/drivers/cros_bbram/cros_bbram_it8xxx2.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT ite_it8xxx2_cros_bbram
+
+#include <drivers/cros_bbram.h>
+#include <errno.h>
+#include <logging/log.h>
+#include <sys/util.h>
+
+LOG_MODULE_REGISTER(cros_bbram, LOG_LEVEL_ERR);
+
+/* Device config */
+struct cros_bbram_it8xxx2_config {
+	/* BBRAM base address */
+	uintptr_t base_addr;
+	/* BBRAM size (Unit:bytes) */
+	int size;
+};
+
+#define DRV_CONFIG(dev) \
+	((const struct cros_bbram_it8xxx2_config *)(dev)->config)
+
+static int cros_bbram_it8xxx2_read(const struct device *dev, int offset,
+				   int size, uint8_t *data)
+{
+	const struct cros_bbram_it8xxx2_config *config = DRV_CONFIG(dev);
+
+	if (offset < 0 || size < 1 || offset + size >= config->size) {
+		return -EFAULT;
+	}
+
+	for (size_t i = 0; i < size; ++i) {
+		*(data + i) =
+			*((volatile uint8_t *)config->base_addr + offset + i);
+	}
+	return 0;
+}
+
+static int cros_bbram_it8xxx2_write(const struct device *dev, int offset,
+				    int size, uint8_t *data)
+{
+	const struct cros_bbram_it8xxx2_config *config = DRV_CONFIG(dev);
+
+	if (offset < 0 || size < 1 || offset + size >= config->size) {
+		return -EFAULT;
+	}
+
+	for (size_t i = 0; i < size; ++i) {
+		*((volatile uint8_t *)config->base_addr + offset + i) =
+			*(data + i);
+	}
+	return 0;
+}
+
+static const struct cros_bbram_driver_api cros_bbram_it8xxx2_driver_api = {
+	.read = cros_bbram_it8xxx2_read,
+	.write = cros_bbram_it8xxx2_write,
+};
+
+static int bbram_it8xxx2_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+static const struct cros_bbram_it8xxx2_config cros_bbram_cfg = {
+	.base_addr = DT_INST_REG_ADDR_BY_NAME(0, memory),
+	.size = DT_INST_REG_SIZE_BY_NAME(0, memory),
+};
+
+DEVICE_DEFINE(cros_bbram_it8xxx2_0, DT_INST_LABEL(0), bbram_it8xxx2_init,
+	      NULL, NULL, &cros_bbram_cfg, PRE_KERNEL_1,
+	      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+	      &cros_bbram_it8xxx2_driver_api);