diff options
-rw-r--r-- | chip/lm4/watchdog.c | 2 | ||||
-rw-r--r-- | chip/stm32/hwtimer.c | 10 | ||||
-rw-r--r-- | chip/stm32/registers.h | 12 | ||||
-rw-r--r-- | include/common.h | 17 | ||||
-rw-r--r-- | include/task.h | 9 |
5 files changed, 31 insertions, 19 deletions
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c index 7bc7aa8a60..ef817cf715 100644 --- a/chip/lm4/watchdog.c +++ b/chip/lm4/watchdog.c @@ -48,7 +48,7 @@ void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void) "b task_resched_if_needed\n" : : [irq] "i" (LM4_IRQ_WATCHDOG)); } -const struct irq_priority IRQ_BUILD_NAME(prio_, LM4_IRQ_WATCHDOG, ) +const struct irq_priority IRQ_PRIORITY(LM4_IRQ_WATCHDOG) __attribute__((section(".rodata.irqprio"))) = {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest priority */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 6ac971f44d..abd2d2ba7b 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -51,14 +51,14 @@ #define STM32_TIM_TS_SLAVE_9_MASTER_3 1 #define STM32_TIM_TS_SLAVE_9_MASTER_10 2 #define STM32_TIM_TS_SLAVE_9_MASTER_11 3 -#define TSMAP1(slave, master) STM32_TIM_TS_SLAVE_ ## slave ## _MASTER_ ## master -#define TSMAP(slave, master) TSMAP1(slave, master) +#define TSMAP(slave, master) \ + CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master) /* * Timers are defined per board. This gives us flexibility to work around * timers which are dedicated to board-specific PWM sources. */ -#define IRQ_TIM(n) STM32_CAT(STM32_IRQ_TIM, n, ) +#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) #define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) #define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) #define IRQ_WD IRQ_TIM(TIM_WATCHDOG) @@ -66,7 +66,7 @@ /* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ #define STM32_IRQ_TIM1 STM32_IRQ_TIM1_UP_TIM16 -#define TIM_BASE(n) STM32_CAT(STM32_TIM, n, _BASE) +#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) #define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG) static uint32_t last_deadline; @@ -295,7 +295,7 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0, lr}\n" "b task_resched_if_needed\n"); } -const struct irq_priority IRQ_BUILD_NAME(prio_, IRQ_WD, ) +const struct irq_priority IRQ_PRIORITY(IRQ_WD) __attribute__((section(".rodata.irqprio"))) = {IRQ_WD, 0}; /* put the watchdog at the highest priority */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 48ebf1242b..0d7d14e9a2 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -10,9 +10,6 @@ #include "common.h" -/* concatenation helper */ -#define STM32_CAT(prefix, n, suffix) prefix ## n ## suffix - /* IRQ numbers */ #define STM32_IRQ_WWDG 0 #define STM32_IRQ_PVD 1 @@ -100,10 +97,9 @@ #define STM32_UART4_BASE 0x40004c00 /* STM32F100 and STM32F10x */ #define STM32_UART5_BASE 0x40005000 /* STM32F100 and STM32F10x */ -#define STM32_USART_BASE(n) STM32_CAT(STM32_USART, n, _BASE) +#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) -#define STM32_USART_REG(n, offset) \ - REG16(STM32_CAT(STM32_USART, n, _BASE) + (offset)) +#define STM32_USART_REG(n, offset) REG16(STM32_USART_BASE(n) + (offset)) #define STM32_USART_SR(n) STM32_USART_REG(n, 0x00) #define STM32_USART_SR_RXNE (1 << 5) @@ -122,7 +118,7 @@ #define STM32_USART_CR3_ONEBIT (1 << 11) /* STM32L only */ #define STM32_USART_GTPR(n) STM32_USART_REG(n, 0x18) -#define STM32_IRQ_USART(n) STM32_CAT(STM32_IRQ_USART, n, ) +#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) /* --- TIMERS --- */ #define STM32_TIM1_BASE 0x40012c00 /* STM32F100 and STM32F10x */ @@ -150,7 +146,7 @@ #define STM32_TIM17_BASE 0x40014800 /* STM32F100 only */ #define STM32_TIM_REG(n, offset) \ - REG16(STM32_CAT(STM32_TIM, n, _BASE) + (offset)) + REG16(CONCAT3(STM32_TIM, n, _BASE) + (offset)) #define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) #define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) diff --git a/include/common.h b/include/common.h index 1fb4fc5563..c6eeb11fef 100644 --- a/include/common.h +++ b/include/common.h @@ -10,6 +10,23 @@ #include <stdint.h> +/* + * Macros to concatenate 2 - 4 tokens together to form a single token. + * Multiple levels of nesting are required to convince the preprocessor to + * expand currently-defined tokens before concatenation. + * + * For example, if you have + * #define FOO 1 + * #define BAR1 42 + * Then + * #define BAZ CONCAT2(BAR, FOO) + * Will evaluate to BAR1, which then evaluates to 42. + */ +#define CONCAT_STAGE_1(w, x, y, z) w ## x ## y ## z +#define CONCAT2(w, x) CONCAT_STAGE_1(w, x, , ) +#define CONCAT3(w, x, y) CONCAT_STAGE_1(w, x, y, ) +#define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z) + /* Macros to access registers */ #define REG32(addr) (*(volatile uint32_t *)(addr)) #define REG16(addr) (*(volatile uint16_t *)(addr)) diff --git a/include/task.h b/include/task.h index ff3fe30f60..edf278c066 100644 --- a/include/task.h +++ b/include/task.h @@ -196,10 +196,9 @@ struct irq_priority { uint8_t priority; }; -/* Helper macros to build the IRQ handler name */ -#define IRQ_BUILD_NAME(prefix, irqnum, postfix) prefix ## irqnum ## postfix -#define IRQ_HANDLER(irqname) IRQ_BUILD_NAME(irq_,irqname,_handler) - +/* Helper macros to build the IRQ handler and priority struct names */ +#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler) +#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname) /* * Macro to connect the interrupt handler "routine" to the irq number "irq" and * ensure it is enabled in the interrupt controller with the right priority. @@ -212,7 +211,7 @@ struct irq_priority { routine(); \ task_resched_if_needed(ret); \ } \ - const struct irq_priority IRQ_BUILD_NAME(prio_, irq, ) \ + const struct irq_priority IRQ_PRIORITY(irq) \ __attribute__((section(".rodata.irqprio"))) \ = {irq, priority} |