diff options
-rw-r--r-- | core/riscv-rv32i/ec.lds.S | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index 1a979ddcaa..c9de979d78 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -47,6 +47,10 @@ MEMORY #else IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE #endif /* CHIP_FAMILY_IT8XXX2 */ + +#ifdef CONFIG_DRAM_BASE + DRAM (rwx) : ORIGIN = CONFIG_DRAM_BASE, LENGTH = CONFIG_DRAM_SIZE +#endif } SECTIONS @@ -359,6 +363,66 @@ SECTIONS #endif #endif /* CHIP_FAMILY_IT8XXX2 */ +#ifdef CONFIG_DRAM_BASE + /* + * Sections in DRAM region are constructed as like in non-DRAM regions: + * .dram.data LMA is for preserving initialized data across resets. + * The only difference is that they are all in the DRAM region: + * .dram.text | LOAD + * .dram.rodata | LOAD + * .dram.data LMA | LOAD + * .dram.data VMA | + * .dram.bss | NOLOAD + */ + + .dram.text : { + . = ALIGN(4); + KEEP(*(SORT(.dram.text.keep.*))) + *(SORT(.dram.text.*)) + . = ALIGN(4); + } > DRAM + + .dram.rodata : { + . = ALIGN(4); + KEEP(*(SORT(.dram.rodata.keep.*))) + *(SORT(.dram.rodata.*)) + . = ALIGN(4); + } > DRAM + + __dram_data_lma_start = ADDR(.dram.rodata) + SIZEOF(.dram.rodata); + + /* Place .dram.data LMA in between .dram.rodata and .dram.data VMA. */ + .dram.data __dram_data_lma_start + + (__dram_data_end - __dram_data_start) : { + . = ALIGN(4); + __dram_data_start = .; + *(.dram.data*) + . = ALIGN(4); + __dram_data_end = .; + + /* + * Normally, '> DRAM AT > DRAM' should be the same as '> DRAM', + * and they will be at the same address. However, if the address + * of VMA specified, LMA and VMA might have different addresses: + * '> DRAM' places VMA at the address where section declaration + * specified. + * 'AT > DRAM' places LMA at the location counter's address. + */ + } > DRAM AT > DRAM + + /* + * ld assigns correct attribute for .bss, but not for other .*.bss, + * we need an explicltly NOLOAD. + */ + .dram.bss(NOLOAD) : { + . = ALIGN(4); + __dram_bss_start = .; + *(SORT(.dram.bss*)) + . = ALIGN(4); + __dram_bss_end = .; + } > DRAM +#endif /* CONFIG_DRAM_BASE */ + #if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH)) /DISCARD/ : { *(.google) } #endif |