diff options
| -rw-r--r-- | core/riscv-rv32i/build.mk | 4 | ||||
| -rw-r--r-- | core/riscv-rv32i/math.c | 8 |
2 files changed, 12 insertions, 0 deletions
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index 76a318a500..df4e5e7ca9 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -14,6 +14,10 @@ $(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) # CPU specific compilation flags CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os +# RISC-V does not trap division by zero, enable the sanitizer to check those. +# TODO(b:173969773): It might be better to add a new compiler flag for this +# (e.g. -mcheck-zero-division that is only only available on MIPS currently). +CFLAGS_CPU+=-fsanitize=integer-divide-by-zero LDFLAGS_EXTRA+=-mrelax LDFLAGS_EXTRA+=-static-libgcc -lgcc diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c index 591a67eb8f..2a637c8bcc 100644 --- a/core/riscv-rv32i/math.c +++ b/core/riscv-rv32i/math.c @@ -4,6 +4,8 @@ */ #include "common.h" +#include "cpu.h" +#include "panic.h" #ifdef CONFIG_FPU /* Single precision floating point square root. */ @@ -17,3 +19,9 @@ float sqrtf(float x) return x; } #endif + +void __ubsan_handle_divrem_overflow(void *data, + void *lhs, void *rhs) +{ + exception_panic(PANIC_SW_DIV_ZERO, 0); +} |