diff options
-rw-r--r-- | chip/stm32/clock-stm32l4.c | 90 | ||||
-rw-r--r-- | chip/stm32/config-stm32l552xe.h | 4 | ||||
-rw-r--r-- | chip/stm32/registers-stm32l5.h | 206 |
3 files changed, 178 insertions, 122 deletions
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 2094751aab..4624013a16 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -463,42 +463,62 @@ void clock_enable_module(enum module_id module, int enable) new_mask = clock_mask & ~BIT_ULL(module); /* Only change clock if needed */ - if (new_mask != clock_mask) { - if (module == MODULE_ADC) { - STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN; - STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN; - - /* ADC select bit 28/29 */ - STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK; - STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 | - STM32_RCC_CCIPR_ADCSEL_1); - /* ADC clock enable */ - if (enable) - STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1; - else - STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1; - } else if (module == MODULE_SPI_FLASH) { - if (enable) - STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; - else - STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2; - } else if (module == MODULE_SPI || - module == MODULE_SPI_CONTROLLER) { - if (enable) - STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN; - else if ((new_mask & (BIT(MODULE_SPI) | - BIT(MODULE_SPI_CONTROLLER))) == 0) - STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN; - } else if (module == MODULE_USB) { -#if defined(STM32_RCC_APB1ENR2_USBFSEN) - if (enable) - STM32_RCC_APB1ENR2 |= - STM32_RCC_APB1ENR2_USBFSEN; - else - STM32_RCC_APB1ENR2 &= - ~STM32_RCC_APB1ENR2_USBFSEN; -#endif + if (new_mask == clock_mask) + return; + + if (module == MODULE_ADC) { + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN; + STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN; + + /* ADC select bit 28/29 */ + STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK; + STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 | + STM32_RCC_CCIPR_ADCSEL_1); + /* ADC clock enable */ + if (enable) + STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1; + else + STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1; + } else if (module == MODULE_SPI_FLASH) { + if (enable) + STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; + else + STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2; + } else if (module == MODULE_SPI || + module == MODULE_SPI_CONTROLLER) { + if (enable) + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN; + else if ((new_mask & (BIT(MODULE_SPI) | + BIT(MODULE_SPI_CONTROLLER))) == 0) + STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN; + } else if (module == MODULE_USB) { +#ifdef CHIP_FAMILY_STM32L5 + if (enable) { + /* Keep USB subsystem under reset for now. */ + STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST; + + /* Enable power to the USB domain. */ + STM32_PWR_CR2 |= STM32_PWR_CR2_USV; + + /* Enable internal 48 MHz RC oscillator. */ + wait_for_ready(&STM32_RCC_CRRCR, + STM32_RCC_CRRCR_HSI48ON, + STM32_RCC_CRRCR_HSI48RDY); + + /* Enable USB device clock. */ + STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_USBFSEN; + + /* 48 MHz clock is stable, release USB reset. */ + STM32_RCC_APB1RSTR2 &= ~STM32_RCC_APB1RSTR2_USBFSRST; + + } else { + STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_USBFSEN; + STM32_CRS_CR &= + ~(STM32_CRS_CR_CEN | STM32_CRS_CR_AUTOTRIMEN); + STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON; + STM32_PWR_CR2 &= ~STM32_PWR_CR2_USV; } +#endif } clock_mask = new_mask; diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h index 6953df3950..dab0400775 100644 --- a/chip/stm32/config-stm32l552xe.h +++ b/chip/stm32/config-stm32l552xe.h @@ -26,8 +26,8 @@ /* USB packet ram config */ #define CONFIG_USB_RAM_BASE 0x4000D800 #define CONFIG_USB_RAM_SIZE 1024 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 +#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t +#define CONFIG_USB_RAM_ACCESS_SIZE 2 #undef I2C_PORT_COUNT #define I2C_PORT_COUNT 4 diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index d418362fce..3a31b26ec9 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -141,6 +141,7 @@ #define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) #define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) #define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) #define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) #define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) #define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) @@ -359,6 +360,10 @@ #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) +#define STM32_PWR_CR2_USV_POS 10U +#define STM32_PWR_CR2_USV_MASK (0x7UL << STM32_PWR_CR2_USV_POS) +#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK + /* --- Macro usage in ec code --- */ #define STM32_RCC_AHB2ENR_GPIOMASK \ @@ -491,11 +496,17 @@ #define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) #define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) #define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_CCIPR STM32_RCC_CCIPR1 #define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) #define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) #define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) #define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C) #define STM32_RCC_PLLSAI1_SUPPORT #define STM32_RCC_PLLP_SUPPORT @@ -1691,90 +1702,91 @@ (0x1UL << STM32_RCC_APB2SMENR_DFSDM1SMEN_POS) #define STM32_RCC_APB2SMENR_DFSDM1SMEN STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK -/************* BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER ******************/ -#define STM32_RCC_CCIPR_USART1SEL_POS 0U -#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS) -#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK -#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS) -#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS) - -#define STM32_RCC_CCIPR_USART2SEL_POS 2U -#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS) -#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK -#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS) -#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS) - -#define STM32_RCC_CCIPR_USART3SEL_POS 4U -#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS) -#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK -#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS) -#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS) - -#define STM32_RCC_CCIPR_USART4SEL_POS 6U -#define STM32_RCC_CCIPR_USART4SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART4SEL_POS) -#define STM32_RCC_CCIPR_USART4SEL STM32_RCC_CCIPR_USART4SEL_MSK -#define STM32_RCC_CCIPR_USART4SEL_0 (0x1UL << STM32_RCC_CCIPR_USART4SEL_POS) -#define STM32_RCC_CCIPR_USART4SEL_1 (0x2UL << STM32_RCC_CCIPR_USART4SEL_POS) - -#define STM32_RCC_CCIPR_USART5SEL_POS 8U -#define STM32_RCC_CCIPR_USART5SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART5SEL_POS) -#define STM32_RCC_CCIPR_USART5SEL STM32_RCC_CCIPR_USART5SEL_MSK -#define STM32_RCC_CCIPR_USART5SEL_0 (0x1UL << STM32_RCC_CCIPR_USART5SEL_POS) -#define STM32_RCC_CCIPR_USART5SEL_1 (0x2UL << STM32_RCC_CCIPR_USART5SEL_POS) - -#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U -#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS) -#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK -#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS) -#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS) - -#define STM32_RCC_CCIPR_I2C1SEL_POS 12U -#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS) -#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK -#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS) -#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS) - -#define STM32_RCC_CCIPR_I2C2SEL_POS 14U -#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS) -#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK -#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS) -#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS) - -#define STM32_RCC_CCIPR_I2C3SEL_POS 16U -#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS) -#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK -#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS) -#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U -#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) -#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK -#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) -#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U -#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) -#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK -#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) -#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM3SEL_POS 22U -#define STM32_RCC_CCIPR_LPTIM3SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) -#define STM32_RCC_CCIPR_LPTIM3SEL STM32_RCC_CCIPR_LPTIM3SEL_MSK -#define STM32_RCC_CCIPR_LPTIM3SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) -#define STM32_RCC_CCIPR_LPTIM3SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) - -#define STM32_RCC_CCIPR_FDCANSEL_POS 24U -#define STM32_RCC_CCIPR_FDCANSEL_MSK (0x3UL << STM32_RCC_CCIPR_FDCANSEL_POS) -#define STM32_RCC_CCIPR_FDCANSEL STM32_RCC_CCIPR_FDCANSEL_MSK -#define STM32_RCC_CCIPR_FDCANSEL_0 (0x1UL << STM32_RCC_CCIPR_FDCANSEL_POS) -#define STM32_RCC_CCIPR_FDCANSEL_1 (0x2UL << STM32_RCC_CCIPR_FDCANSEL_POS) - -#define STM32_RCC_CCIPR_CLK48SEL_POS 26U -#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS) -#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK -#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS) -#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS) +/************* BIT DEFINITION FOR STM32_RCC_CCIPR1 REGISTER *****************/ +#define STM32_RCC_CCIPR1_USART1SEL_POS 0U +#define STM32_RCC_CCIPR1_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS) +#define STM32_RCC_CCIPR1_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK +#define STM32_RCC_CCIPR1_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS) +#define STM32_RCC_CCIPR1_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS) + +#define STM32_RCC_CCIPR1_USART2SEL_POS 2U +#define STM32_RCC_CCIPR1_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS) +#define STM32_RCC_CCIPR1_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK +#define STM32_RCC_CCIPR1_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS) +#define STM32_RCC_CCIPR1_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS) + +#define STM32_RCC_CCIPR1_USART3SEL_POS 4U +#define STM32_RCC_CCIPR1_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS) +#define STM32_RCC_CCIPR1_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK +#define STM32_RCC_CCIPR1_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS) +#define STM32_RCC_CCIPR1_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS) + +#define STM32_RCC_CCIPR1_USART4SEL_POS 6U +#define STM32_RCC_CCIPR1_USART4SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART4SEL_POS) +#define STM32_RCC_CCIPR1_USART4SEL STM32_RCC_CCIPR_USART4SEL_MSK +#define STM32_RCC_CCIPR1_USART4SEL_0 (0x1UL << STM32_RCC_CCIPR_USART4SEL_POS) +#define STM32_RCC_CCIPR1_USART4SEL_1 (0x2UL << STM32_RCC_CCIPR_USART4SEL_POS) + +#define STM32_RCC_CCIPR1_USART5SEL_POS 8U +#define STM32_RCC_CCIPR1_USART5SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART5SEL_POS) +#define STM32_RCC_CCIPR1_USART5SEL STM32_RCC_CCIPR_USART5SEL_MSK +#define STM32_RCC_CCIPR1_USART5SEL_0 (0x1UL << STM32_RCC_CCIPR_USART5SEL_POS) +#define STM32_RCC_CCIPR1_USART5SEL_1 (0x2UL << STM32_RCC_CCIPR_USART5SEL_POS) + +#define STM32_RCC_CCIPR1_LPUART1SEL_POS 10U +#define STM32_RCC_CCIPR1_LPUART1SEL_MSK \ + (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS) +#define STM32_RCC_CCIPR1_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK +#define STM32_RCC_CCIPR1_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS) +#define STM32_RCC_CCIPR1_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS) + +#define STM32_RCC_CCIPR1_I2C1SEL_POS 12U +#define STM32_RCC_CCIPR1_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS) +#define STM32_RCC_CCIPR1_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK +#define STM32_RCC_CCIPR1_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS) +#define STM32_RCC_CCIPR1_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS) + +#define STM32_RCC_CCIPR1_I2C2SEL_POS 14U +#define STM32_RCC_CCIPR1_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS) +#define STM32_RCC_CCIPR1_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK +#define STM32_RCC_CCIPR1_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS) +#define STM32_RCC_CCIPR1_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS) + +#define STM32_RCC_CCIPR1_I2C3SEL_POS 16U +#define STM32_RCC_CCIPR1_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS) +#define STM32_RCC_CCIPR1_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK +#define STM32_RCC_CCIPR1_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS) +#define STM32_RCC_CCIPR1_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS) + +#define STM32_RCC_CCIPR1_LPTIM1SEL_POS 18U +#define STM32_RCC_CCIPR1_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) +#define STM32_RCC_CCIPR1_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK +#define STM32_RCC_CCIPR1_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) +#define STM32_RCC_CCIPR1_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) + +#define STM32_RCC_CCIPR1_LPTIM2SEL_POS 20U +#define STM32_RCC_CCIPR1_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) +#define STM32_RCC_CCIPR1_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK +#define STM32_RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) +#define STM32_RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) + +#define STM32_RCC_CCIPR1_LPTIM3SEL_POS 22U +#define STM32_RCC_CCIPR1_LPTIM3SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) +#define STM32_RCC_CCIPR1_LPTIM3SEL STM32_RCC_CCIPR_LPTIM3SEL_MSK +#define STM32_RCC_CCIPR1_LPTIM3SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) +#define STM32_RCC_CCIPR1_LPTIM3SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) + +#define STM32_RCC_CCIPR1_FDCANSEL_POS 24U +#define STM32_RCC_CCIPR1_FDCANSEL_MSK (0x3UL << STM32_RCC_CCIPR_FDCANSEL_POS) +#define STM32_RCC_CCIPR1_FDCANSEL STM32_RCC_CCIPR_FDCANSEL_MSK +#define STM32_RCC_CCIPR1_FDCANSEL_0 (0x1UL << STM32_RCC_CCIPR_FDCANSEL_POS) +#define STM32_RCC_CCIPR1_FDCANSEL_1 (0x2UL << STM32_RCC_CCIPR_FDCANSEL_POS) + +#define STM32_RCC_CCIPR1_CLK48SEL_POS 26U +#define STM32_RCC_CCIPR1_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS) +#define STM32_RCC_CCIPR1_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK +#define STM32_RCC_CCIPR1_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS) +#define STM32_RCC_CCIPR1_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS) #define STM32_RCC_CCIPR_ADCSEL_POS 28U #define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS) @@ -1880,6 +1892,30 @@ /************** Bit definition for STM32_RCC_CCIPR2 register ****************/ /* TODO */ +/************** Bit definition for STM32_CRS_CR register ********************/ +#define STM32_CRS_CR_SYNCOKIE_POS 0U +#define STM32_CRS_CR_SYNCOKIE_MSK (0x1UL << STM32_CRS_CR_SYNCOKIE_POS) +#define STM32_CRS_CR_SYNCOKIE STM32_CRS_CR_SYNCOKIE_MSK +#define STM32_CRS_CR_SYNCWARNIE_POS 1U +#define STM32_CRS_CR_SYNCWARNIE_MSK (0x1UL << STM32_CRS_CR_SYNCWARNIE_POS) +#define STM32_CRS_CR_SYNCWARNIE STM32_CRS_CR_SYNCWARNIE_MSK +#define STM32_CRS_CR_SYNCERRIE_POS 2U +#define STM32_CRS_CR_SYNCERRIE_MSK (0x1UL << STM32_CRS_CR_SYNCERRIE_POS) +#define STM32_CRS_CR_SYNCERRIE STM32_CRS_CR_SYNCERRIE_MSK +#define STM32_CRS_CR_SYNCIE_POS 3U +#define STM32_CRS_CR_SYNCIE_MSK (0x1UL << STM32_CRS_CR_SYNCIE_POS) +#define STM32_CRS_CR_SYNCIE STM32_CRS_CR_SYNCIE_MSK +#define STM32_CRS_CR_CEN_POS 5U +#define STM32_CRS_CR_CEN_MSK (0x1UL << STM32_CRS_CR_CEN_POS) +#define STM32_CRS_CR_CEN STM32_CRS_CR_CEN_MSK +#define STM32_CRS_CR_AUTOTRIMEN_POS 6U +#define STM32_CRS_CR_AUTOTRIMEN_MSK (0x1UL << STM32_CRS_CR_AUTOTRIMEN_POS) +#define STM32_CRS_CR_AUTOTRIMEN STM32_CRS_CR_AUTOTRIMEN_MSK +#define STM32_CRS_CR_SWSYNC_POS 7U +#define STM32_CRS_CR_SWSYNC_MSK (0x1UL << STM32_CRS_CR_SWSYNC_POS) +#define STM32_CRS_CR_SWSYNC STM32_CRS_CR_SWSYNC_MSK + + /*!< HSI48CAL configuration */ #define STM32_RCC_CRRCR_HSI48CAL_POS 7U |