diff options
33 files changed, 148 insertions, 301 deletions
diff --git a/board/samus/board.c b/board/samus/board.c index 32fef8ff26..37ecbfeee3 100644 --- a/board/samus/board.c +++ b/board/samus/board.c @@ -26,7 +26,6 @@ #include "hooks.h" #include "host_command.h" #include "i2c.h" -#include "jtag.h" #include "keyboard_scan.h" #include "lid_switch.h" #include "lightbar.h" @@ -39,6 +38,7 @@ #include "pwm_chip.h" #include "registers.h" #include "switch.h" +#include "system.h" #include "task.h" #include "temp_sensor.h" #include "temp_sensor_chip.h" @@ -422,3 +422,22 @@ struct motion_sensor_t motion_sensors[] = { }; const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); + +#ifdef CONFIG_LOW_POWER_IDLE +void jtag_interrupt(enum gpio_signal signal) +{ + /* + * This interrupt is the first sign someone is trying to use + * the JTAG. Disable slow speed sleep so that the JTAG action + * can take place. + */ + disable_sleep(SLEEP_MASK_JTAG); + + /* + * Once we get this interrupt, disable it from occurring again + * to avoid repeated interrupts when debugging via JTAG. + */ + gpio_disable_interrupt(GPIO_JTAG_TCK); +} +#endif /* CONFIG_LOW_POWER_IDLE */ + diff --git a/board/samus/board.h b/board/samus/board.h index 82dc062518..26c06b46af 100644 --- a/board/samus/board.h +++ b/board/samus/board.h @@ -198,6 +198,9 @@ void board_reset_pd_mcu(void); /* Backboost detected interrupt */ void bkboost_det_interrupt(enum gpio_signal signal); +/* Interrupt handler for JTAG clock */ +void jtag_interrupt(enum gpio_signal signal); + /* Bit masks for turning on PP5000 rail in G3 */ #define PP5000_IN_G3_AC (1 << 0) #define PP5000_IN_G3_LIGHTBAR (1 << 1) diff --git a/chip/g/build.mk b/chip/g/build.mk index d3a228cdd3..cedba7d95b 100644 --- a/chip/g/build.mk +++ b/chip/g/build.mk @@ -20,7 +20,7 @@ CPPFLAGS += -I$(CRYPTOCLIB)/include endif # Required chip modules -chip-y = clock.o gpio.o hwtimer.o jtag.o pre_init.o system.o +chip-y = clock.o gpio.o hwtimer.o pre_init.o system.o chip-$(CONFIG_BOARD_ID_SUPPORT) += board_id.o ifeq ($(CONFIG_POLLING_UART),y) chip-y += polling_uart.o diff --git a/chip/g/jtag.c b/chip/g/jtag.c deleted file mode 100644 index 6d700d9680..0000000000 --- a/chip/g/jtag.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -void jtag_pre_init(void) -{ -} diff --git a/chip/ish/build.mk b/chip/ish/build.mk index 2206426757..a2f015f270 100644 --- a/chip/ish/build.mk +++ b/chip/ish/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright (c) 2016 The Chromium OS Authors. All rights reserved. +# Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # @@ -17,7 +17,7 @@ include core/$(CORE)/build.mk endif # Required chip modules -chip-y+=clock.o gpio.o jtag.o system.o hwtimer.o uart.o flash.o +chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o chip-$(CONFIG_I2C)+=i2c.o chip-$(CONFIG_LPC)+=ipc.o chip-$(CONFIG_WATCHDOG)+=watchdog.o diff --git a/chip/ish/jtag.c b/chip/ish/jtag.c deleted file mode 100644 index 168364b6e1..0000000000 --- a/chip/ish/jtag.c +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* Not implemented yet */ -} diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk index 97f41ce287..69832c2de6 100644 --- a/chip/it83xx/build.mk +++ b/chip/it83xx/build.mk @@ -12,7 +12,7 @@ CORE:=nds32 CFLAGS_CPU+=-mno-gp-direct # Required chip modules -chip-y=hwtimer.o uart.o gpio.o system.o jtag.o clock.o irq.o intc.o +chip-y=hwtimer.o uart.o gpio.o system.o clock.o irq.o intc.o # Optional chip modules chip-$(CONFIG_WATCHDOG)+=watchdog.o diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index 58cfe37541..41509b3563 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -109,6 +109,9 @@ #define CONFIG_SPI #define CONFIG_SWITCH +/* Chip needs to do custom pre-init */ +#define CONFIG_CHIP_PRE_INIT + #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) diff --git a/chip/it83xx/jtag.c b/chip/it83xx/jtag.c deleted file mode 100644 index 1943e0a031..0000000000 --- a/chip/it83xx/jtag.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "gpio.h" -#include "jtag.h" -#include "registers.h" -#include "system.h" - -void jtag_pre_init(void) -{ - /* bit4, enable debug mode through SMBus */ - IT83XX_SMB_SLVISELR &= ~(1 << 4); -} diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 0ad1be657b..ddd8b048f0 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -101,6 +101,12 @@ int system_is_reboot_warm(void) return 1; } +void chip_pre_init(void) +{ + /* bit4, enable debug mode through SMBus */ + IT83XX_SMB_SLVISELR &= ~(1 << 4); +} + void system_pre_init(void) { /* No initialization required */ diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk index 3253ebd478..8adde58abd 100644 --- a/chip/lm4/build.mk +++ b/chip/lm4/build.mk @@ -12,7 +12,7 @@ CORE:=cortex-m CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 # Required chip modules -chip-y=clock.o gpio.o hwtimer.o jtag.o system.o uart.o +chip-y=clock.o gpio.o hwtimer.o system.o uart.o # Optional chip modules chip-$(CONFIG_ADC)+=adc.o chip_temp_sensor.o diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 31ee2f6b9b..64dfb99dc6 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -98,6 +98,9 @@ #define CONFIG_SWITCH #define CONFIG_MPU +/* Chip needs to do custom pre-init */ +#define CONFIG_CHIP_PRE_INIT + #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) diff --git a/chip/lm4/jtag.c b/chip/lm4/jtag.c deleted file mode 100644 index a3867aa0f6..0000000000 --- a/chip/lm4/jtag.c +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "gpio.h" -#include "jtag.h" -#include "registers.h" -#include "system.h" - -void jtag_pre_init(void) -{ - /* Enable clocks to GPIO block C in run and sleep modes. */ - clock_enable_peripheral(CGC_OFFSET_GPIO, 0x0004, CGC_MODE_ALL); - - /* - * Ensure PC0:3 are set to JTAG function. They should be set this way - * on a cold boot, but on a warm reboot a previous misbehaving image - * could have set them differently. - */ - if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) && - ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) && - ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) && - ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f)) - return; /* Already properly configured */ - - /* Unlock commit register for JTAG pins */ - LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK; - LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f; - - /* Reset JTAG pins */ - LM4_GPIO_PCTL(LM4_GPIO_C) = - (LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111; - LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f; - LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f; - LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f; - - /* Set interrupt on either edge of the JTAG signals */ - LM4_GPIO_IS(LM4_GPIO_C) &= ~0x0f; - LM4_GPIO_IBE(LM4_GPIO_C) |= 0x0f; - - /* Re-lock commit register */ - LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f; - LM4_GPIO_LOCK(LM4_GPIO_C) = 0; -} - -#ifdef CONFIG_LOW_POWER_IDLE -void jtag_interrupt(enum gpio_signal signal) -{ - /* - * This interrupt is the first sign someone is trying to use - * the JTAG. Disable slow speed sleep so that the JTAG action - * can take place. - */ - disable_sleep(SLEEP_MASK_JTAG); - - /* - * Once we get this interrupt, disable it from occurring again - * to avoid repeated interrupts when debugging via JTAG. - */ - gpio_disable_interrupt(GPIO_JTAG_TCK); -} -#endif /* CONFIG_LOW_POWER_IDLE */ - diff --git a/chip/lm4/system.c b/chip/lm4/system.c index 684b520dae..625a4076e2 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -388,6 +388,42 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) hibernate(seconds, microseconds, HIBDATA_WAKE_PIN); } +void chip_pre_init(void) +{ + /* Enable clocks to GPIO block C in run and sleep modes. */ + clock_enable_peripheral(CGC_OFFSET_GPIO, 0x0004, CGC_MODE_ALL); + + /* + * Ensure PC0:3 are set to JTAG function. They should be set this way + * on a cold boot, but on a warm reboot a previous misbehaving image + * could have set them differently. + */ + if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) && + ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) && + ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) && + ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f)) + return; /* Already properly configured */ + + /* Unlock commit register for JTAG pins */ + LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK; + LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f; + + /* Reset JTAG pins */ + LM4_GPIO_PCTL(LM4_GPIO_C) = + (LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111; + LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f; + LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f; + LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f; + + /* Set interrupt on either edge of the JTAG signals */ + LM4_GPIO_IS(LM4_GPIO_C) &= ~0x0f; + LM4_GPIO_IBE(LM4_GPIO_C) |= 0x0f; + + /* Re-lock commit register */ + LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f; + LM4_GPIO_LOCK(LM4_GPIO_C) = 0; +} + void system_pre_init(void) { uint32_t hibctl; diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk index 615697be0b..14726e9705 100644 --- a/chip/mec1322/build.mk +++ b/chip/mec1322/build.mk @@ -17,7 +17,7 @@ include core/$(CORE)/build.mk endif # Required chip modules -chip-y=clock.o gpio.o hwtimer.o system.o uart.o jtag.o port80.o +chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_FANS)+=fan.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o diff --git a/chip/mec1322/jtag.c b/chip/mec1322/jtag.c deleted file mode 100644 index fdc2ed63cd..0000000000 --- a/chip/mec1322/jtag.c +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* Not implemented yet */ -} diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index fc6ea0e765..f228a13de1 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -17,7 +17,7 @@ CHIP_FAMILY:=npcx5 endif # Required chip modules -chip-y=header.o clock.o gpio.o hwtimer.o jtag.o system.o uart.o +chip-y=header.o clock.o gpio.o hwtimer.o system.o uart.o chip-y+=system-$(CHIP_FAMILY).o # Optional chip modules diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 90bfc9ab44..959b75b066 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -68,6 +68,9 @@ #define CONFIG_SWITCH #define CONFIG_MPU +/* Chip needs to do custom pre-init */ +#define CONFIG_CHIP_PRE_INIT + #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) diff --git a/chip/npcx/jtag.c b/chip/npcx/jtag.c deleted file mode 100644 index 692c278a8f..0000000000 --- a/chip/npcx/jtag.c +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "gpio.h" -#include "jtag.h" -#include "registers.h" -#include "system.h" - -void jtag_pre_init(void) -{ - /* Setting for fixing JTAG issue */ - NPCX_DBGCTRL = 0x04; - /* Enable automatic freeze mode */ - CLEAR_BIT(NPCX_DBGFRZEN3, NPCX_DBGFRZEN3_GLBL_FRZ_DIS); - - /* - * Enable JTAG functionality by SW without pulling down strap-pin - * nJEN0 or nJEN1 during ec POWERON or VCCRST reset occurs. - * Please notice it will change pinmux to JTAG directly. - */ -#ifdef NPCX_ENABLE_JTAG -#if NPCX_JTAG_MODULE2 - CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN1_EN); -#else - CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN0_EN); -#endif -#endif -} diff --git a/chip/npcx/system.c b/chip/npcx/system.c index a81c3cd383..012a508208 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -632,6 +632,27 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) #endif } +void chip_pre_init(void) +{ + /* Setting for fixing JTAG issue */ + NPCX_DBGCTRL = 0x04; + /* Enable automatic freeze mode */ + CLEAR_BIT(NPCX_DBGFRZEN3, NPCX_DBGFRZEN3_GLBL_FRZ_DIS); + + /* + * Enable JTAG functionality by SW without pulling down strap-pin + * nJEN0 or nJEN1 during ec POWERON or VCCRST reset occurs. + * Please notice it will change pinmux to JTAG directly. + */ +#ifdef NPCX_ENABLE_JTAG +#if NPCX_JTAG_MODULE2 + CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN1_EN); +#else + CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_5), NPCX_DEVALT5_NJEN0_EN); +#endif +#endif +} + void system_pre_init(void) { /* diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk index 5680f10d91..e5d8ed1b29 100644 --- a/chip/nrf51/build.mk +++ b/chip/nrf51/build.mk @@ -11,7 +11,7 @@ CORE:=cortex-m0 CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0 chip-y+=gpio.o system.o uart.o -chip-y+=jtag.o watchdog.o ppi.o +chip-y+=watchdog.o ppi.o chip-$(CONFIG_BLUETOOTH_LE)+=radio.o bluetooth_le.o chip-$(CONFIG_BLUETOOTH_LE_RADIO_TEST)+=radio_test.o diff --git a/chip/nrf51/jtag.c b/chip/nrf51/jtag.c deleted file mode 100644 index 6c2ee03323..0000000000 --- a/chip/nrf51/jtag.c +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -void jtag_pre_init(void) -{ -} diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk index c339885816..da16ea3a19 100644 --- a/chip/stm32/build.mk +++ b/chip/stm32/build.mk @@ -29,7 +29,7 @@ DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4),-stm32f4,) chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o chip-$(CONFIG_COMMON_RUNTIME)+=system.o -chip-y+=jtag-$(CHIP_FAMILY).o clock-$(CHIP_FAMILY).o +chip-y+=clock-$(CHIP_FAMILY).o ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4)) chip-y+=clock-f.o endif diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index fc8174bc47..43769cf2bf 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -124,6 +124,9 @@ /* Flash protection applies to the next boot, not the current one */ #define CONFIG_FLASH_PROTECT_NEXT_BOOT +/* Chip needs to do custom pre-init */ +#define CONFIG_CHIP_PRE_INIT + #define GPIO_NAME_BY_PIN(port, index) #port#index #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) diff --git a/chip/stm32/jtag-stm32f0.c b/chip/stm32/jtag-stm32f0.c deleted file mode 100644 index 0bf9540622..0000000000 --- a/chip/stm32/jtag-stm32f0.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* - * Stop all timers we might use (TIM1-3,14-17) and watchdogs when - * the JTAG stops the CPU. - */ - STM32_DBGMCU_APB1FZ |= - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - STM32_DBGMCU_APB2FZ |= STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | - STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; -} diff --git a/chip/stm32/jtag-stm32f3.c b/chip/stm32/jtag-stm32f3.c deleted file mode 100644 index d8f03b5eef..0000000000 --- a/chip/stm32/jtag-stm32f3.c +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* - * Stop all timers we might use and watchdogs when the JTAG stops - * the CPU. - */ - STM32_DBGMCU_APB1FZ |= - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - STM32_DBGMCU_APB2FZ |= - STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; -} diff --git a/chip/stm32/jtag-stm32f4.c b/chip/stm32/jtag-stm32f4.c deleted file mode 100644 index fb6431214d..0000000000 --- a/chip/stm32/jtag-stm32f4.c +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* - * Stop all timers we might use (TIM1-8) and watchdogs when - * the JTAG stops the CPU. - */ - /* TODO(nsanders): Implement this if someone needs jtag. */ -} diff --git a/chip/stm32/jtag-stm32l.c b/chip/stm32/jtag-stm32l.c deleted file mode 100644 index f4ac4b0ae8..0000000000 --- a/chip/stm32/jtag-stm32l.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* - * Stop all timers we might use (TIM2-4,9-11) and watchdogs when - * the JTAG stops the CPU. - */ - STM32_DBGMCU_APB1FZ |= - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - STM32_DBGMCU_APB2FZ |= STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | - STM32_RCC_PB2_TIM11; -} diff --git a/chip/stm32/jtag-stm32l4.c b/chip/stm32/jtag-stm32l4.c deleted file mode 100644 index 44fb9972e3..0000000000 --- a/chip/stm32/jtag-stm32l4.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Settings to enable JTAG debugging */ - -#include "jtag.h" -#include "registers.h" - -void jtag_pre_init(void) -{ - /* - * Stop all timers we might use (TIM1-8) and watchdogs when - * the JTAG stops the CPU. - */ - STM32_DBGMCU_APB1FZ |= - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - STM32_DBGMCU_APB2FZ |= STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; -} diff --git a/chip/stm32/system.c b/chip/stm32/system.c index c40790be40..d0c69101ef 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -175,6 +175,47 @@ static void check_reset_cause(void) system_set_reset_flags(flags); } +/* Stop all timers and WDGs we might use when JTAG stops the CPU. */ +void chip_pre_init(void) +{ + uint32_t apb1fz_reg = 0; + uint32_t apb2fz_reg = 0; + +#if defined(CHIP_FAMILY_STM32F0) + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | + STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | + STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; +#elif defined(CHIP_FAMILY_STM32F3) + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | + STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = + STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; +#elif defined(CHIP_FAMILY_STM32F4) + /* TODO(nsanders): Implement this if someone needs jtag. */ +#elif defined(CHIP_FAMILY_STM32L4) + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | + STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; +#elif defined(CHIP_FAMILY_STM32L) + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | + STM32_RCC_PB2_TIM11; +#endif + + if (apb1fz_reg) + STM32_DBGMCU_APB1FZ |= apb1fz_reg; + if (apb2fz_reg) + STM32_DBGMCU_APB2FZ |= apb2fz_reg; +} + void system_pre_init(void) { #ifdef CONFIG_SOFTWARE_PANIC diff --git a/common/main.c b/common/main.c index 8a1c1dabb1..95ef89f798 100644 --- a/common/main.c +++ b/common/main.c @@ -16,7 +16,6 @@ #include "flash.h" #include "gpio.h" #include "hooks.h" -#include "jtag.h" #include "keyboard_scan.h" #ifdef CONFIG_MPU #include "mpu.h" @@ -64,8 +63,6 @@ test_mockable __keep int main(void) mpu_pre_init(); #endif - /* Configure the pin multiplexers and GPIOs */ - jtag_pre_init(); gpio_pre_init(); #ifdef CONFIG_BOARD_POST_GPIO_INIT diff --git a/core/host/disabled.c b/core/host/disabled.c index 679a1ab451..60b5d9f7ca 100644 --- a/core/host/disabled.c +++ b/core/host/disabled.c @@ -7,5 +7,4 @@ #define DISABLED(proto) proto { } -DISABLED(void jtag_pre_init(void)); DISABLED(void clock_init(void)); diff --git a/include/jtag.h b/include/jtag.h deleted file mode 100644 index cf927c2e2d..0000000000 --- a/include/jtag.h +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* JTAG interface for Chrome EC */ - -#ifndef __CROS_EC_JTAG_H -#define __CROS_EC_JTAG_H - -#include "common.h" -#include "gpio.h" - -/** - * Pre-initialize the JTAG module. - */ -void jtag_pre_init(void); - -#ifdef CONFIG_LOW_POWER_IDLE -/** - * Interrupt handler for JTAG clock. - * - * @param signal Signal which triggered the interrupt. - */ -void jtag_interrupt(enum gpio_signal signal); -#else -static inline void jtag_interrupt(enum gpio_signal signal) { } -#endif /* !CONFIG_LOW_POWER_IDLE */ - -#endif /* __CROS_EC_JTAG_H */ |