diff options
279 files changed, 8062 insertions, 2190 deletions
diff --git a/Makefile.toolchain b/Makefile.toolchain index 69a3c3b9f3..c2e952d43b 100644 --- a/Makefile.toolchain +++ b/Makefile.toolchain @@ -31,7 +31,6 @@ ifeq ($(cc-name),gcc) cxx-name:=g++ else cxx-name:=clang++ -CROSS_COMPILE_arm:=arm-none-eabi- endif # Try not to assume too much about optional tools and prefixes @@ -43,7 +42,7 @@ endif AR=$(CROSS_COMPILE)ar CC=$(CCACHE) $(CROSS_COMPILE)$(cc-name) CPP=$(CC) -E -CXX=$(CROSS_COMPILE)clang++ +CXX=$(CROSS_COMPILE)$(cxx-name) LD=$(CROSS_COMPILE)ld NM=$(CROSS_COMPILE)nm OBJCOPY=$(CROSS_COMPILE)objcopy diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c index 707533762b..7b9e3c2e00 100644 --- a/baseboard/brya/baseboard.c +++ b/baseboard/brya/baseboard.c @@ -26,8 +26,10 @@ __override void lid_angle_peripheral_enable(int enable) * ignore the lid angle, which might be faulty then * disable keyboard. */ +#ifdef CONFIG_TABLET_MODE if (tablet_get_mode()) enable = 0; +#endif if (enable) { keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE); diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c index 4d5ece38ca..e3e85539bf 100644 --- a/baseboard/brya/usb_pd_policy.c +++ b/baseboard/brya/usb_pd_policy.c @@ -75,6 +75,9 @@ int pd_set_power_supply_ready(int port) int board_vbus_source_enabled(int port) { + /* BJ port is always sink. */ + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return 0; return ppc_is_sourcing_vbus(port); } diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk index 976ff2c931..dff52adc93 100644 --- a/baseboard/guybrush/build.mk +++ b/baseboard/guybrush/build.mk @@ -12,4 +12,4 @@ CHIP_VARIANT:=npcx9m3f baseboard-y=baseboard.o baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-$(CONFIG_CBI_EEPROM)+=cbi.o
\ No newline at end of file +baseboard-$(CONFIG_CBI_EEPROM)+=cbi.o diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c index 683df43251..bdbeb36a3c 100644 --- a/baseboard/hatch/baseboard.c +++ b/baseboard/hatch/baseboard.c @@ -178,7 +178,7 @@ void board_hibernate(void) * To support hibernate from ectool, keyboard, and console, * ensure that the AP is fully shutdown before hibernating. */ -#ifdef HAS_TASK_CHIPSET +#ifdef CONFIG_AP_POWER_CONTROL chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); #endif diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c index 93e521e14a..4d97418d23 100644 --- a/baseboard/intelrvp/adlrvp.c +++ b/baseboard/intelrvp/adlrvp.c @@ -540,3 +540,20 @@ __override void board_pre_task_i2c_peripheral_init(void) /* Configure board specific retimer & mux */ configure_retimer_usbmux(); } + +/* + * ADL RVP has both ITE and FUSB based TCPC chips. By default, the PD + * state of a non-attached port remains in PD_DRP_TOGGLE_ON in active + * state. Also, FUSB TCPC chip does not support dual role auto toggle + * which contradicts the default set S0 state of PD_DRP_TOGGLE_ON, + * while ITE based TCPC can support dual role auto toggle. The + * default PD_DRP_TOGGLE_ON state in Active state doesnot allow TCPC + * ports to enter Low power mode. To fix the issue, added board + * specific code to disable the dual role toggle in S0. + * Note:For ITE based TCPC, low power mode entry does makes no + * difference, as it is controlled by ITE TCPC clk in deep sleepmode. + */ +__override enum pd_dual_role_states pd_get_drp_state_in_s0(void) +{ + return PD_DRP_TOGGLE_OFF; +} diff --git a/baseboard/kalista/build.mk b/baseboard/kalista/build.mk index 85270d4bd4..fb844b19f1 100644 --- a/baseboard/kalista/build.mk +++ b/baseboard/kalista/build.mk @@ -8,4 +8,4 @@ baseboard-y=baseboard.o baseboard-y+=led.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o
\ No newline at end of file +baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o usb_pd_pdo.o diff --git a/baseboard/nucleo-h743zi/build.mk b/baseboard/nucleo-h743zi/build.mk index e9f9ae3faa..470214aabc 100644 --- a/baseboard/nucleo-h743zi/build.mk +++ b/baseboard/nucleo-h743zi/build.mk @@ -11,4 +11,4 @@ CHIP:=stm32 CHIP_FAMILY:=stm32h7 CHIP_VARIANT:=stm32h7x3 -baseboard-y=base-board.o
\ No newline at end of file +baseboard-y=base-board.o diff --git a/board/agah/board.c b/board/agah/board.c index e3a9e1b93e..d1cc519402 100644 --- a/board/agah/board.c +++ b/board/agah/board.c @@ -52,6 +52,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); static void board_init(void) { gpio_enable_interrupt(GPIO_PG_PP3300_S5_OD); + gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/agah/board.h b/board/agah/board.h index 9b9998d6a8..7655f9a4fe 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -51,6 +51,7 @@ /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_TCPM_RT1715 #undef CONFIG_USB_PD_TCPM_NCT38XX +#define CONFIG_USBC_RETIMER_PS8818 /* I2C speed console command */ #define CONFIG_CMD_I2C_SPEED @@ -138,10 +139,15 @@ /* Charger defines */ #define CONFIG_CHARGER_ISL9241 -#define CONFIG_CHARGE_RAMP_SW #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +/* Barrel jack adapter settings */ +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 +/* This is the next available port # after USB-C ports. */ +#define DEDICATED_CHARGE_PORT 2 + /* * Older boards have a different ADC assignment. */ @@ -197,6 +203,12 @@ enum mft_channel { MFT_CH_COUNT }; +enum charge_port { + CHARGE_PORT_TYPEC0, + CHARGE_PORT_TYPEC1, + CHARGE_PORT_BARRELJACK, +}; + /** * Interrupt handler for PG_PP3300_S5_OD changes. * @@ -204,6 +216,9 @@ enum mft_channel { */ void board_power_interrupt(enum gpio_signal signal); +/* IRQ for BJ plug/unplug. */ +void bj_present_interrupt(enum gpio_signal signal); + #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ diff --git a/board/agah/charger_isl9241.c b/board/agah/charger_isl9241.c index 85e0de90fe..6f041a7455 100644 --- a/board/agah/charger_isl9241.c +++ b/board/agah/charger_isl9241.c @@ -6,18 +6,21 @@ #include "common.h" #include "charge_manager.h" +#include "charge_state.h" #include "charge_state_v2.h" #include "charger.h" #include "compile_time_macros.h" #include "console.h" #include "driver/charger/isl9241.h" +#include "gpio.h" +#include "hooks.h" +#include "stdbool.h" #include "usbc_ppc.h" #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -29,62 +32,227 @@ const struct charger_config_t chg_chips[] = { }; BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +static int board_disable_bj_port(void) +{ + gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1); + /* If the current port is BJ, disable bypass mode. */ + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_DEDICATED) + return charger_enable_bypass_mode(0, 0); + + CPRINTS("BJ power is disabled"); + + return EC_SUCCESS; +} + +static int board_enable_bj_port(void) +{ + if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) + return EC_ERROR_INVAL; + gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0); + + CPRINTS("BJ power is enabled"); + + return charger_enable_bypass_mode(0, 1); +} + +/* + * TODO: + * + * When AC is being plugged in (including switching source port), + * 1. Deassert NVIDIA_GPU_ACOFF_ODL. + * 2. Call evaluate_d_notify. + * + * When AC is being lost, + * 1. Assert NVIDIA_GPU_ACOFF_ODL. + * 2. Set D-Notify to D5. + * 3. Differ-call + * a. Deassert NVIDIA_GPU_ACOFF_ODL. + * b. evaluate_d_notify + */ +static int board_throttle_ap_gpu(bool enable) +{ + int rv = EC_SUCCESS; + + if (!chipset_in_state(CHIPSET_STATE_ON)) + return EC_SUCCESS; + + CPRINTS("TODO: %s to %s AP & GPU (%d)", rv ? "Failed" : "Succeeded", + enable ? "throttle" : "unthrottle", rv); + + return rv; +} + +/* Disable all VBUS sink ports except <port>. <port> = -1 disables all ports. */ +static int board_disable_vbus_sink(int port) +{ + int i, r, rv = EC_SUCCESS; + + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + /* + * Do not return early if one fails otherwise we can get into a + * boot loop assertion failure. + */ + r = ppc_vbus_sink_enable(i, 0); + CPRINTS("%s to disable sink path C%d (%d).", + r ? "Failed" : "Succeeded", i, r); + rv |= r; + } + + return rv; +} + +/* Minimum battery SoC required for switching source port. */ +#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1 + +/* + * It should also work on POR with/without a battery: + * + * 1. EC gathers power info of all ports. + * 2. Identify the highest power port. + * 3. If + * 1. battery soc = 0% --> Exit + * 2. BJ_ADP_PRESENT_ODL = 1 --> Exit + * 3. highest power port == active port --> Exit + * 4. If + * 1. in S0, throttle AP & GPU to the DC rating. + * 5. Turn off the current active port. + * 6. Turn on the highest power port. + * 7. If + * 1. in S0, throttle AP & GPU back. + * + * TODO: Are the following cases covered? + * 1. Two AC adapters are plugged. Then, the active adapter is removed. + * + * TODO: Recover from incomplete execution: + * 1. Failed to turn on/off PPC. + */ int board_set_active_charge_port(int port) { - int is_valid_port = board_is_usb_pd_port_present(port); - int i; + enum charge_supplier supplier = charge_manager_get_supplier(); + int active_port = charge_manager_get_active_charge_port(); + + CPRINTS("Changing charge port to %d (current port=%d supplier=%d)", + port, active_port, supplier); if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } + CPRINTS("Disabling all charger ports"); + + board_throttle_ap_gpu(1); + + board_disable_bj_port(); + board_disable_vbus_sink(-1); return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); + if (port < 0 || CHARGE_PORT_COUNT <= port) { + return EC_ERROR_INVAL; + } else if (port == active_port) { + return EC_SUCCESS; + } else if (board_vbus_source_enabled(port)) { + /* Don't charge from a USBC source port */ + CPRINTS("Don't enable C%d. It's sourcing.", port); return EC_ERROR_INVAL; } - CPRINTSUSB("New charge port: C%d", port); - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. + * We need to check the battery if we're switching a source port. If + * we're just starting up or no AC was previously plugged, we shouldn't + * check the battery. Both cases can be caught by supplier == NONE. */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); + if (supplier != CHARGE_SUPPLIER_NONE) { + if (charge_get_percent() < MIN_BATT_FOR_SWITCHING_SOURCE_PORT) + return EC_ERROR_NOT_POWERED; } - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; + /* Turn off other ports' sink paths before enabling requested port. */ + if (port == CHARGE_PORT_TYPEC0 || port == CHARGE_PORT_TYPEC1) { + /* + * BJ port is on POR. So, we need to turn it off even if we're + * not previously on BJ. + */ + board_disable_bj_port(); + if (board_disable_vbus_sink(port)) + return EC_ERROR_UNCHANGED; + + /* Enable requested USBC charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTS("Failed to enable sink path for C%d", port); + return EC_ERROR_UNKNOWN; + } + } else if (port == CHARGE_PORT_BARRELJACK) { + /* + * We can't proceed unless both ports are successfully + * disconnected as sources. + */ + if (board_disable_vbus_sink(-1)) + return EC_ERROR_UNKNOWN; + board_enable_bj_port(); } + /* Switching port is complete. Turn off throttling. */ + if (supplier != CHARGE_SUPPLIER_NONE) + board_throttle_ap_gpu(0); + + CPRINTS("New charger p%d", port); + return EC_SUCCESS; } -__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) { charge_set_input_current_limit(MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } + +static const struct charge_port_info bj_power = { + /* 150W (also default) */ + .voltage = 19500, + .current = 7700, +}; + +/* Debounce time for BJ plug/unplug */ +#define BJ_DEBOUNCE_MS 1000 + +static void bj_connect_deferred(void) +{ + static int8_t bj_connected = -1; + const struct charge_port_info *pi = NULL; + int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL); + + if (connected == bj_connected) + return; + + if (connected) + pi = &bj_power; + + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + DEDICATED_CHARGE_PORT, pi); + bj_connected = connected; + CPRINTS("BJ %s", connected ? "connected" : "disconnected"); +} +DECLARE_DEFERRED(bj_connect_deferred); + +void bj_present_interrupt(enum gpio_signal signal) +{ + hook_call_deferred(&bj_connect_deferred_data, BJ_DEBOUNCE_MS * MSEC); +} + +static void bj_state_init(void) +{ + /* + * Initialize all charge suppliers to 0. The charge manager waits until + * all ports have reported in before doing anything. + */ + for (int i = 0; i < CHARGE_PORT_COUNT; i++) { + for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++) + charge_manager_update_charge(j, i, NULL); + } + + bj_connect_deferred(); +} +DECLARE_HOOK(HOOK_INIT, bj_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1); diff --git a/board/agah/ec.tasklist b/board/agah/ec.tasklist index ea1f6e7e09..7286caf6c6 100644 --- a/board/agah/ec.tasklist +++ b/board/agah/ec.tasklist @@ -12,7 +12,6 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \ - TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \ TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \ diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index a1573f6290..41a8f2a4d8 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -26,6 +26,7 @@ GPIO_INT(PG_PP3300_S5_OD, PIN(B, 4), GPIO_INT_BOTH | GPIO_PULL_UP GPIO_INT(USB_C2_BC12_INT_ODL, PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(USB_C2_TCPC_INT_ODL, PIN(A, 7), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C2_PPC_INT_ODL, PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt) +GPIO_INT(BJ_ADP_PRESENT_ODL, PIN(5, 6), GPIO_INT_BOTH | GPIO_PULL_UP, bj_present_interrupt) /* USED GPIOs: */ GPIO(CCD_MODE_ODL, PIN(E, 5), GPIO_INPUT) @@ -68,8 +69,7 @@ GPIO(PG_PP3300_S5_EC_SEQ_OD, PIN(B, 5), GPIO_OUT_LOW) GPIO(USB_C2_FRS_EN, PIN(D, 4), GPIO_OUT_LOW) /* Barreljack */ -GPIO(EN_PPVAR_BJ_ADP, PIN(A, 2), GPIO_OUT_LOW) -GPIO(BJ_ADP_PRESENT_L, PIN(5, 6), GPIO_INPUT) +GPIO(EN_PPVAR_BJ_ADP_L, PIN(A, 2), GPIO_OUT_LOW) /* * The NPCX keyboard driver does not use named GPIOs to access @@ -128,4 +128,4 @@ UNUSED(PIN(7, 3)) /* GPIO73 */ UNUSED(PIN(4, 1)) /* GPIO41 */ UNUSED(PIN(5, 0)) /* GPIO50 */ UNUSED(PIN(6, 0)) /* GPIO60 */ -UNUSED(PIN(C, 2)) /* GPIOC2 */
\ No newline at end of file +UNUSED(PIN(C, 2)) /* GPIOC2 */ diff --git a/board/agah/usbc_config.c b/board/agah/usbc_config.c index d3d20c96c5..0902f2f799 100644 --- a/board/agah/usbc_config.c +++ b/board/agah/usbc_config.c @@ -14,6 +14,7 @@ #include "console.h" #include "driver/bc12/pi3usb9201_public.h" #include "driver/ppc/syv682x_public.h" +#include "driver/retimer/ps8818.h" #include "driver/tcpm/rt1715.h" #include "driver/tcpm/tcpci.h" #include "ec_commands.h" @@ -85,30 +86,86 @@ struct ppc_config_t ppc_chips[] = { unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); -/* USBC mux configuration - Alder Lake includes internal mux */ -static const struct usb_mux usbc0_tcss_usb_mux = { - .usb_port = USBC_PORT_C0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, +const static struct ps8818_reg_val equalizer_default_table[] = { + { + .reg = PS8818_REG1_APTX1EQ_10G_LEVEL, + .mask = PS8818_EQ_LEVEL_UP_MASK, + .val = PS8818_EQ_LEVEL_UP_19DB, + }, + { + .reg = PS8818_REG1_APTX2EQ_10G_LEVEL, + .mask = PS8818_EQ_LEVEL_UP_MASK, + .val = PS8818_EQ_LEVEL_UP_19DB, + }, + { + .reg = PS8818_REG1_APTX1EQ_5G_LEVEL, + .mask = PS8818_EQ_LEVEL_UP_MASK, + .val = PS8818_EQ_LEVEL_UP_19DB, + }, + { + .reg = PS8818_REG1_APTX2EQ_5G_LEVEL, + .mask = PS8818_EQ_LEVEL_UP_MASK, + .val = PS8818_EQ_LEVEL_UP_19DB, + }, + { + .reg = PS8818_REG1_RX_PHY, + .mask = PS8818_RX_INPUT_TERM_MASK, + .val = PS8818_RX_INPUT_TERM_112_OHM, + }, }; -static const struct usb_mux usbc2_tcss_usb_mux = { + +#define NUM_EQ_DEFAULT_ARRAY ARRAY_SIZE(equalizer_default_table) + +int board_ps8818_mux_set(const struct usb_mux *me, + mux_state_t mux_state) +{ + int rv = EC_SUCCESS; + int i; + + /* USB specific config */ + if (mux_state & USB_PD_MUX_USB_ENABLED) { + + /* Boost the USB gain */ + for (i = 0; i < NUM_EQ_DEFAULT_ARRAY; i++) + rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + equalizer_default_table[i].reg, + equalizer_default_table[i].mask, + equalizer_default_table[i].val); + } + + /* DP specific config */ + if (mux_state & USB_PD_MUX_DP_ENABLED) { + /* Boost the DP gain */ + rv |= ps8818_i2c_field_update8(me, + PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); + } + + return rv; +} + +const static struct usb_mux usbc2_ps8818 = { .usb_port = USBC_PORT_C2, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .i2c_port = I2C_PORT_USB_C2_TCPC, + .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, + .driver = &ps8818_usb_retimer_driver, + .board_set = &board_ps8818_mux_set, }; +/* USBC mux configuration - Alder Lake includes internal mux */ const struct usb_mux usb_muxes[] = { [USBC_PORT_C0] = { .usb_port = USBC_PORT_C0, .driver = &virtual_usb_mux_driver, .hpd_update = &virtual_hpd_update, - .next_mux = &usbc0_tcss_usb_mux, }, [USBC_PORT_C2] = { .usb_port = USBC_PORT_C2, .driver = &virtual_usb_mux_driver, .hpd_update = &virtual_hpd_update, - .next_mux = &usbc2_tcss_usb_mux, + .next_mux = &usbc2_ps8818, }, }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); diff --git a/board/agah/usbc_config.h b/board/agah/usbc_config.h index b9f2c2ffff..e5b7576d72 100644 --- a/board/agah/usbc_config.h +++ b/board/agah/usbc_config.h @@ -16,4 +16,10 @@ enum usbc_port { USBC_PORT_COUNT }; +struct ps8818_reg_val { + uint8_t reg; + uint8_t mask; + uint16_t val; +}; + #endif /* __CROS_EC_USBC_CONFIG_H */ diff --git a/board/banshee/board.c b/board/banshee/board.c index 4f2b06b448..8f1d8bb811 100644 --- a/board/banshee/board.c +++ b/board/banshee/board.c @@ -85,12 +85,20 @@ void board_init(void) if (board_id == 0) { /* keyboard_col2_inverted on board id 0 */ gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH); - gpio_set_alternate_function(GPIO_PORT_1, BIT(5), + gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH); + gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(5)), + GPIO_ALT_FUNC_DEFAULT); + } else if (board_id == 1) { + /* keyboard_col4_inverted on board id 1 */ + gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH); + gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH); + gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(7)), GPIO_ALT_FUNC_DEFAULT); } else { - /* keyboard_col4_inverted on board id 1 and later */ + /* keyboard_col5_inverted on board id 2 and later */ gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH); - gpio_set_alternate_function(GPIO_PORT_1, BIT(7), + gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH); + gpio_set_alternate_function(GPIO_PORT_1, (BIT(5) | BIT(7)), GPIO_ALT_FUNC_DEFAULT); } diff --git a/board/banshee/gpio.inc b/board/banshee/gpio.inc index 53c71f77e9..2a0e90e675 100644 --- a/board/banshee/gpio.inc +++ b/board/banshee/gpio.inc @@ -113,7 +113,7 @@ ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L /* KB alternate functions */ ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */ -ALTERNATE(PIN_MASK(1, 0x5F), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */ +ALTERNATE(PIN_MASK(1, 0x4F), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */ ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */ ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */ ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */ @@ -150,9 +150,11 @@ UNUSED(PIN(5, 7)) /* GPIO57/SER_IRQ/ESPI_ALERT_L */ * keyboard scan pins, so we do not list them in *gpio.inc. However, when * KEYBOARD_COL2_INVERTED is defined, this name is required. * + * GPIO14 needs to be inverted on BOARD ID 2 and later * GPIO15 needs to be inverted on BOARD ID 1 * GPIO17 needs to be inverted on BOARD ID 0 */ +GPIO(EC_KSO_05_INV, PIN(1, 4), GPIO_OUT_LOW) GPIO(EC_KSO_04_INV, PIN(1, 5), GPIO_OUT_LOW) GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) diff --git a/board/banshee/keyboard.c b/board/banshee/keyboard.c index 3bea4aeb40..3891955b46 100644 --- a/board/banshee/keyboard.c +++ b/board/banshee/keyboard.c @@ -25,7 +25,7 @@ __override struct keyboard_scan_config keyscan_config = { }, }; -static const struct ec_response_keybd_config banshee_kb = { +static const struct ec_response_keybd_config banshee_kb_id1 = { .num_top_row_keys = 12, .action_keys = { TK_BACK, /* T1 */ @@ -44,10 +44,32 @@ static const struct ec_response_keybd_config banshee_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; +static const struct ec_response_keybd_config banshee_kb_id2 = { + .num_top_row_keys = 12, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_KBD_BKLIGHT_TOGGLE, /* T8 */ + TK_PLAY_PAUSE, /* T9 */ + TK_VOL_MUTE, /* T10 */ + TK_VOL_DOWN, /* T11 */ + TK_VOL_UP, /* T12 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + __override const struct ec_response_keybd_config *board_vivaldi_keybd_config(void) { - return &banshee_kb; + if (get_board_id() <= 1) + return &banshee_kb_id1; + else + return &banshee_kb_id2; } /* diff --git a/board/banshee/keyboard_customization.c b/board/banshee/keyboard_customization.c index 0fdf8f8a9b..cf6904cb37 100644 --- a/board/banshee/keyboard_customization.c +++ b/board/banshee/keyboard_customization.c @@ -53,10 +53,14 @@ void board_id_keyboard_col_inverted(int board_id) /* keyboard_col2_inverted on board id 0 */ signal = GPIO_EC_KSO_02_INV; colinv = 2; - } else { - /* keyboard_col4_inverted on board id 1 and later */ + } else if (board_id == 1) { + /* keyboard_col4_inverted on board id 1 */ signal = GPIO_EC_KSO_04_INV; colinv = 4; + } else { + /* keyboard_col5_inverted on board id 2 and later */ + signal = GPIO_EC_KSO_05_INV; + colinv = 5; } } diff --git a/board/beadrix/board.c b/board/beadrix/board.c index a08daf5177..0fb2f9773b 100644 --- a/board/beadrix/board.c +++ b/board/beadrix/board.c @@ -10,8 +10,6 @@ #include "charge_manager.h" #include "charge_state_v2.h" #include "charger.h" -#include "driver/accel_kionix.h" -#include "driver/accelgyro_lsm6dsm.h" #include "driver/bc12/pi3usb9201.h" #include "driver/charger/isl923x.h" #include "driver/retimer/nb7v904m.h" @@ -225,12 +223,16 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; +static int board_nb7v904m_mux_set(const struct usb_mux *me, + mux_state_t mux_state); + /* USB Retimer */ const struct usb_mux usbc1_retimer = { .usb_port = 1, .i2c_port = I2C_PORT_SUB_USB_C1, .i2c_addr_flags = NB7V904M_I2C_ADDR0, .driver = &nb7v904m_usb_redriver_drv, + .board_set = &board_nb7v904m_mux_set, }; /* USB Muxes */ @@ -251,6 +253,91 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; +/* USB Mux */ +static int board_nb7v904m_mux_set(const struct usb_mux *me, + mux_state_t mux_state) +{ + int rv = EC_SUCCESS; + int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED); + + if (mux_state & USB_PD_MUX_USB_ENABLED) { + /* USB with DP */ + if (mux_state & USB_PD_MUX_DP_ENABLED) { + if (flipped) { /* CC2 */ + rv |= nb7v904m_tune_usb_set_eq(me, + NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_4_DB, + NB7V904M_CH_C_EQ_0_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, + NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_3P5_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match(me, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D); + } /* CC1 */ + else { + rv |= nb7v904m_tune_usb_set_eq(me, + NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_0_DB, + NB7V904M_CH_C_EQ_4_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, + NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_3P5_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match(me, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); + } + } else { + /* USB only */ + rv |= nb7v904m_tune_usb_set_eq(me, + NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_4_DB, + NB7V904M_CH_C_EQ_4_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, + NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_3P5_DB, + NB7V904M_CH_C_GAIN_3P5_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match(me, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); + } + + } else if (mux_state & USB_PD_MUX_DP_ENABLED) { + /* 4 lanes DP */ + rv |= nb7v904m_tune_usb_set_eq(me, + NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_0_DB, + NB7V904M_CH_C_EQ_0_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, + NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match(me, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D); + } + + return rv; +} + void board_init(void) { int on; @@ -269,8 +356,6 @@ void board_init(void) check_c1_line(); gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL); - /* Enable Base Accel interrupt */ - gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L); /* Turn on 5V if the system is on, otherwise turn it off. */ on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND | @@ -474,89 +559,6 @@ const struct pwm_t pwm_channels[] = { }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -/* Sensor Mutexes */ -static struct mutex g_lid_mutex; -static struct mutex g_base_mutex; - -/* Sensor Data */ -static struct kionix_accel_data g_kx022_data; -static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; - -/* Drivers */ -struct motion_sensor_t motion_sensors[] = { - [LID_ACCEL] = { - .name = "Lid Accel", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_KX022, - .type = MOTIONSENSE_TYPE_ACCEL, - .location = MOTIONSENSE_LOC_LID, - .drv = &kionix_accel_drv, - .mutex = &g_lid_mutex, - .drv_data = &g_kx022_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = KX022_ADDR1_FLAGS, - .rot_standard_ref = NULL, - .default_range = 2, /* g */ - /* We only use 2g because its resolution is only 8-bits */ - .min_frequency = KX022_ACCEL_MIN_FREQ, - .max_frequency = KX022_ACCEL_MAX_FREQ, - .config = { - [SENSOR_CONFIG_EC_S0] = { - .odr = 10000 | ROUND_UP_FLAG, - }, - [SENSOR_CONFIG_EC_S3] = { - .odr = 10000 | ROUND_UP_FLAG, - }, - }, - }, - [BASE_ACCEL] = { - .name = "Base Accel", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_LSM6DSM, - .type = MOTIONSENSE_TYPE_ACCEL, - .location = MOTIONSENSE_LOC_BASE, - .drv = &lsm6dsm_drv, - .mutex = &g_base_mutex, - .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, - MOTIONSENSE_TYPE_ACCEL), - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, - .rot_standard_ref = NULL, - .default_range = 4, /* g */ - .min_frequency = LSM6DSM_ODR_MIN_VAL, - .max_frequency = LSM6DSM_ODR_MAX_VAL, - .config = { - [SENSOR_CONFIG_EC_S0] = { - .odr = 13000 | ROUND_UP_FLAG, - .ec_rate = 100 * MSEC, - }, - [SENSOR_CONFIG_EC_S3] = { - .odr = 10000 | ROUND_UP_FLAG, - .ec_rate = 100 * MSEC, - }, - }, - }, - [BASE_GYRO] = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_LSM6DSM, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &lsm6dsm_drv, - .mutex = &g_base_mutex, - .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, - MOTIONSENSE_TYPE_GYRO), - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, - .default_range = 1000 | ROUND_UP_FLAG, /* dps */ - .rot_standard_ref = NULL, - .min_frequency = LSM6DSM_ODR_MIN_VAL, - .max_frequency = LSM6DSM_ODR_MAX_VAL, - }, -}; - -const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); - /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { [TEMP_SENSOR_1] = {.name = "Memory", diff --git a/board/beadrix/board.h b/board/beadrix/board.h index 2b0a85a0ee..6e7975fd14 100644 --- a/board/beadrix/board.h +++ b/board/beadrix/board.h @@ -44,20 +44,6 @@ /* PWM */ #define CONFIG_PWM -/* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ -#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -/* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) - -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* Power of 2 - Too large of a fifo causes too much timestamp jitter */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - /* TCPC */ #define CONFIG_USB_PD_TCPM_ANX7447 /* C1: MUX only*/ #define CONFIG_USB_PD_TCPM_MUX @@ -115,14 +101,6 @@ enum pwm_channel { PWM_CH_COUNT, }; -/* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; - /* ADC channels */ enum adc_channel { ADC_VSNS_PP3300_A, /* ADC0 */ diff --git a/board/beadrix/ec.tasklist b/board/beadrix/ec.tasklist index e201fb0b1c..74b7663d69 100644 --- a/board/beadrix/ec.tasklist +++ b/board/beadrix/ec.tasklist @@ -9,7 +9,6 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \ - TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \ diff --git a/board/beadrix/gpio.inc b/board/beadrix/gpio.inc index a7ca521e4b..b5e557f01f 100644 --- a/board/beadrix/gpio.inc +++ b/board/beadrix/gpio.inc @@ -37,7 +37,6 @@ GPIO_INT(USB_C0_CCSBU_OVP_ODL, PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_cc GPIO_INT(LID_OPEN, PIN(F, 3), GPIO_INT_BOTH, lid_interrupt) GPIO_INT(VOLDN_BTN_ODL, PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(VOLUP_BTN_ODL, PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO_INT(BASE_SIXAXIS_INT_L, PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt) GPIO_INT(EC_WP_OD, PIN(A, 6), GPIO_INT_BOTH, switch_interrupt) /* Power sequence GPIOs */ @@ -98,8 +97,7 @@ GPIO(EC_ENTERING_RW, PIN(G, 0), GPIO_OUT_LOW) GPIO(EC_ENTERING_RW2, PIN(C, 7), GPIO_OUT_LOW) GPIO(CCD_MODE_ODL, PIN(H, 5), GPIO_ODR_HIGH) GPIO(EC_BATTERY_PRES_ODL, PIN(I, 4), GPIO_INPUT) -GPIO(PEN_DET_ODL, PIN(J, 1), GPIO_INPUT | GPIO_PULL_UP) -GPIO(EN_KB_BL, PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */ +GPIO(IMVP9_PE, PIN(J, 3), GPIO_OUT_LOW) GPIO(ECH1_PACKET_MODE, PIN(H, 1), GPIO_OUT_LOW) /* LEDs */ @@ -122,6 +120,8 @@ GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOH4_NC, PIN(H, 4), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOH6_NC, PIN(H, 6), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOJ0_NC, PIN(J, 0), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOJ1_NC, PIN(J, 1), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN) diff --git a/board/brya/pwm.c b/board/brya/pwm.c index 2203f14c8d..cb452c13ed 100644 --- a/board/brya/pwm.c +++ b/board/brya/pwm.c @@ -35,7 +35,7 @@ const struct pwm_t pwm_channels[] = { * lower PWM frequencies, but higher frequencies record a much * lower maximum power. */ - .freq = 2400, + .freq = 12000, }, [PWM_CH_FAN] = { .channel = 5, diff --git a/board/crota/board.h b/board/crota/board.h index f527011e9f..46f3eb7755 100644 --- a/board/crota/board.h +++ b/board/crota/board.h @@ -75,6 +75,8 @@ #define CONFIG_USBC_PPC_SYV682X +#define CONFIG_USB_PD_FRS_PPC + /* TODO: b/177608416 - measure and check these values on brya */ #define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ @@ -157,10 +159,10 @@ /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x54 /* Type-C connector facing Burnside Bridge retimer */ -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE diff --git a/board/crota/gpio.inc b/board/crota/gpio.inc index ab8d6ae381..655fc68060 100644 --- a/board/crota/gpio.inc +++ b/board/crota/gpio.inc @@ -136,9 +136,9 @@ UNUSED(PIN(C, 2)) /* GPIOC2/PWM1/I2C6_SCL0 */ GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) IOEX(USB_C0_OC_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW) +IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW) IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW) IOEX(USB_C1_RT_RST_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW) IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C1_FRS_EN, EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW) +IOEX(USB_C1_FRS_EN, EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW) diff --git a/board/crota/pwm.c b/board/crota/pwm.c index 15cf80eea9..51bee909ff 100644 --- a/board/crota/pwm.c +++ b/board/crota/pwm.c @@ -34,8 +34,8 @@ const struct pwm_t pwm_channels[] = { }, [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, - .freq = 1000 + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); diff --git a/board/crota/usbc_config.c b/board/crota/usbc_config.c index e0e575c78c..a06631489f 100644 --- a/board/crota/usbc_config.c +++ b/board/crota/usbc_config.c @@ -87,11 +87,13 @@ struct ppc_config_t ppc_chips[] = { [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0_C1_PPC, .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .frs_en = IOEX_USB_C0_FRS_EN, .drv = &syv682x_drv, }, [USBC_PORT_C1] = { .i2c_port = I2C_PORT_USB_C0_C1_PPC, .i2c_addr_flags = SYV682X_ADDR2_FLAGS, + .frs_en = IOEX_USB_C1_FRS_EN, .drv = &syv682x_drv, }, }; diff --git a/board/drawcia_riscv/board.h b/board/drawcia_riscv/board.h index fa40c8a80a..45f16c9ac3 100644 --- a/board/drawcia_riscv/board.h +++ b/board/drawcia_riscv/board.h @@ -19,6 +19,13 @@ #define CONFIG_LTO +/* + * The workaround can be enabled on a chip variant with 1MB flash. + * (There is relocation truncated to fit error when building this board) + */ +#define CONFIG_RISCV_EXTENSION_M +#undef CONFIG_IT8XXX2_MUL_WORKAROUND + #undef GPIO_VOLUME_UP_L #define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD diff --git a/board/felwinter/gpio.inc b/board/felwinter/gpio.inc index 86f71a9ea3..112047c35f 100644 --- a/board/felwinter/gpio.inc +++ b/board/felwinter/gpio.inc @@ -148,7 +148,7 @@ IOEX(USB_C1_RT_RST_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW) IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH) IOEX(USB_C1_FRS_EN, EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW) -IOEX(USB_C2_RT_RST_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW) +IOEX(USB_C2_RT_RST_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_LOW) IOEX(USB_C2_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH) IOEX(USB_C2_FRS_EN, EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW) /* GPIO07_P2 to PU */ diff --git a/board/ghost/board.c b/board/ghost/board.c index 52348277bf..d156a78975 100644 --- a/board/ghost/board.c +++ b/board/ghost/board.c @@ -22,7 +22,7 @@ static void board_chipset_resume(void) { /* Allow keyboard backlight to be enabled */ - gpio_set_level(GPIO_EC_KB_BL_EN_L, 0); + gpio_set_level(GPIO_EC_KB_BL_EN, 1); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); @@ -31,6 +31,6 @@ static void board_chipset_suspend(void) { /* Turn off the keyboard backlight if it's on. */ - gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); + gpio_set_level(GPIO_EC_KB_BL_EN, 0); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); diff --git a/board/ghost/board.h b/board/ghost/board.h index 9f1dd73847..79be17ac2f 100644 --- a/board/ghost/board.h +++ b/board/ghost/board.h @@ -18,6 +18,11 @@ /* Baseboard features */ #include "baseboard.h" +/* + * TODO(b/230813416): remove after bringup + */ +#define CONFIG_BRINGUP + /* Buttons are not supported */ #undef CONFIG_VOLUME_BUTTONS #undef CONFIG_MKBP_INPUT_DEVICES @@ -84,6 +89,7 @@ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ +#define GPIO_IMVP9_VRRDY_OD GPIO_IMVP91_VRRDY_OD #define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL #define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG #define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK @@ -99,26 +105,24 @@ #define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 - -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 - -#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_RT NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_RT NPCX_I2C_PORT6_1 #define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT5_0 +#define I2C_PORT_MISC NPCX_I2C_PORT7_0 + +#define I2C_PORT_EEPROM I2C_PORT_MISC +#define I2C_PORT_MP2964 I2C_PORT_MISC #define I2C_ADDR_EEPROM_FLAGS 0x50 #define I2C_ADDR_MP2964_FLAGS 0x20 -/* - * see b/174768555#comment22 - */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -136,12 +140,9 @@ #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B /* Charger defines */ -#define CONFIG_CHARGER_BQ25720 -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 -#define CONFIG_CHARGER_BQ25710_PSYS_SENSING +#define CONFIG_CHARGER_ISL9241 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 #ifndef __ASSEMBLER__ diff --git a/board/ghost/charger.c b/board/ghost/charger.c index ad2d841adb..6e14119a77 100644 --- a/board/ghost/charger.c +++ b/board/ghost/charger.c @@ -10,7 +10,7 @@ #include "charger.h" #include "compile_time_macros.h" #include "console.h" -#include "driver/charger/bq25710.h" +#include "driver/charger/isl9241.h" #include "usbc_ppc.h" #include "usb_pd.h" #include "util.h" @@ -24,8 +24,8 @@ const struct charger_config_t chg_chips[] = { { .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, - .drv = &bq25710_drv, + .i2c_addr_flags = ISL9241_ADDR_FLAGS, + .drv = &isl9241_drv, }, }; BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); diff --git a/board/ghost/generated-gpio.inc b/board/ghost/generated-gpio.inc index 8a6a2e6a20..593eb21dec 100644 --- a/board/ghost/generated-gpio.inc +++ b/board/ghost/generated-gpio.inc @@ -4,12 +4,7 @@ /* INTERRUPT GPIOs: */ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) -/*GPIO_INT(EC_ACCEL_INT_R_L, PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)*/ -/*GPIO_INT(EC_ALS_RGB_INT_R_L, PIN(D, 4), GPIO_INT_FALLING, tcs3400_interrupt)*/ -/*GPIO_INT(EC_IMU_INT_R_L, PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)*/ GPIO_INT(EC_PROCHOT_IN_L, PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt) -/*GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)*/ -/*GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)*/ GPIO_INT(EC_WP_ODL, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) GPIO_INT(GSC_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) @@ -19,25 +14,20 @@ GPIO_INT(SEQ_EC_RSMRST_ODL, PIN(E, 2), GPIO_INT_BOTH, power_signal_ GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_SUS_L, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SYS_SLP_S0IX_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) -/*GPIO_INT(TABLET_MODE_L, PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)*/ -/*GPIO_INT(USB_C0_BC12_INT_ODL, PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)*/ -GPIO_INT(USB_C0_C2_TCPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C0_C1_TCPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C0_PPC_INT_ODL, PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt) GPIO_INT(USB_C0_RT_INT_ODL, PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt) -/*GPIO_INT(USB_C1_BC12_INT_ODL, PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)*/ -/*GPIO_INT(USB_C1_PPC_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)*/ -/*GPIO_INT(USB_C1_TCPC_INT_ODL, PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)*/ -/*GPIO_INT(USB_C2_BC12_INT_ODL, PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)*/ GPIO_INT(USB_C1_PPC_INT_ODL, PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C2_RT_INT_ODL, PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt) +GPIO_INT(USB_C1_RT_INT_ODL, PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt) /* USED GPIOs: */ GPIO(CCD_MODE_ODL, PIN(E, 5), GPIO_INPUT) -GPIO(CHARGER_VAP_OTG_EN, PIN(7, 3), GPIO_OUT_LOW) +GPIO(CHARGER_INT_ODL, PIN(7, 3), GPIO_INPUT) GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) +GPIO(EC_ALS_RGB_INT_R_L, PIN(D, 4), GPIO_INPUT) GPIO(EC_BATT_PRES_ODL, PIN(A, 3), GPIO_INPUT) GPIO(EC_ENTERING_RW, PIN(0, 3), GPIO_OUT_LOW) -GPIO(EC_EN_EDP_BL, PIN(D, 3), GPIO_OUT_HIGH) +GPIO(EC_EN_EDP_BL, PIN(8, 3), GPIO_OUT_HIGH) GPIO(EC_GSC_PACKET_MODE, PIN(7, 5), GPIO_OUT_LOW) GPIO(EC_I2C_BAT_SCL, PIN(3, 3), GPIO_INPUT) GPIO(EC_I2C_BAT_SDA, PIN(3, 6), GPIO_INPUT) @@ -45,17 +35,15 @@ GPIO(EC_I2C_MISC_SCL_R, PIN(B, 3), GPIO_INPUT) GPIO(EC_I2C_MISC_SDA_R, PIN(B, 2), GPIO_INPUT) GPIO(EC_I2C_SENSOR_SCL, PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(EC_I2C_SENSOR_SDA, PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V) -GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL, PIN(9, 2), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA, PIN(9, 1), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_RT_SCL, PIN(D, 1), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_RT_SDA, PIN(D, 0), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_TCPC_SCL, PIN(9, 0), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_TCPC_SDA, PIN(8, 7), GPIO_INPUT) -GPIO(EC_I2C_USB_C1_MIX_SCL, PIN(E, 4), GPIO_INPUT) -GPIO(EC_I2C_USB_C1_MIX_SDA, PIN(E, 3), GPIO_INPUT) -GPIO(EC_I2C_USB_C1_TCPC_SCL, PIN(F, 3), GPIO_INPUT) -GPIO(EC_I2C_USB_C1_TCPC_SDA, PIN(F, 2), GPIO_INPUT) -GPIO(EC_KB_BL_EN_L, PIN(8, 6), GPIO_OUT_HIGH) +GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL, PIN(9, 2), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA, PIN(9, 1), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C1_TCPC_SCL, PIN(9, 0), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_C1_TCPC_SDA, PIN(8, 7), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_RT_SCL, PIN(D, 1), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_RT_SDA, PIN(D, 0), GPIO_INPUT) +GPIO(EC_I2C_USB_C1_RT_SCL, PIN(E, 4), GPIO_INPUT) +GPIO(EC_I2C_USB_C1_RT_SDA, PIN(E, 3), GPIO_INPUT) +GPIO(EC_KB_BL_EN, PIN(F, 5), GPIO_OUT_HIGH) GPIO(EC_PCHHOT_ODL, PIN(7, 4), GPIO_INPUT) GPIO(EC_PCH_INT_ODL, PIN(B, 0), GPIO_ODR_HIGH) GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) @@ -65,16 +53,13 @@ GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_R_ODL, PIN(C, 0), GPIO_ODR_HIGH) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_HIGH) -GPIO(EN_PP5000_USBA_R, PIN(D, 7), GPIO_OUT_LOW) GPIO(EN_S5_RAILS, PIN(B, 6), GPIO_OUT_LOW) -GPIO(IMVP9_VRRDY_OD, PIN(4, 3), GPIO_INPUT) +GPIO(FAN_TACH2, PIN(D, 3), GPIO_INPUT) +GPIO(GLOGO_EN, PIN(D, 7), GPIO_OUT_LOW) +GPIO(IMVP91_VRRDY_OD, PIN(4, 3), GPIO_INPUT) GPIO(PCH_PWROK, PIN(7, 2), GPIO_OUT_LOW) GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) -GPIO(USB_C0_C2_TCPC_RST_ODL, PIN(A, 7), GPIO_ODR_LOW) -GPIO(USB_C1_FRS_EN, PIN(9, 4), GPIO_OUT_LOW) -GPIO(USB_C1_RST_ODL, PIN(9, 6), GPIO_ODR_LOW) -GPIO(USB_C1_RT_INT_ODL, PIN(A, 0), GPIO_INPUT) -GPIO(USB_C1_RT_RST_R_ODL, PIN(0, 2), GPIO_ODR_LOW) +GPIO(USB_C0_C1_TCPC_RST_ODL, PIN(A, 7), GPIO_ODR_LOW) GPIO(VCCST_PWRGD_OD, PIN(A, 4), GPIO_ODR_LOW) /* UART alternate functions */ @@ -88,14 +73,12 @@ ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0) /* GPIOB3/I2C7_SCL0 ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V) /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */ ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0) /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */ ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0) /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */ -ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0) /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */ /* PWM alternate functions */ ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0) /* GPIO40/TA1 */ -ALTERNATE(PIN_MASK(6, 0x01), 0, MODULE_PWM, 0) /* GPIO60/PWM7 */ ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* GPIO80/PWM3 */ ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0) /* GPIOB7/PWM5 */ -ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0) /* GPIOC4/PWM2, GPIOC3/PWM0, GPIOC2/PWM1/I2C6_SCL0 */ +ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0) /* GPIOC2/PWM1/I2C6_SCL0, GPIOC3/PWM0, GPIOC4/PWM2 */ /* ADC alternate functions */ ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0) /* GPIO34/PS2_DAT2/ADC6 */ @@ -103,23 +86,29 @@ ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0) /* GPIOE1/ADC7 */ /* KB alternate functions */ -ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */ +ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05 */ ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */ -ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */ + +ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI3/GPIO26/TRACEDATA0, KSI2/GPIO27/TRACEDATA1, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */ ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */ ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */ -ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO14/GPIO82 */ /* PMU alternate functions */ ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */ ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */ ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */ +/* GPIO alternate functions */ +ALTERNATE(PIN_MASK(D, 0x08), 0, MODULE_GPIO, GPIO_INPUT) /* GPIOD3/TB1 */ + /* Unused Pins */ +UNUSED(PIN(5, 7)) /* SER_IRQ/ESPI_ALERT_L/GPIO57 */ UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */ UNUSED(PIN(3, 2)) /* GPO32/TRIS_L */ UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */ UNUSED(PIN(6, 6)) /* GPIO66 */ -UNUSED(PIN(5, 7)) /* GPIO57/SER_IRQ/ESPI_ALERT_L */ /* Pre-configured PSL balls: J8 K6 */ + +/* Unreferenced balls */ +/* ['D10', 'D11', 'D6', 'E11', 'F12', 'F5', 'F6', 'F7', 'G10', 'G11', 'G12', 'G6', 'J9', 'L10', 'M11', 'M12', 'M2', 'M7'] */ diff --git a/board/ghost/gpio.inc b/board/ghost/gpio.inc index 7b49e668ee..40d9aa1418 100644 --- a/board/ghost/gpio.inc +++ b/board/ghost/gpio.inc @@ -28,10 +28,10 @@ */ GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) +IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 2), GPIO_ODR_LOW) IOEX(USB_C0_OC_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH) IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW) -IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW) -IOEX(USB_C1_RT_RST_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW) IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH) IOEX(USB_C1_FRS_EN, EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW) +IOEX(USB_C1_RT_RST_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 7), GPIO_ODR_LOW) diff --git a/board/ghost/i2c.c b/board/ghost/i2c.c index f3426740b9..f65a074344 100644 --- a/board/ghost/i2c.c +++ b/board/ghost/i2c.c @@ -19,30 +19,30 @@ const struct i2c_port_t i2c_ports[] = { }, { /* I2C1 */ - .name = "tcpc0,2", - .port = I2C_PORT_USB_C0_C2_TCPC, + .name = "tcpc0,1", + .port = I2C_PORT_USB_C0_C1_TCPC, /* TODO(b/233013680): set to 1000 when validated */ .kbps = 400, - .scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL, - .sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA, + .scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL, + .sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA, }, { /* I2C2 */ - .name = "ppc0,2", - .port = I2C_PORT_USB_C0_C2_PPC, + .name = "ppc0,1", + .port = I2C_PORT_USB_C0_C1_PPC, /* TODO(b/233013680): set to 1000 when validated */ .kbps = 400, - .scl = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SCL, - .sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA, + .scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL, + .sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA, }, { /* I2C3 */ - .name = "retimer0,2", - .port = I2C_PORT_USB_C0_C2_MUX, + .name = "retimer0", + .port = I2C_PORT_USB_C0_RT, /* TODO(b/233013680): set to 1000 when validated */ .kbps = 400, - .scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL, - .sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA, + .scl = GPIO_EC_I2C_USB_C0_RT_SCL, + .sda = GPIO_EC_I2C_USB_C0_RT_SDA, }, { /* I2C5 */ @@ -53,6 +53,15 @@ const struct i2c_port_t i2c_ports[] = { .sda = GPIO_EC_I2C_BAT_SDA, }, { + /* I2C6 */ + .name = "retimer1", + .port = I2C_PORT_USB_C1_RT, + /* TODO(b/233013680): set to 1000 when validated */ + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C1_RT_SCL, + .sda = GPIO_EC_I2C_USB_C1_RT_SDA, + }, + { /* I2C7 */ .name = "eeprom", .port = I2C_PORT_EEPROM, diff --git a/board/ghost/usbc_config.c b/board/ghost/usbc_config.c index 9a7015cebc..f8b1df5ade 100644 --- a/board/ghost/usbc_config.c +++ b/board/ghost/usbc_config.c @@ -41,8 +41,8 @@ const struct tcpc_config_t tcpc_config[] = { [USBC_PORT_C0] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { - .port = I2C_PORT_USB_C0_C2_TCPC, - .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + .port = I2C_PORT_USB_C0_C1_TCPC, + .addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, }, .drv = &nct38xx_tcpm_drv, .flags = TCPC_FLAGS_TCPCI_REV2_0 | @@ -51,8 +51,8 @@ const struct tcpc_config_t tcpc_config[] = { [USBC_PORT_C1] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { - .port = I2C_PORT_USB_C0_C2_TCPC, - .addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + .port = I2C_PORT_USB_C0_C1_TCPC, + .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, }, .drv = &nct38xx_tcpm_drv, .flags = TCPC_FLAGS_TCPCI_REV2_0, @@ -66,14 +66,14 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); /* USBC PPC configuration */ struct ppc_config_t ppc_chips[] = { [USBC_PORT_C0] = { - .i2c_port = I2C_PORT_USB_C0_C2_PPC, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .i2c_port = I2C_PORT_USB_C0_C1_PPC, + .i2c_addr_flags = SYV682X_ADDR2_FLAGS, .frs_en = IOEX_USB_C0_FRS_EN, .drv = &syv682x_drv, }, [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_USB_C0_C2_PPC, - .i2c_addr_flags = SYV682X_ADDR2_FLAGS, + .i2c_port = I2C_PORT_USB_C0_C1_PPC, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, .frs_en = IOEX_USB_C1_FRS_EN, .drv = &syv682x_drv, }, @@ -99,7 +99,7 @@ const struct usb_mux usb_muxes[] = { .usb_port = USBC_PORT_C0, .driver = &bb_usb_retimer, .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_port = I2C_PORT_USB_C0_RT, .i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR, .next_mux = &usbc0_tcss_usb_mux, }, @@ -107,8 +107,8 @@ const struct usb_mux usb_muxes[] = { .usb_port = USBC_PORT_C1, .driver = &bb_usb_retimer, .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C0_C2_MUX, - .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, + .i2c_port = I2C_PORT_USB_C1_RT, + .i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR, .next_mux = &usbc1_tcss_usb_mux, }, }; @@ -126,14 +126,14 @@ BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); struct ioexpander_config_t ioex_config[] = { [IOEX_C0_NCT38XX] = { - .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + .i2c_host_port = I2C_PORT_USB_C0_C1_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, .drv = &nct38xx_ioexpander_drv, .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, }, [IOEX_C1_NCT38XX] = { - .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, - .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + .i2c_host_port = I2C_PORT_USB_C0_C1_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, .drv = &nct38xx_ioexpander_drv, .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, }, @@ -182,7 +182,7 @@ void board_reset_pd_mcu(void) { enum gpio_signal tcpc_rst; - tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; + tcpc_rst = GPIO_USB_C0_C1_TCPC_RST_ODL; gpio_set_level(tcpc_rst, 0); @@ -222,7 +222,7 @@ static void board_tcpc_init(void) gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); @@ -230,7 +230,7 @@ uint16_t tcpc_get_alert_status(void) { uint16_t status = 0; - if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0) + if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0) status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1; return status; @@ -248,7 +248,7 @@ int ppc_get_alert_status(int port) void tcpc_alert_event(enum gpio_signal signal) { switch (signal) { - case GPIO_USB_C0_C2_TCPC_INT_ODL: + case GPIO_USB_C0_C1_TCPC_INT_ODL: schedule_deferred_pd_interrupt(USBC_PORT_C0); break; default: diff --git a/board/gimble/led.c b/board/gimble/led.c index 39bfff17ab..3176e1a35d 100644 --- a/board/gimble/led.c +++ b/board/gimble/led.c @@ -78,34 +78,49 @@ __override void led_set_color_battery(enum ec_led_colors color) /* Check which port is the charging port, * and turn on the corresponding led. */ - port = charge_manager_get_active_charge_port(); - switch (port) { - case LED_SIDESEL_MB_PORT: - switch (color) { - case EC_LED_COLOR_AMBER: - led1_duty = BAT_LED_ON_LVL; + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + port = charge_manager_get_active_charge_port(); + switch (port) { + case LED_SIDESEL_MB_PORT: + switch (color) { + case EC_LED_COLOR_AMBER: + led1_duty = BAT_LED_ON_LVL; + break; + case EC_LED_COLOR_WHITE: + led2_duty = BAT_LED_ON_LVL; + break; + default: /* LED_OFF and other unsupported colors */ + break; + } break; - case EC_LED_COLOR_WHITE: - led2_duty = BAT_LED_ON_LVL; + case LED_SIDESEL_DB_PORT: + switch (color) { + case EC_LED_COLOR_AMBER: + led3_duty = BAT_LED_ON_LVL; + break; + case EC_LED_COLOR_WHITE: + led4_duty = BAT_LED_ON_LVL; + break; + default: /* LED_OFF and other unsupported colors */ + break; + } break; - default: /* LED_OFF and other unsupported colors */ + default: /* Unknown charging port */ break; } - break; - case LED_SIDESEL_DB_PORT: + } else { switch (color) { case EC_LED_COLOR_AMBER: + led1_duty = BAT_LED_ON_LVL; led3_duty = BAT_LED_ON_LVL; break; case EC_LED_COLOR_WHITE: + led2_duty = BAT_LED_ON_LVL; led4_duty = BAT_LED_ON_LVL; break; default: /* LED_OFF and other unsupported colors */ break; } - break; - default: /* Unknown charging port */ - break; } pwm_set_duty(PWM_CH_LED1, led1_duty); @@ -141,8 +156,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) led_set_color_battery(EC_LED_COLOR_AMBER); else if (brightness[EC_LED_COLOR_WHITE] != 0) led_set_color_battery(EC_LED_COLOR_WHITE); - else + else if (brightness[LED_OFF] != 0) led_set_color_battery(LED_OFF); + else { + led_auto_control(led_id, 1); + led_set_color_battery(LED_OFF); + } } else if (led_id == EC_LED_ID_POWER_LED) { if (brightness[EC_LED_COLOR_WHITE] != 0) led_set_color_power(EC_LED_COLOR_WHITE); diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk index 8986d3ee91..cffb093fc8 100644 --- a/board/hatch_fp/build.mk +++ b/board/hatch_fp/build.mk @@ -57,4 +57,4 @@ test-list-y=\ # Note that this variable includes the trailing "/" _hatch_fp_cur_dir:=$(dir $(lastword $(MAKEFILE_LIST))) --include $(_hatch_fp_cur_dir)../../private/board/hatch_fp/build.mk
\ No newline at end of file +-include $(_hatch_fp_cur_dir)../../private/board/hatch_fp/build.mk diff --git a/board/host/chipset.c b/board/host/chipset.c index 5213d06acb..0a7385fc84 100644 --- a/board/host/chipset.c +++ b/board/host/chipset.c @@ -5,6 +5,9 @@ /* Chipset module for emulator */ +/* Does not run a chipset task, but does emulate an AP chipset */ +#define CONFIG_AP_POWER_CONTROL + #include <stdio.h> #include "chipset.h" #include "common.h" diff --git a/board/lantis/board.c b/board/lantis/board.c index 44e117ee9a..f8c8b2e477 100644 --- a/board/lantis/board.c +++ b/board/lantis/board.c @@ -26,6 +26,7 @@ #include "hooks.h" #include "intc.h" #include "keyboard_8042.h" +#include "keyboard_8042_sharedlib.h" #include "keyboard_raw.h" #include "keyboard_scan.h" #include "lid_switch.h" @@ -376,7 +377,7 @@ struct motion_sensor_t motion_sensors[] = { .port = I2C_PORT_SENSOR, .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, .default_range = 1000 | ROUND_UP_FLAG, /* dps */ - .rot_standard_ref = NULL, + .rot_standard_ref = &base_standard_ref, .min_frequency = LSM6DSM_ODR_MIN_VAL, .max_frequency = LSM6DSM_ODR_MAX_VAL, }, @@ -531,6 +532,17 @@ static void board_update_no_keypad_by_fwconfig(void) } } +static void board_update_keyboard_layout(void) +{ + if (get_cbi_fw_config_keyboard() == KB_LAYOUT_1) { + /* + * If keyboard is UK(KB_LAYOUT_1), we need translate right ctrl + * to backslash(\|) key. + */ + set_scancode_set2(4, 0, get_scancode_set2(2, 7)); + } +} + void board_init(void) { int on; @@ -592,6 +604,7 @@ void board_init(void) board_power_5v_enable(on); board_update_no_keypad_by_fwconfig(); + board_update_keyboard_layout(); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/lantis/board.h b/board/lantis/board.h index c2ea89b168..067ff7eb94 100644 --- a/board/lantis/board.h +++ b/board/lantis/board.h @@ -143,6 +143,11 @@ enum battery_type { BATTERY_TYPE_COUNT, }; +enum ec_cfg_keyboard_layout { + KB_LAYOUT_DEFAULT = 0, + KB_LAYOUT_1 = 1 +}; + #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ diff --git a/board/lazor/board.c b/board/lazor/board.c index 03192e1bbc..e25b83d7db 100644 --- a/board/lazor/board.c +++ b/board/lazor/board.c @@ -19,6 +19,7 @@ #include "hooks.h" #include "keyboard_scan.h" #include "lid_switch.h" +#include "mkbp_info.h" #include "power.h" #include "power_button.h" #include "pwm.h" @@ -454,3 +455,8 @@ __override uint32_t board_get_sku_id(void) return (uint32_t)sku_id; } + +__override int mkbp_support_volume_buttons(void) +{ + return board_has_side_volume_buttons(); +} diff --git a/board/lazor/board.h b/board/lazor/board.h index e46c9d2218..f4f722c6a2 100644 --- a/board/lazor/board.h +++ b/board/lazor/board.h @@ -83,6 +83,7 @@ /* Disable console commands to help save space */ #undef CONFIG_CMD_BATTFAKE +#undef CONFIG_CMD_CHARGE_SUPPLIER_INFO #ifndef __ASSEMBLER__ diff --git a/board/lazor/sku.c b/board/lazor/sku.c index 815295d9f5..1f63d05bf6 100644 --- a/board/lazor/sku.c +++ b/board/lazor/sku.c @@ -91,3 +91,8 @@ int board_has_ln9310(void) { return get_model() == LIMOZEEN && system_get_board_version() < 8; } + +int board_has_side_volume_buttons(void) +{ + return get_model() == LAZOR; +} diff --git a/board/lazor/sku.h b/board/lazor/sku.h index 96eaf2bb92..85f549858a 100644 --- a/board/lazor/sku.h +++ b/board/lazor/sku.h @@ -13,5 +13,6 @@ int board_is_clamshell(void); int board_has_da9313(void); int board_has_ln9310(void); int board_has_buck_ic(void); +int board_has_side_volume_buttons(void); #endif /* __CROS_EC_SKU_H */ diff --git a/board/mithrax/board.c b/board/mithrax/board.c index b391301cc8..3db87618f8 100644 --- a/board/mithrax/board.c +++ b/board/mithrax/board.c @@ -32,6 +32,8 @@ #define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) #define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +static void rgb_backlight_config(void); + /******************************************************************************/ /* USB-A charging control */ @@ -67,6 +69,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); static void board_chipset_startup(void) { pen_config(); + rgb_backlight_config(); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); @@ -168,5 +171,14 @@ void pen_config(void) static void board_chipset_shutdown(void) { gpio_set_level(GPIO_EN_PP5000_PEN, 0); + gpio_set_level(GPIO_EN_PP5000_LED, 0); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); + +static void rgb_backlight_config(void) +{ + if (ec_cfg_kb_backlight() == RGB) + gpio_set_level(GPIO_EN_PP5000_LED, 1); + else + gpio_set_level(GPIO_EN_PP5000_LED, 0); +} diff --git a/board/mithrax/board.h b/board/mithrax/board.h index 90716c9112..c9d2112b2c 100644 --- a/board/mithrax/board.h +++ b/board/mithrax/board.h @@ -21,6 +21,11 @@ #define CONFIG_MP2964 +/* KEYBOARD */ +#define CONFIG_KEYBOARD_CUSTOMIZATION +#define CONFIG_KEYBOARD_VIVALDI +#define CONFIG_KEYBOARD_REFRESH_ROW3 + /* LED */ #define CONFIG_LED_ONOFF_STATES #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 @@ -124,7 +129,7 @@ #define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ -#define CONFIG_PWM_KBLIGHT +#define CONFIG_KEYBOARD_BACKLIGHT /* I2C Bus Configuration */ @@ -146,6 +151,7 @@ #define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 #define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 #define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0 #define I2C_ADDR_EEPROM_FLAGS 0x50 @@ -180,7 +186,14 @@ #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#define CONFIG_KEYBOARD_REFRESH_ROW3 +/* RGB Keyboard */ +#ifdef SECTION_IS_RW +#define CONFIG_RGB_KEYBOARD +#define CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ +#define TLC59116F_I2C_ADDR_FLAG TLC59116F_ADDR3_FLAG +#endif /* SECTION_IS_RW */ +#define RGB_GRID0_COL 4 +#define RGB_GRID0_ROW 1 #ifndef __ASSEMBLER__ diff --git a/board/mithrax/build.mk b/board/mithrax/build.mk index c4345d8de0..a7ec1987de 100644 --- a/board/mithrax/build.mk +++ b/board/mithrax/build.mk @@ -23,3 +23,4 @@ board-y+=led.o board-y+=pwm.o board-y+=sensors.o board-y+=usbc_config.o +board-y+=keyboard_customization.o diff --git a/board/mithrax/ec.tasklist b/board/mithrax/ec.tasklist index 96c9128df4..b6a6557d1e 100644 --- a/board/mithrax/ec.tasklist +++ b/board/mithrax/ec.tasklist @@ -12,6 +12,7 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \ + TASK_ALWAYS_RW(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \ TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \ diff --git a/board/mithrax/keyboard.c b/board/mithrax/keyboard.c index f07b2dda17..6534c7bc63 100644 --- a/board/mithrax/keyboard.c +++ b/board/mithrax/keyboard.c @@ -6,7 +6,9 @@ #include "common.h" #include "ec_commands.h" #include "keyboard_scan.h" +#include "rgb_keyboard.h" #include "timer.h" +#include "tlc59116f.h" /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -19,8 +21,8 @@ __override struct keyboard_scan_config keyscan_config = { .min_post_scan_delay_us = 1000, .poll_timeout_us = 100 * MSEC, .actual_key_mask = { - 0x1c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */ + 0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x86, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff, /* full set */ }, }; @@ -38,11 +40,193 @@ static const struct ec_response_keybd_config mithrax_kb = { TK_VOL_DOWN, /* T9 */ TK_VOL_UP, /* T10 */ }, - .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; +static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW]; + +struct rgbkbd rgbkbds[] = { + [0] = { + .cfg = &(const struct rgbkbd_cfg) { + .drv = &tlc59116f_drv, + .i2c = I2C_PORT_KBMCU, + .col_len = RGB_GRID0_COL, + .row_len = RGB_GRID0_ROW, + }, + .buf = grid0, + }, +}; +const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); + +const uint8_t rgbkbd_hsize = RGB_GRID0_COL; +const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; + +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM +const uint8_t rgbkbd_map[] = { + DELM, /* 0: (null) */ + LED(0, 0), DELM, /* 1: ~ ` */ + LED(0, 0), DELM, /* 2: ! 1 */ + LED(0, 0), DELM, /* 3: @ 2 */ + LED(0, 0), DELM, /* 4: # 3 */ + LED(1, 0), DELM, /* 5: $ 4 */ + LED(1, 0), DELM, /* 6: % 5 */ + LED(1, 0), DELM, /* 7: ^ 6 */ + LED(2, 0), DELM, /* 8: & 7 */ + LED(2, 0), DELM, /* 9: * 8 */ + LED(2, 0), DELM, /* 10: ( 9 */ + LED(2, 0), DELM, /* 11: ) 0 */ + LED(2, 0), DELM, /* 12: _ - */ + LED(3, 0), DELM, /* 13: + = */ + DELM, /* 14: (null) */ + LED(3, 0), DELM, /* 15: backspace */ + LED(0, 0), DELM, /* 16: tab */ + LED(0, 0), DELM, /* 17: q */ + LED(0, 0), DELM, /* 18: w */ + LED(0, 0), DELM, /* 19: e */ + LED(1, 0), DELM, /* 20: r */ + LED(1, 0), DELM, /* 21: t */ + LED(1, 0), DELM, /* 22: y */ + LED(2, 0), DELM, /* 23: u */ + LED(2, 0), DELM, /* 24: i */ + LED(2, 0), DELM, /* 25: o */ + LED(2, 0), DELM, /* 26: p */ + LED(2, 0), DELM, /* 27: [ { */ + LED(3, 0), DELM, /* 28: ] } */ + LED(3, 0), DELM, /* 29: \ | */ + LED(0, 0), DELM, /* 30: caps lock */ + LED(0, 0), DELM, /* 31: a */ + LED(0, 0), DELM, /* 32: s */ + LED(0, 0), DELM, /* 33: d */ + LED(1, 0), DELM, /* 34: f */ + LED(1, 0), DELM, /* 35: g */ + LED(1, 0), DELM, /* 36: h */ + LED(2, 0), DELM, /* 37: j */ + LED(2, 0), DELM, /* 38: k */ + LED(2, 0), DELM, /* 39: l */ + LED(3, 0), DELM, /* 40: ; : */ + LED(3, 0), DELM, /* 41: " ' */ + DELM, /* 42: (null) */ + LED(3, 0), DELM, /* 43: enter */ + LED(0, 0), DELM, /* 44: L-shift */ + DELM, /* 45: (null) */ + LED(0, 0), DELM, /* 46: z */ + LED(0, 0), DELM, /* 47: x */ + LED(0, 0), DELM, /* 48: c */ + LED(1, 0), DELM, /* 49: v */ + LED(1, 0), DELM, /* 50: b */ + LED(1, 0), DELM, /* 51: n */ + LED(2, 0), DELM, /* 52: m */ + LED(2, 0), DELM, /* 53: , < */ + LED(2, 0), DELM, /* 54: . > */ + LED(3, 0), DELM, /* 55: / ? */ + DELM, /* 56: (null) */ + LED(3, 0), DELM, /* 57: R-shift */ + LED(0, 0), DELM, /* 58: L-ctrl */ + LED(3, 0), DELM, /* 59: power */ + LED(0, 0), DELM, /* 60: L-alt */ + LED(0, 0), LED(1, 0), + LED(2, 0), DELM, /* 61: space */ + LED(2, 0), DELM, /* 62: R-alt */ + DELM, /* 63: (null) */ + LED(2, 0), DELM, /* 64: R-ctrl */ + DELM, /* 65: (null) */ + DELM, /* 66: (null) */ + DELM, /* 67: (null) */ + DELM, /* 68: (null) */ + DELM, /* 69: (null) */ + DELM, /* 70: (null) */ + DELM, /* 71: (null) */ + DELM, /* 72: (null) */ + DELM, /* 73: (null) */ + DELM, /* 74: (null) */ + DELM, /* 75: (null) */ + DELM, /* 76: delete */ + DELM, /* 77: (null) */ + DELM, /* 78: (null) */ + LED(3, 0), DELM, /* 79: left */ + DELM, /* 80: home */ + DELM, /* 81: end */ + DELM, /* 82: (null) */ + LED(3, 0), DELM, /* 83: up */ + LED(3, 0), DELM, /* 84: down */ + DELM, /* 85: page up */ + DELM, /* 86: page down */ + DELM, /* 87: (null) */ + DELM, /* 88: (null) */ + LED(3, 0), DELM, /* 89: right */ + DELM, /* 90: (null) */ + DELM, /* 91: numpad 7 */ + DELM, /* 92: numpad 4 */ + DELM, /* 93: numpad 1 */ + DELM, /* 94: (null) */ + DELM, /* 95: numpad / */ + DELM, /* 96: numpad 8 */ + DELM, /* 97: numpad 5 */ + DELM, /* 98: numpad 2 */ + DELM, /* 99: numpad 0 */ + DELM, /* 100: numpad * */ + DELM, /* 101: numpad 9 */ + DELM, /* 102: numpad 6 */ + DELM, /* 103: numpad 3 */ + DELM, /* 104: numpad . */ + DELM, /* 105: numpad - */ + DELM, /* 106: numpad + */ + DELM, /* 107: (null) */ + DELM, /* 108: numpad enter */ + DELM, /* 109: (null) */ + LED(0, 0), DELM, /* 110: esc */ + LED(0, 0), DELM, /* T1: back */ + LED(0, 0), DELM, /* T2: refresh */ + LED(1, 0), DELM, /* T3: full screen */ + LED(1, 0), DELM, /* T4: overview */ + LED(1, 0), DELM, /* T5: snapshot */ + LED(2, 0), DELM, /* T6: brightness down */ + LED(2, 0), DELM, /* T7: brightness up */ + LED(2, 0), DELM, /* T8: mute */ + LED(2, 0), DELM, /* T9: volume down */ + LED(3, 0), DELM, /* T10: volume up */ + DELM, /* T11: (null) */ + DELM, /* T12: (null) */ + DELM, /* T13: (null) */ + DELM, /* T14: (null) */ + DELM, /* T15: (null) */ + DELM, /* 126: (null) */ + DELM, /* 127: (null) */ +}; +#undef LED +#undef DELM +const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map); + __override const struct ec_response_keybd_config *board_vivaldi_keybd_config(void) { return &mithrax_kb; } + +/* + * Row Column info for Top row keys T1 - T15. + * on mithrax_kb keyboard Row Column is customization + * need define row col to mapping matrix layout. + */ +__override const struct key { + uint8_t row; + uint8_t col; +} vivaldi_keys[] = { + {.row = 4, .col = 2}, /* T1 */ + {.row = 3, .col = 2}, /* T2 */ + {.row = 2, .col = 2}, /* T3 */ + {.row = 1, .col = 2}, /* T4 */ + {.row = 4, .col = 4}, /* T5 */ + {.row = 3, .col = 4}, /* T6 */ + {.row = 2, .col = 4}, /* T7 */ + {.row = 2, .col = 9}, /* T8 */ + {.row = 1, .col = 9}, /* T9 */ + {.row = 1, .col = 4}, /* T10 */ + {.row = 0, .col = 4}, /* T11 */ + {.row = 1, .col = 5}, /* T12 */ + {.row = 3, .col = 5}, /* T13 */ + {.row = 2, .col = 1}, /* T14 */ + {.row = 0, .col = 1}, /* T15 */ +}; +BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); diff --git a/board/mithrax/keyboard_customization.c b/board/mithrax/keyboard_customization.c new file mode 100644 index 0000000000..4e45de34be --- /dev/null +++ b/board/mithrax/keyboard_customization.c @@ -0,0 +1,113 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "gpio.h" +#include "keyboard_customization.h" +#include "keyboard_8042_sharedlib.h" +#include "keyboard_config.h" +#include "keyboard_protocol.h" +#include "keyboard_raw.h" + +static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { + {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000}, + {0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016}, + {0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a}, + {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d}, + {0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d}, + {0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043}, + {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c}, + {0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059}, + {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d}, + {0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a}, + {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, + {0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066}, + {0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d}, + {0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021}, + {0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069}, +}; + + +uint16_t get_scancode_set2(uint8_t row, uint8_t col) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + return scancode_set2[col][row]; + return 0; +} + +void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + scancode_set2[col][row] = val; +} + +void board_keyboard_drive_col(int col) +{ + /* Drive all lines to high */ + if (col == KEYBOARD_COLUMN_NONE) + gpio_set_level(GPIO_KBD_KSO2, 0); + + /* Set KBSOUT to zero to detect key-press */ + else if (col == KEYBOARD_COLUMN_ALL) + gpio_set_level(GPIO_KBD_KSO2, 1); + + /* Drive one line for detection */ + else { + if (col == 2) + gpio_set_level(GPIO_KBD_KSO2, 1); + else + gpio_set_level(GPIO_KBD_KSO2, 0); + } +} + +#ifdef CONFIG_KEYBOARD_DEBUG +static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { + {'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + {'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', + '1', KLLI_UNKNO, 'a'}, + {KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + {KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, + KLLI_SEARC, '3', KLLI_F3, KLLI_UNKNO}, + {'x', 'z', KLLI_F2, KLLI_F1, + 's', '2', 'w', KLLI_ESC}, + {'v', 'b', 'g', 't', + '5', '4', 'r', 'f'}, + {'m', 'n', 'h', 'y', + '6', '7', 'u', 'j'}, + {'.', KLLI_DOWN, '\\', 'o', + KLLI_F10, '9', KLLI_UNKNO, 'l'}, + {KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + {',', KLLI_UNKNO, KLLI_F7, KLLI_F6, + KLLI_F5, '8', 'i', 'k'}, + {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, + KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT, KLLI_UNKNO}, + {KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + {'/', KLLI_UP, '-', KLLI_UNKNO, + '0', 'p', '[', ';'}, + {'\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, + '=', KLLI_B_SPC, ']', 'd'}, + {KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, +}; + +char get_keycap_label(uint8_t row, uint8_t col) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + return keycap_label[col][row]; + return KLLI_UNKNO; +} + +void set_keycap_label(uint8_t row, uint8_t col, char val) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + keycap_label[col][row] = val; +} +#endif diff --git a/board/mithrax/keyboard_customization.h b/board/mithrax/keyboard_customization.h new file mode 100644 index 0000000000..b177a11eb4 --- /dev/null +++ b/board/mithrax/keyboard_customization.h @@ -0,0 +1,73 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Keyboard configuration */ + +#ifndef __KEYBOARD_CUSTOMIZATION_H +#define __KEYBOARD_CUSTOMIZATION_H + +/* + * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate + * exact spaces for arrays. Actual keyboard scanning is done using + * keyboard_cols, which holds a runtime column size. + */ +#define KEYBOARD_COLS_MAX 15 +#define KEYBOARD_ROWS 8 + +/* + * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols, + * instead. It checks whether you're eligible or not. + */ +extern uint8_t keyboard_cols; + +#define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) + +/* Columns and masks for keys we particularly care about */ +#define KEYBOARD_COL_DOWN 11 +#define KEYBOARD_ROW_DOWN 5 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 1 +#define KEYBOARD_ROW_ESC 1 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 6 +#define KEYBOARD_ROW_KEY_H 1 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 3 +#define KEYBOARD_ROW_KEY_R 7 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 10 +#define KEYBOARD_ROW_LEFT_ALT 6 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 2 +#define KEYBOARD_ROW_REFRESH 3 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 10 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 1 +#define KEYBOARD_COL_LEFT_CTRL 0 +#define KEYBOARD_ROW_LEFT_CTRL 2 +#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) +#define KEYBOARD_COL_RIGHT_CTRL 0 +#define KEYBOARD_ROW_RIGHT_CTRL 4 +#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) +#define KEYBOARD_COL_SEARCH 0 +#define KEYBOARD_ROW_SEARCH 3 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 9 +#define KEYBOARD_ROW_KEY_0 0 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 1 +#define KEYBOARD_ROW_KEY_1 7 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 4 +#define KEYBOARD_ROW_KEY_2 6 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_LEFT_SHIFT 7 +#define KEYBOARD_ROW_LEFT_SHIFT 1 +#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) + +#endif /* __KEYBOARD_CUSTOMIZATION_H */ diff --git a/board/moli/board.c b/board/moli/board.c index baf8f94703..4a6445a8d6 100644 --- a/board/moli/board.c +++ b/board/moli/board.c @@ -104,91 +104,6 @@ int board_set_active_charge_port(int port) } static uint8_t usbc_overcurrent; -static int32_t base_5v_power_s5; -static int32_t base_5v_power_z1; - -/* - * Power usage for each port as measured or estimated. - * Units are milliwatts (5v x ma current) - */ - -/* PP5000_S5 loads */ -#define PWR_S5_BASE_LOAD (5*1275) -#define PWR_S5_FRONT_HIGH (5*1737) -#define PWR_S5_FRONT_LOW (5*1055) -#define PWR_S5_REAR_HIGH (5*1128) -#define PWR_S5_REAR_LOW (5*1128) -#define PWR_S5_HDMI (5*1000) -#define PWR_S5_MAX (5*10000) -#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW) -#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW) - -/* PP5000_Z1 loads */ -#define PWR_Z1_BASE_LOAD (5*5) -#define PWR_Z1_C_HIGH (5*3600) -#define PWR_Z1_C_LOW (5*2000) -#define PWR_Z1_MAX (5*9900) -/* - * Update the 5V power usage, assuming no throttling, - * and invoke the power monitoring. - */ -static void update_5v_usage(void) -{ - int front_ports = 0; - int rear_ports = 0; - - /* - * Recalculate the 5V load, assuming no throttling. - */ - base_5v_power_s5 = PWR_S5_BASE_LOAD; - if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) { - front_ports++; - base_5v_power_s5 += PWR_S5_FRONT_LOW; - } - if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) { - front_ports++; - base_5v_power_s5 += PWR_S5_FRONT_LOW; - } - /* - * Only 1 front port can run higher power at a time. - */ - if (front_ports > 0) - base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW; - - if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) { - rear_ports++; - base_5v_power_s5 += PWR_S5_REAR_LOW; - } - if (!gpio_get_level(GPIO_USB_A4_OC_ODL)) { - rear_ports++; - base_5v_power_s5 += PWR_S5_REAR_LOW; - } - /* - * Only 1 rear port can run higher power at a time. - */ - if (rear_ports > 0) - base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW; - if (!gpio_get_level(GPIO_HDMI_CONN_OC_ODL)) - base_5v_power_s5 += PWR_S5_HDMI; - base_5v_power_z1 = PWR_Z1_BASE_LOAD; - if (usbc_overcurrent) - base_5v_power_z1 += PWR_Z1_C_HIGH; - /* - * Invoke the power handler immediately. - */ - hook_call_deferred(&power_monitor_data, 0); -} -DECLARE_DEFERRED(update_5v_usage); -/* - * Start power monitoring after ADCs have been initialised. - */ -DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1); - -static void port_ocp_interrupt(enum gpio_signal signal) -{ - hook_call_deferred(&update_5v_usage_data, 0); -} -#include "gpio_list.h" /* Must come after other header files. */ /******************************************************************************/ /* @@ -294,7 +209,6 @@ void board_overcurrent_event(int port, int is_overcurrented) if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT)) return; usbc_overcurrent = is_overcurrented; - update_5v_usage(); } /* * Power monitoring and management. @@ -338,6 +252,7 @@ void board_overcurrent_event(int port, int is_overcurrented) #define THROT_TYPE_A_FRONT BIT(0) #define THROT_TYPE_A_REAR BIT(1) #define THROT_TYPE_C0 BIT(2) +#define THROT_TYPE_C1 BIT(3) #define THROT_PROCHOT BIT(5) /* @@ -354,6 +269,8 @@ void board_overcurrent_event(int port, int is_overcurrented) #define POWER_DELAY_MS 2 #define POWER_READINGS (10/POWER_DELAY_MS) +#include "gpio_list.h" /* Must come after other header files. */ + static void power_monitor(void) { static uint32_t current_state; @@ -361,8 +278,6 @@ static void power_monitor(void) static uint8_t index; int32_t delay; uint32_t new_state = 0, diff; - int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5; - int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1; /* * If CPU is off or suspended, no need to throttle @@ -440,7 +355,6 @@ static void power_monitor(void) */ if (gap <= 0) { new_state |= THROT_TYPE_A_REAR; - headroom_5v_s5 += REAR_DELTA; if (!(current_state & THROT_TYPE_A_REAR)) gap += POWER_GAIN_TYPE_A; } @@ -449,7 +363,6 @@ static void power_monitor(void) */ if (gap <= 0) { new_state |= THROT_TYPE_A_FRONT; - headroom_5v_s5 += FRONT_DELTA; if (!(current_state & THROT_TYPE_A_FRONT)) gap += POWER_GAIN_TYPE_A; } @@ -459,11 +372,19 @@ static void power_monitor(void) */ if (ppc_is_sourcing_vbus(0) && gap <= 0) { new_state |= THROT_TYPE_C0; - headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW; if (!(current_state & THROT_TYPE_C0)) gap += POWER_GAIN_TYPE_C; } /* + * If the type-C port is sourcing power, + * check whether it should be throttled. + */ + if (ppc_is_sourcing_vbus(1) && gap <= 0) { + new_state |= THROT_TYPE_C1; + if (!(current_state & THROT_TYPE_C1)) + gap += POWER_GAIN_TYPE_C; + } + /* * As a last resort, turn on PROCHOT to * throttle the CPU. */ @@ -472,60 +393,6 @@ static void power_monitor(void) } } /* - * Check the 5v power usage and if necessary, - * adjust the throttles in priority order. - * - * Either throttle may have already been activated by - * the overall power control. - * - * We rely on the overcurrent detection to inform us - * if the port is in use. - * - * - If type C not already throttled: - * * If not overcurrent, prefer to limit type C [1]. - * * If in overcurrentuse: - * - limit type A first [2] - * - If necessary, limit type C [3]. - * - If type A not throttled, if necessary limit it [2]. - */ - if (headroom_5v_z1 < 0) { - /* - * Check whether type C is not throttled, - * and is not overcurrent. - */ - if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) { - /* - * [1] Type C not in overcurrent, throttle it. - */ - headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW; - new_state |= THROT_TYPE_C0; - } - /* - * [2] If still under-budget, limit type C. - * No need to check if it is already throttled or not. - */ - if (headroom_5v_z1 < 0) - new_state |= THROT_TYPE_C0; - } - if (headroom_5v_s5 < 0) { - /* - * [1] If type A rear not already throttled, and power still - * needed, limit type A rear. - */ - if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) { - headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW; - new_state |= THROT_TYPE_A_REAR; - } - /* - * [2] If type A front not already throttled, and power still - * needed, limit type A front. - */ - if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) { - headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW; - new_state |= THROT_TYPE_A_FRONT; - } - } - /* * Turn the throttles on or off if they have changed. */ diff = new_state ^ current_state; @@ -543,6 +410,14 @@ static void power_monitor(void) tcpm_select_rp_value(0, rp); pd_update_contract(0); } + if (diff & THROT_TYPE_C1) { + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) + ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + + ppc_set_vbus_source_current_limit(1, rp); + tcpm_select_rp_value(1, rp); + pd_update_contract(1); + } if (diff & THROT_TYPE_A_REAR) { int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0; @@ -555,3 +430,7 @@ static void power_monitor(void) } hook_call_deferred(&power_monitor_data, delay); } +/* + * Start power monitoring after ADCs have been initialised. + */ +DECLARE_HOOK(HOOK_INIT, power_monitor, HOOK_PRIO_INIT_ADC + 1); diff --git a/board/moli/gpio.inc b/board/moli/gpio.inc index 7cc088e7ef..21336f6245 100644 --- a/board/moli/gpio.inc +++ b/board/moli/gpio.inc @@ -25,11 +25,6 @@ GPIO_INT(EC_RECOVERY_BTN_ODL, PIN(2, 3), GPIO_INT_BOTH, button_interrupt) GPIO_INT(USB_C1_RT_INT_ODL, PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt) GPIO_INT(USB_C1_BC12_INT_ODL, PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(USB_C1_PPC_INT_ODL, PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(HDMI_CONN_OC_ODL, PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt) -GPIO_INT(USB_A1_OC_ODL, PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt) -GPIO_INT(USB_A2_OC_ODL, PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt) -GPIO_INT(USB_A3_OC_ODL, PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt) -GPIO_INT(USB_A4_OC_ODL, PIN(0, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt) /* CCD */ GPIO(CCD_MODE_ODL, PIN(E, 5), GPIO_INPUT) @@ -79,6 +74,9 @@ GPIO(EC_QI_PWR, PIN(D, 2), GPIO_OUT_HIGH) GPIO(EC_I2C_QI_RESET_L, PIN(9, 3), GPIO_OUT_HIGH) GPIO(EC_I2C_QI_INT_ODL, PIN(9, 6), GPIO_INPUT) +/* HDMI */ +GPIO(HDMI_CONN_OC_ODL, PIN(2, 4), GPIO_INPUT) + /* HDMI CEC */ /* TODO(b/197474873): Enable HDMI CEC */ GPIO(HDMI_CEC_IN, PIN(4, 0), GPIO_INPUT) @@ -103,9 +101,13 @@ GPIO(EC_I2C_USB_A0_A1_MIX_SDA, PIN(E, 3), GPIO_INPUT) GPIO(EN_PP5000_USBA, PIN(D, 7), GPIO_OUT_LOW) GPIO(USB_A1_STATUS_L, PIN(2, 0), GPIO_INPUT) GPIO(USB_A2_STATUS_L, PIN(1, 7), GPIO_INPUT) -GPIO(USB_A_LOW_PWR1_OD, PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN) -GPIO(USB_A_LOW_PWR2_OD, PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(USB_A_LOW_PWR1_OD, PIN(1, 4), GPIO_OUT_LOW) +GPIO(USB_A_LOW_PWR2_OD, PIN(1, 1), GPIO_OUT_LOW) GPIO(USB_A_OC_SOC_L, PIN(8, 0), GPIO_OUT_HIGH) +GPIO(USB_A1_OC_ODL, PIN(3, 0), GPIO_INPUT) +GPIO(USB_A2_OC_ODL, PIN(2, 7), GPIO_INPUT) +GPIO(USB_A3_OC_ODL, PIN(2, 6), GPIO_INPUT) +GPIO(USB_A4_OC_ODL, PIN(0, 6), GPIO_INPUT) /* USBC */ GPIO(USB_C0_C1_TCPC_RST_ODL, PIN(F, 5), GPIO_ODR_LOW) diff --git a/board/moli/pwm.c b/board/moli/pwm.c index 8c034057bb..ad3d45f34c 100644 --- a/board/moli/pwm.c +++ b/board/moli/pwm.c @@ -18,8 +18,8 @@ const struct pwm_t pwm_channels[] = { }, [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, - .freq = 1000 + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, [PWM_CH_LED_BLUE] = { .channel = 2, diff --git a/board/moli/sensors.c b/board/moli/sensors.c index 34cad8e5af..8992b24ac4 100644 --- a/board/moli/sensors.c +++ b/board/moli/sensors.c @@ -39,11 +39,11 @@ const struct adc_t adc_channels[] = { .factor_mul = ADC_MAX_VOLT * 39, .factor_div = (ADC_READ_MAX + 1) * 5, }, - [ADC_PPVAR_IMON] = { /* 20/(20+8.66) */ + [ADC_PPVAR_IMON] = { /* 20/(20+8.66)*50/200 current divider */ .name = "PPVAR_IMON", .input_ch = NPCX_ADC_CH3, .factor_mul = ADC_MAX_VOLT * 1433, - .factor_div = (ADC_READ_MAX + 1) * 1000, + .factor_div = (ADC_READ_MAX + 1) * 250, }, }; diff --git a/board/osiris/board.c b/board/osiris/board.c index d74e7e6088..8d20de1550 100644 --- a/board/osiris/board.c +++ b/board/osiris/board.c @@ -57,3 +57,24 @@ __override void board_kblight_init(void) gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); msleep(10); } + +/* keyboard factory test */ +#ifdef CONFIG_KEYBOARD_FACTORY_TEST +/* + * We have total 30 pins for keyboard connecter {-1, -1} mean + * the N/A pin that don't consider it and reserve index 0 area + * that we don't have pin 0. + */ +const int keyboard_factory_scan_pins[][2] = { + {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, + {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, + {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, + {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, + {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, + {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, + {-1, -1}, +}; + +const int keyboard_factory_scan_pins_used = + ARRAY_SIZE(keyboard_factory_scan_pins); +#endif diff --git a/board/osiris/board.h b/board/osiris/board.h index abddb9104c..292a540087 100644 --- a/board/osiris/board.h +++ b/board/osiris/board.h @@ -106,7 +106,6 @@ #define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 #define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 #define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 #define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 @@ -145,6 +144,7 @@ #define RGB_GRID0_ROW 1 #define I2C_PORT_KBMCU I2C_PORT_RGBKB +#define CONFIG_KEYBOARD_FACTORY_TEST #ifndef __ASSEMBLER__ @@ -188,6 +188,11 @@ enum mft_channel { MFT_CH_COUNT }; +#ifdef CONFIG_KEYBOARD_FACTORY_TEST +extern const int keyboard_factory_scan_pins[][2]; +extern const int keyboard_factory_scan_pins_used; +#endif + #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ diff --git a/board/osiris/fans.c b/board/osiris/fans.c index 27f5bca929..fa5a8dc09a 100644 --- a/board/osiris/fans.c +++ b/board/osiris/fans.c @@ -31,16 +31,16 @@ static const struct fan_conf fan_conf_0 = { }; /* - * TOOD(b/181271666): thermistor placement and calibration + * TODO(b/234545460): thermistor placement and calibration * * Prototype fan spins at about 4200 RPM at 100% PWM, this * is specific to board ID 2 and might also apears in later * boards as well. */ static const struct fan_rpm fan_rpm_0 = { - .rpm_min = 2200, - .rpm_start = 2200, - .rpm_max = 4200, + .rpm_min = 3000, + .rpm_start = 3000, + .rpm_max = 6000, }; const struct fan_t fans[FAN_CH_COUNT] = { @@ -49,41 +49,3 @@ const struct fan_t fans[FAN_CH_COUNT] = { .rpm = &fan_rpm_0, }, }; - -#ifndef CONFIG_FANS - -/* - * TODO(b/181271666): use static fan speeds until fan and sensors are - * tuned. for now, use: - * - * AP off: 33% - * AP on: 100% - */ - -static void fan_slow(void) -{ - const int duty_pct = 33; - - ccprints("%s: speed %d%%", __func__, duty_pct); - - pwm_enable(PWM_CH_FAN, 1); - pwm_set_duty(PWM_CH_FAN, duty_pct); -} - -static void fan_max(void) -{ - const int duty_pct = 100; - - ccprints("%s: speed %d%%", __func__, duty_pct); - - pwm_enable(PWM_CH_FAN, 1); - pwm_set_duty(PWM_CH_FAN, duty_pct); -} - -DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT); - -#endif /* CONFIG_FANS */ diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc index c34ac9d44c..ca22ddba08 100644 --- a/board/osiris/gpio.inc +++ b/board/osiris/gpio.inc @@ -44,8 +44,6 @@ GPIO(EC_I2C_SENSOR_SCL, PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(EC_I2C_SENSOR_SDA, PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(EC_I2C_USB_C0_C2_PPC_BC_SCL, PIN(9, 2), GPIO_INPUT) GPIO(EC_I2C_USB_C0_C2_PPC_BC_SDA, PIN(9, 1), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_RT_SCL, PIN(D, 1), GPIO_INPUT) -GPIO(EC_I2C_USB_C0_C2_RT_SDA, PIN(D, 0), GPIO_INPUT) GPIO(EC_I2C_USB_C0_C2_TCPC_SCL, PIN(9, 0), GPIO_INPUT) GPIO(EC_I2C_USB_C0_C2_TCPC_SDA, PIN(8, 7), GPIO_INPUT) GPIO(EC_I2C_USB_C1_MIX_SCL, PIN(E, 4), GPIO_INPUT) @@ -74,8 +72,10 @@ GPIO(USB_C1_RT_RST_R_ODL, PIN(0, 2), GPIO_ODR_LOW) GPIO(VCCST_PWRGD_OD, PIN(A, 4), GPIO_ODR_LOW) GPIO(LED_1_L, PIN(C, 4), GPIO_OUT_HIGH) GPIO(LED_2_L, PIN(C, 3), GPIO_OUT_HIGH) -GPIO(KYBL_EN, PIN(A, 7), GPIO_ODR_LOW) -GPIO(AMP_PWR_EN, PIN(5, 7), GPIO_ODR_LOW) +GPIO(KYBL_EN, PIN(A, 7), GPIO_OUT_LOW) +GPIO(AMP_PWR_EN, PIN(5, 7), GPIO_OUT_LOW) +GPIO(EC_FAN_TACH_2, PIN(7, 3), GPIO_INPUT) +GPIO(RGB_KB_INT, PIN(5, 6), GPIO_INPUT) /* UART alternate functions */ ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */ @@ -120,11 +120,12 @@ UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */ UNUSED(PIN(6, 6)) /* GPIO66 */ UNUSED(PIN(8, 3)) /* GPIO83 */ UNUSED(PIN(7, 0)) /* GPIO70 */ -UNUSED(PIN(7, 3)) /* GPIO73 */ UNUSED(PIN(8, 1)) /* GPIO81 */ -UNUSED(PIN(5, 6)) /* GPIO56 */ UNUSED(PIN(9, 3)) /* GPIO93 */ UNUSED(PIN(9, 7)) /* GPIO97 */ +UNUSED(PIN(D, 0)) /* GPIOD0/I2C3_SDA0 */ +UNUSED(PIN(D, 1)) /* GPIOD1/I2C3_SCL0 */ + /* Pre-configured PSL balls: J8 K6 */ /* diff --git a/board/osiris/i2c.c b/board/osiris/i2c.c index c4b057ce2c..7c88d306a7 100644 --- a/board/osiris/i2c.c +++ b/board/osiris/i2c.c @@ -38,14 +38,6 @@ const struct i2c_port_t i2c_ports[] = { .sda = GPIO_EC_I2C_USB_C0_C2_PPC_BC_SDA, }, { - /* I2C3 */ - .name = "retimer0,2", - .port = I2C_PORT_USB_C0_C2_MUX, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL, - .sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA, - }, - { /* I2C4 C1 TCPC */ .name = "tcpc1", .port = I2C_PORT_USB_C1_TCPC, diff --git a/board/osiris/sensors.c b/board/osiris/sensors.c index 08ed297f5a..e02bee6a20 100644 --- a/board/osiris/sensors.c +++ b/board/osiris/sensors.c @@ -63,11 +63,9 @@ const struct temp_sensor_t temp_sensors[] = { BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* - * TODO(b/180681346): update for Alder Lake/brya + * TODO(b/234545460): update for Alder Lake/brya * - * Alder Lake specifies 100 C as maximum TDP temperature. THRMTRIP# occurs at - * 130 C. However, sensor is located next to DDR, so we need to use the lower - * DDR temperature limit (85 C) + * temperature limit, See thermal table in b/234545460#comment2 */ /* * TODO(b/202062363): Remove when clang is fixed. @@ -75,101 +73,36 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); #define THERMAL_CPU \ { \ .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ + .temp_fan_off = C_TO_K(25), \ + .temp_fan_max = C_TO_K(89), \ } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; -/* - * TODO(b/180681346): update for Alder Lake/brya - * - * Inductor limits - used for both charger and PP3300 regulator - * - * Need to use the lower of the charger IC, PP3300 regulator, and the inductors - * - * Charger max recommended temperature 100C, max absolute temperature 125C - * PP3300 regulator: operating range -40 C to 145 C - * - * Inductors: limit of 125c - * PCB: limit is 80c - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ -#define THERMAL_AMBIENT \ - { \ - .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ - }, \ - .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ - }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ - } -__maybe_unused static const struct ec_thermal_config thermal_ambient = - THERMAL_AMBIENT; - -/* - * Inductor limits - used for both charger and PP3300 regulator - * - * Need to use the lower of the charger IC, PP3300 regulator, and the inductors - * - * Charger max recommended temperature 125C, max absolute temperature 150C - * PP3300 regulator: operating range -40 C to 125 C - * - * Inductors: limit of 125c - * PCB: limit is 80c - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ -#define THERMAL_CHARGER \ - { \ - .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(105), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(120), \ - }, \ - .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ - }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(65), \ - } -__maybe_unused static const struct ec_thermal_config thermal_charger = - THERMAL_CHARGER; -/* - * TODO(b/180681346): update for brya WWAN module - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ -#define THERMAL_WWAN \ +#define THERMAL_UNUSED \ { \ .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(130), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(130), \ + [EC_TEMP_THRESH_HIGH] = 0, \ + [EC_TEMP_THRESH_HALT] = 0, \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(100), \ + [EC_TEMP_THRESH_HIGH] = 0, \ }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ + .temp_fan_off = 0, \ + .temp_fan_max = 0, \ } -__maybe_unused static const struct ec_thermal_config thermal_wwan = - THERMAL_WWAN; +__maybe_unused static const struct ec_thermal_config thermal_unused = + THERMAL_UNUSED; struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU, - [TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT, - [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, + [TEMP_SENSOR_2_AMBIENT] = THERMAL_UNUSED, + [TEMP_SENSOR_3_CHARGER] = THERMAL_UNUSED, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); diff --git a/board/prism/board.c b/board/prism/board.c index e35eaf9ef5..dc5c042db1 100644 --- a/board/prism/board.c +++ b/board/prism/board.c @@ -87,7 +87,6 @@ struct rgbkbd rgbkbds[] = { .col_len = RGB_GRID0_COL, .row_len = RGB_GRID0_ROW, }, - .init = &rgbkbd_default, .buf = grid0, }, [1] = { @@ -97,7 +96,6 @@ struct rgbkbd rgbkbds[] = { .col_len = RGB_GRID1_COL, .row_len = RGB_GRID1_ROW, }, - .init = &rgbkbd_default, .buf = grid1, }, }; diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c index c4d7c239a1..26dc64c7d5 100644 --- a/board/servo_v4p1/usb_pd_policy.c +++ b/board/servo_v4p1/usb_pd_policy.c @@ -1129,8 +1129,9 @@ static void do_cc(int cc_config_new) if (cc_config_new != cc_config) { if (!(cc_config & CC_DETACH)) { - /* Force detach */ - pd_power_supply_reset(DUT); + /* Force detach by disabling VBUS */ + chg_power_select(CHG_POWER_OFF); + dut_chg_en(0); /* Always set to 0 here so both CC lines are changed */ cc_config &= ~(CC_DISABLE_DTS & CC_ALLOW_SRC); diff --git a/board/shotzo/battery.c b/board/shotzo/battery.c new file mode 100644 index 0000000000..f71533accf --- /dev/null +++ b/board/shotzo/battery.c @@ -0,0 +1,349 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery_fuel_gauge.h" +#include "charge_state.h" +#include "common.h" + +/* + * Battery info for all shotzo battery types. Note that the fields + * start_charging_min/max and charging_min/max are not used for the charger. + * The effective temperature limits are given by discharging_min/max_c. + * + * Fuel Gauge (FG) parameters which are used for determining if the battery + * is connected, the appropriate ship mode (battery cutoff) command, and the + * charge/discharge FETs status. + * + * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery + * register. For some batteries, the charge/discharge FET bits are set when + * charging/discharging is active, in other types, these bits set mean that + * charging/discharging is disabled. Therefore, in addition to the mask for + * these bits, a disconnect value must be specified. Note that for TI fuel + * gauge, the charge/discharge FET status is found in Operation Status (0x54), + * but a read of Manufacturer Access (0x00) will return the lower 16 bits of + * Operation status which contains the FET status bits. + * + * The assumption for battery types supported is that the charge/discharge FET + * status can be read with a sb_read() command and therefore, only the register + * address, mask, and disconnect value need to be provided. + */ +const struct board_batt_params board_battery_info[] = { + /* DynaPack CosMX Battery Information */ + [BATTERY_DYNAPACK_COS] = { + .fuel_gauge = { + .manuf_name = "333-2C-DA-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* DynaPack ATL Battery Information */ + [BATTERY_DYNAPACK_ATL] = { + .fuel_gauge = { + .manuf_name = "333-27-DA-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* DynaPack HIGHPOWER Battery Information */ + [BATTERY_DYNAPACK_HIGHPOWER] = { + .fuel_gauge = { + .manuf_name = "333-2D-0D-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* DynaPack BYD Battery Information */ + [BATTERY_DYNAPACK_BYD] = { + .fuel_gauge = { + .manuf_name = "333-2E-0D-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* Samsung SDI Battery Information */ + [BATTERY_SAMSUNG_SDI] = { + .fuel_gauge = { + .manuf_name = "333-54-DA-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* Simplo CosMX Battery Information */ + [BATTERY_SIMPLO_COS] = { + .fuel_gauge = { + .manuf_name = "333-1C-DA-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* Simplo HIGHPOWER Battery Information */ + [BATTERY_SIMPLO_HIGHPOWER] = { + .fuel_gauge = { + .manuf_name = "333-1D-DA-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* CosMX Battery Information */ + [BATTERY_COS] = { + .fuel_gauge = { + .manuf_name = "333-AC-0D-A", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* CosMX B00C4473A9D0002 Battery Information */ + [BATTERY_COS_2] = { + .fuel_gauge = { + .manuf_name = "333-AC-DA-A", + .ship_mode = { + .reg_addr = 0x0, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 1, + .reg_addr = 0x0, + .reg_mask = 0x0006, + .disconnect_val = 0x0, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, /* mV */ + .voltage_min = 6000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, + + /* ATL GB-S20-4473A9-01H&020H Battery Information + * Gauge IC : RAJ240045 + */ + [BATTERY_ATL] = { + .fuel_gauge = { + .manuf_name = "313-B7-0D-A", + .ship_mode = { + .reg_addr = 0x0, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 0, + .reg_addr = 0x43, + .reg_mask = 0x0003, + .disconnect_val = 0x0, + .cfet_mask = 0x0002, + .cfet_off_val = 0x0, + }, + }, + .batt_info = { + .voltage_max = 8800, /* mV */ + .voltage_normal = 7700, /* mV */ + .voltage_min = 6000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -10, + .discharging_max_c = 60, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS; diff --git a/board/shotzo/board.c b/board/shotzo/board.c new file mode 100644 index 0000000000..a7cd45c7c6 --- /dev/null +++ b/board/shotzo/board.c @@ -0,0 +1,787 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shotzo board-specific configuration */ + +#include "adc_chip.h" +#include "button.h" +#include "cbi_fw_config.h" +#include "cbi_ssfc.h" +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "cros_board_info.h" +#include "driver/accel_bma2x2.h" +#include "driver/accel_bma422.h" +#include "driver/accelgyro_lsm6dsm.h" +#include "driver/bc12/pi3usb9201.h" +#include "driver/charger/sm5803.h" +#include "driver/temp_sensor/thermistor.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx.h" +#include "driver/usb_mux/it5205.h" +#include "gpio.h" +#include "hooks.h" +#include "intc.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "power.h" +#include "power_button.h" +#include "pwm.h" +#include "pwm_chip.h" +#include "switch.h" +#include "system.h" +#include "tablet_mode.h" +#include "task.h" +#include "tcpm/tcpci.h" +#include "temp_sensor.h" +#include "uart.h" +#include "usb_charge.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usb_pd_tcpm.h" + +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) + +#define INT_RECHECK_US 5000 + +uint32_t board_version; + +/* GPIO to enable/disable the USB Type-A port. */ +const int usb_port_enable[USB_PORT_COUNT] = { + GPIO_EN_USB_A_5V, +}; + +__override void board_process_pd_alert(int port) +{ + /* + * PD_INT task will process this alert, and that task is only needed on + * C1. + */ + if (port != 1) + return; + + if (gpio_get_level(GPIO_USB_C1_INT_ODL)) + return; + + sm5803_handle_interrupt(port); +} + +/* C0 interrupt line shared by BC 1.2 and charger */ +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +static void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +static void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +static void board_enable_hdmi_hpd(int enable) +{ + enum fw_config_db db = get_cbi_fw_config_db(); + int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD); + + if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) { + /* Check if we can report HDMI_HPD signal to CPU */ + if (enable) + gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd); + else + gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, 0); + } +} + +static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s) +{ + enum fw_config_db db = get_cbi_fw_config_db(); + int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD); + + if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) { + /* Do not report HDMI_HPD signal to CPU when system off. */ + if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) + gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd); + } else + button_interrupt(s); +} + +static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) +{ + cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event"); + pd_handle_cc_overvoltage(0); +} + +static void pen_detect_interrupt(enum gpio_signal s) +{ + int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL); + + gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect); +} + +/* Must come after other header files and interrupt handler declarations */ +#include "gpio_list.h" + +/* ADC channels */ +const struct adc_t adc_channels[] = { + [ADC_VSNS_PP3300_A] = { + .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 + }, + [ADC_TEMP_SENSOR_1] = { + .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 + }, + [ADC_TEMP_SENSOR_2] = { + .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 + }, + [ADC_SUB_ANALOG] = { + .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 + }, + [ADC_TEMP_SENSOR_3] = { + .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 + }, + [ADC_TEMP_SENSOR_4] = { + .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 + }, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* BC 1.2 chips */ +const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { + { + .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + .flags = PI3USB9201_ALWAYS_POWERED, + }, + { + .i2c_port = I2C_PORT_SUB_USB_C1, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + .flags = PI3USB9201_ALWAYS_POWERED, + }, +}; + +/* Charger chips */ +const struct charger_config_t chg_chips[] = { + [CHARGER_PRIMARY] = { + .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS, + .drv = &sm5803_drv, + }, + [CHARGER_SECONDARY] = { + .i2c_port = I2C_PORT_SUB_USB_C1, + .i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS, + .drv = &sm5803_drv, + }, +}; + +/* TCPCs */ +const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + .drv = &it83xx_tcpm_drv, + }, + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_SUB_USB_C1, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + }, +}; + +/* USB Muxes */ +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .usb_port = 0, + .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, + .driver = &it5205_usb_mux_driver, + }, + { + .usb_port = 1, + .i2c_port = I2C_PORT_SUB_USB_C1, + .i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, +}; + +/* Sensor Mutexes */ +static struct mutex g_lid_mutex; +static struct mutex g_base_mutex; + +/* Sensor Data */ +static struct accelgyro_saved_data_t g_bma253_data; +static struct accelgyro_saved_data_t g_bma422_data; +static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; + +/* Matrix to rotate accelrator into standard reference frame */ +static const mat33_fp_t base_standard_ref = { + { FLOAT_TO_FP(1), 0, 0}, + { 0, FLOAT_TO_FP(-1), 0}, + { 0, 0, FLOAT_TO_FP(-1)} +}; + +static const mat33_fp_t lid_standard_ref = { + { FLOAT_TO_FP(1), 0, 0}, + { 0, FLOAT_TO_FP(-1), 0}, + { 0, 0, FLOAT_TO_FP(-1)} +}; + +/* Drivers */ +struct motion_sensor_t motion_sensors[] = { + [LID_ACCEL] = { + .name = "Lid Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_BMA255, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_LID, + .drv = &bma2x2_accel_drv, + .mutex = &g_lid_mutex, + .drv_data = &g_bma253_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS, + .rot_standard_ref = &lid_standard_ref, + .default_range = 2, + .min_frequency = BMA255_ACCEL_MIN_FREQ, + .max_frequency = BMA255_ACCEL_MAX_FREQ, + .config = { + [SENSOR_CONFIG_EC_S0] = { + .odr = 10000 | ROUND_UP_FLAG, + }, + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + }, + }, + }, + [BASE_ACCEL] = { + .name = "Base Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_LSM6DSM, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_BASE, + .drv = &lsm6dsm_drv, + .mutex = &g_base_mutex, + .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, + MOTIONSENSE_TYPE_ACCEL), + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, + .rot_standard_ref = &base_standard_ref, + .default_range = 4, /* g */ + .min_frequency = LSM6DSM_ODR_MIN_VAL, + .max_frequency = LSM6DSM_ODR_MAX_VAL, + .config = { + [SENSOR_CONFIG_EC_S0] = { + .odr = 13000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + }, + }, + [BASE_GYRO] = { + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_LSM6DSM, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &lsm6dsm_drv, + .mutex = &g_base_mutex, + .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, + MOTIONSENSE_TYPE_GYRO), + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, + .default_range = 1000 | ROUND_UP_FLAG, /* dps */ + .rot_standard_ref = &base_standard_ref, + .min_frequency = LSM6DSM_ODR_MIN_VAL, + .max_frequency = LSM6DSM_ODR_MAX_VAL, + }, +}; + +unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); + +struct motion_sensor_t bma422_lid_accel = { + .name = "Lid Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_BMA422, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_LID, + .drv = &bma4_accel_drv, + .mutex = &g_lid_mutex, + .drv_data = &g_bma422_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY, + .rot_standard_ref = &lid_standard_ref, + .default_range = 2, + .min_frequency = BMA4_ACCEL_MIN_FREQ, + .max_frequency = BMA4_ACCEL_MAX_FREQ, + .config = { + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 12500 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, + }, + /* Sensor on in S3 */ + [SENSOR_CONFIG_EC_S3] = { + .odr = 12500 | ROUND_UP_FLAG, + .ec_rate = 0, + }, + }, +}; + +static void board_update_motion_sensor_config(void) +{ + if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_BMA422) + motion_sensors[LID_ACCEL] = bma422_lid_accel; +} + +void board_init(void) +{ + int on; + enum fw_config_db db = get_cbi_fw_config_db(); + + if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) { + /* Select HDMI option */ + gpio_set_level(GPIO_HDMI_SEL_L, 0); + } else { + /* Select AUX option */ + gpio_set_level(GPIO_HDMI_SEL_L, 1); + } + + gpio_enable_interrupt(GPIO_USB_C0_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_INT_ODL); + + /* Store board version for use in determining charge limits */ + cbi_get_board_version(&board_version); + + /* + * If interrupt lines are already low, schedule them to be processed + * after inits are completed. + */ + if (!gpio_get_level(GPIO_USB_C0_INT_ODL)) + hook_call_deferred(&check_c0_line_data, 0); + if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) + hook_call_deferred(&check_c1_line_data, 0); + + gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL); + + if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) { + motion_sensor_count = ARRAY_SIZE(motion_sensors); + /* Enable Base Accel interrupt */ + gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L); + + board_update_motion_sensor_config(); + } else { + motion_sensor_count = 0; + gmr_tablet_switch_disable(); + /* Base accel is not stuffed, don't allow line to float */ + gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, + GPIO_INPUT | GPIO_PULL_DOWN); + } + + gpio_enable_interrupt(GPIO_PEN_DET_ODL); + + /* Make sure pen detection is triggered or not at sysjump */ + if (!gpio_get_level(GPIO_PEN_DET_ODL)) + gpio_set_level(GPIO_EN_PP5000_PEN, 1); + + /* Make sure HDMI_HPD signal can be reported to CPU at sysjump */ + board_enable_hdmi_hpd(1); + + /* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */ + sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1); + sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1); + + if (board_get_charger_chip_count() > 1) { + /* Charger on the sub-board will be a push-pull GPIO */ + sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0); + } + + /* Turn on 5V if the system is on, otherwise turn it off */ + on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND | + CHIPSET_STATE_SOFT_OFF); + board_power_5v_enable(on); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +static void board_resume(void) +{ + sm5803_disable_low_power_mode(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + sm5803_disable_low_power_mode(CHARGER_SECONDARY); + + /* Enable reporting HDMI_HPD to CPU when system resume */ + board_enable_hdmi_hpd(1); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT); + +static void board_suspend(void) +{ + sm5803_enable_low_power_mode(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + sm5803_enable_low_power_mode(CHARGER_SECONDARY); +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT); + +static void board_shutdown(void) +{ + /* Disable reporting HDMI_HPD to CPU at shutdown */ + board_enable_hdmi_hpd(0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_shutdown, HOOK_PRIO_DEFAULT); + +void board_hibernate(void) +{ + /* + * Put all charger ICs present into low power mode before entering + * z-state. + */ + sm5803_hibernate(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + sm5803_hibernate(CHARGER_SECONDARY); +} + +__override void board_ocpc_init(struct ocpc_data *ocpc) +{ + /* There's no provision to measure Isys */ + ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP; +} + +__override void board_pulse_entering_rw(void) +{ + /* + * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin + * which is active high by default. This causes Cr50 to think that the + * EC has jumped to its RW image even though this may not be the case. + * The pin is changed to GPIO_EC_ENTERING_RW2. + */ + gpio_set_level(GPIO_EC_ENTERING_RW, 1); + gpio_set_level(GPIO_EC_ENTERING_RW2, 1); + usleep(MSEC); + gpio_set_level(GPIO_EC_ENTERING_RW, 0); + gpio_set_level(GPIO_EC_ENTERING_RW2, 0); +} + +void board_reset_pd_mcu(void) +{ + /* + * Nothing to do. TCPC C0 is internal, TCPC C1 reset pin is not + * connected to the EC. + */ +} + +__override void board_power_5v_enable(int enable) +{ + /* + * Motherboard has a GPIO to turn on the 5V regulator, but the sub-board + * sets it through the charger GPIO. + */ + gpio_set_level(GPIO_EN_PP5000, !!enable); + + if (board_get_charger_chip_count() > 1) { + if (sm5803_set_gpio0_level(1, !!enable)) + CPRINTUSB("Failed to %sable sub rails!", enable ? + "en" : "dis"); + } +} + +__override uint8_t board_get_usb_pd_port_count(void) +{ + enum fw_config_db db = get_cbi_fw_config_db(); + + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI + || db == DB_1A_HDMI_LTE) + return CONFIG_USB_PD_PORT_MAX_COUNT - 1; + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A + || db == DB_1C_1A_LTE) + return CONFIG_USB_PD_PORT_MAX_COUNT; + + ccprints("Unhandled DB configuration: %d", db); + return 0; +} + +__override uint8_t board_get_charger_chip_count(void) +{ + enum fw_config_db db = get_cbi_fw_config_db(); + + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI + || db == DB_1A_HDMI_LTE) + return CHARGER_NUM - 1; + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A + || db == DB_1C_1A_LTE) + return CHARGER_NUM; + + ccprints("Unhandled DB configuration: %d", db); + return 0; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c) + */ + + uint16_t status = 0; + int regval; + + /* Check whether TCPC 1 pulled the shared interrupt line */ + if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); + + /* Limit C1 on board version 0 to 2.0 A */ + if ((board_version == 0) && (port == 1)) + icl = MIN(icl, 2000); + /* + * TODO(b/151955431): Characterize the input current limit in case a + * scaling needs to be applied here + */ + charge_set_input_current_limit(icl, charge_mv); +} + +int board_set_active_charge_port(int port) +{ + int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count()); + + if (!is_valid_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + if (port == CHARGE_PORT_NONE) { + CPRINTUSB("Disabling all charge ports"); + + sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0); + + if (board_get_charger_chip_count() > 1) + sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0); + + return EC_SUCCESS; + } + + CPRINTUSB("New chg p%d", port); + + /* + * Ensure other port is turned off, then enable new charge port + */ + if (port == 0) { + if (board_get_charger_chip_count() > 1) + sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0); + sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1); + + } else { + sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0); + sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1); + } + + return EC_SUCCESS; +} + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_set_level(GPIO_EN_USB_C0_CC1_VCONN, !!enabled); + else + gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int current; + + if (port < 0 || port > board_get_usb_pd_port_count()) + return; + + current = (rp == TYPEC_RP_3A0) ? 3000 : 1500; + + charger_set_otg_current_voltage(port, current, 5000); +} + +/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ +const struct pwm_t pwm_channels[] = { + [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } +}; +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +/* Thermistors */ +const struct temp_sensor_t temp_sensors[] = { + [TEMP_SENSOR_1] = {.name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1}, + [TEMP_SENSOR_2] = {.name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_3] = {.name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_4] = {.name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4}, +}; +BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); + +/* This callback disables keyboard when convertibles are fully open */ +__override void lid_angle_peripheral_enable(int enable) +{ + int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON); + + /* + * If the lid is in tablet position via other sensors, + * ignore the lid angle, which might be faulty then + * disable keyboard. + */ + if (tablet_get_mode()) + enable = 0; + + if (enable) { + keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE); + } else { + /* + * Ensure that the chipset is off before disabling the keyboard. + * When the chipset is on, the EC keeps the keyboard enabled and + * the AP decides whether to ignore input devices or not. + */ + if (!chipset_in_s0) + keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE); + } +} + +__override void ocpc_get_pid_constants(int *kp, int *kp_div, + int *ki, int *ki_div, + int *kd, int *kd_div) +{ + *kp = 3; + *kp_div = 20; + + *ki = 3; + *ki_div = 125; + + *kd = 4; + *kd_div = 40; +} + +#ifdef CONFIG_KEYBOARD_FACTORY_TEST +/* + * Map keyboard connector pins to EC GPIO pins for factory test. + * Pins mapped to {-1, -1} are skipped. + * The connector has 24 pins total, and there is no pin 0. + */ +const int keyboard_factory_scan_pins[][2] = { + {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, + {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, + {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, + {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, + {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, + {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, +}; + +const int keyboard_factory_scan_pins_used = + ARRAY_SIZE(keyboard_factory_scan_pins); +#endif diff --git a/board/shotzo/board.h b/board/shotzo/board.h new file mode 100644 index 0000000000..7235499624 --- /dev/null +++ b/board/shotzo/board.h @@ -0,0 +1,152 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shotzo board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Select Baseboard features */ +#define VARIANT_DEDEDE_EC_IT8320 +#include "baseboard.h" + +#undef GPIO_VOLUME_UP_L +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD + +/* Battery */ +#define CONFIG_BATTERY_FUEL_GAUGE + +/* BC 1.2 */ +#define CONFIG_BC12_DETECT_PI3USB9201 + +/* Charger */ +#define CONFIG_CHARGE_RAMP_HW +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_USB_PD_VBUS_DETECT_CHARGER +#define CONFIG_USB_PD_5V_CHARGER_CTRL +#define CONFIG_CHARGER_OTG +#undef CONFIG_CHARGER_SINGLE_CHIP +#define CONFIG_OCPC +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ + +/* PWM */ +#define CONFIG_PWM + +/* Sensors */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +/* Sensors without hardware FIFO are in forced mode */ +#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) + +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO + +/* Enable sensor fifo, must also define the _SIZE and _THRES */ +#define CONFIG_ACCEL_FIFO +/* Power of 2 - Too large of a fifo causes too much timestamp jitter */ +#define CONFIG_ACCEL_FIFO_SIZE 256 +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) + +#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT + +#define CONFIG_LID_ANGLE +#define CONFIG_LID_ANGLE_UPDATE +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL + +#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) + +#define CONFIG_TABLET_MODE +#define CONFIG_TABLET_MODE_SWITCH +#define CONFIG_GMR_TABLET_MODE + +/* Keyboard */ +#define CONFIG_KEYBOARD_FACTORY_TEST +#define CONFIG_PWM_KBLIGHT + +/* TCPC */ +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPC_LOW_POWER + +/* Thermistors */ +#define CONFIG_TEMP_SENSOR +#define CONFIG_THERMISTOR +#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B + +/* USB Mux and Retimer */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ + +/* USB Type A Features */ +#define USB_PORT_COUNT 1 +#define CONFIG_USB_PORT_POWER_DUMB + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +enum chg_id { + CHARGER_PRIMARY, + CHARGER_SECONDARY, + CHARGER_NUM, +}; + +enum pwm_channel { + PWM_CH_KBLIGHT, + PWM_CH_COUNT, +}; + +/* Motion sensors */ +enum sensor_id { + LID_ACCEL, + BASE_ACCEL, + BASE_GYRO, + SENSOR_COUNT +}; + +/* ADC channels */ +enum adc_channel { + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_CH_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_1, + TEMP_SENSOR_2, + TEMP_SENSOR_3, + TEMP_SENSOR_4, + TEMP_SENSOR_COUNT +}; + +/* List of possible batteries */ +enum battery_type { + BATTERY_DYNAPACK_COS, + BATTERY_DYNAPACK_ATL, + BATTERY_DYNAPACK_HIGHPOWER, + BATTERY_DYNAPACK_BYD, + BATTERY_SAMSUNG_SDI, + BATTERY_SIMPLO_COS, + BATTERY_SIMPLO_HIGHPOWER, + BATTERY_COS, + BATTERY_COS_2, + BATTERY_ATL, + BATTERY_TYPE_COUNT, +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/shotzo/build.mk b/board/shotzo/build.mk new file mode 100644 index 0000000000..4d677400a9 --- /dev/null +++ b/board/shotzo/build.mk @@ -0,0 +1,15 @@ +# -*- makefile -*- +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=it83xx +CHIP_FAMILY:=it8320 +CHIP_VARIANT:=it8320dx +BASEBOARD:=dedede + +board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o +board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/board/shotzo/cbi_ssfc.c b/board/shotzo/cbi_ssfc.c new file mode 100644 index 0000000000..9f1383b455 --- /dev/null +++ b/board/shotzo/cbi_ssfc.c @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "cbi_ssfc.h" +#include "common.h" +#include "console.h" +#include "cros_board_info.h" +#include "hooks.h" + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) + +/* Cache SSFC on init since we don't expect it to change in runtime */ +static union dedede_cbi_ssfc cached_ssfc; +BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t)); + +static void cbi_ssfc_init(void) +{ + if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS) + /* Default to 0 when CBI isn't populated */ + cached_ssfc.raw_value = 0; + + CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value); +} +DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); + +enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) +{ + return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; +} + +enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) +{ + return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; +} diff --git a/board/shotzo/cbi_ssfc.h b/board/shotzo/cbi_ssfc.h new file mode 100644 index 0000000000..ddfada8a68 --- /dev/null +++ b/board/shotzo/cbi_ssfc.h @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef _DEDEDE_CBI_SSFC__H_ +#define _DEDEDE_CBI_SSFC__H_ + +#include "stdint.h" + +/**************************************************************************** + * Dedede CBI Second Source Factory Cache + */ + +/* + * Base Sensor (Bits 0-2) + */ +enum ec_ssfc_base_sensor { + SSFC_SENSOR_BASE_DEFAULT = 0, + SSFC_SENSOR_BMI160 = 1, + SSFC_SENSOR_ICM426XX = 2, + SSFC_SENSOR_LSM6DSM = 3, + SSFC_SENSOR_ICM42607 = 4 +}; + +/* + * Lid Sensor (Bits 3-5) + */ +enum ec_ssfc_lid_sensor { + SSFC_SENSOR_LID_DEFAULT = 0, + SSFC_SENSOR_BMA255 = 1, + SSFC_SENSOR_BMA422 = 2, +}; + +union dedede_cbi_ssfc { + struct { + uint32_t base_sensor : 3; + uint32_t lid_sensor : 3; + uint32_t reserved_2 : 26; + }; + uint32_t raw_value; +}; + +/** + * Get the Base sensor type from SSFC_CONFIG. + * + * @return the Base sensor board type. + */ +enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); + +/** + * Get the Lid sensor type from SSFC_CONFIG. + * + * @return the Lid sensor board type. + */ +enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); + + +#endif /* _DEDEDE_CBI_SSFC__H_ */ diff --git a/board/shotzo/ec.tasklist b/board/shotzo/ec.tasklist new file mode 100644 index 0000000000..99f42b5579 --- /dev/null +++ b/board/shotzo/ec.tasklist @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * See CONFIG_TASK_LIST in config.h for details. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE) diff --git a/board/shotzo/gpio.inc b/board/shotzo/gpio.inc new file mode 100644 index 0000000000..5d00a0b0e7 --- /dev/null +++ b/board/shotzo/gpio.inc @@ -0,0 +1,148 @@ +/* -*- mode:c -*- + * + * Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +/* Power State interrupts */ +GPIO_INT(SLP_S4_L, PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_S3_L, PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) +GPIO_INT(SLP_S0_L, PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_SUS_L, PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(VCCIN_AUX_VID0, PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(RSMRST_PWRGD_L, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(CPU_C10_GATE_L, PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_DRAM_OD, PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) +GPIO_INT(PG_PP1050_ST_OD, PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(VCCIN_AUX_VID1, PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_VCCIO_EXT_OD, PIN(D, 7), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) +GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) + +GPIO_INT(H1_EC_PWR_BTN_ODL, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt) +#ifdef CONFIG_LOW_POWER_IDLE +/* Used to wake up the EC from Deep Doze mode when writing to console */ +GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt) /* UART_DBG_TX_EC_RX */ +#endif + +/* USB-C interrupts */ +GPIO_INT(USB_C0_INT_ODL, PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */ +GPIO_INT(USB_C1_INT_ODL, PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */ +GPIO_INT(USB_C0_CCSBU_OVP_ODL, PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */ + +/* Other interrupts */ +GPIO_INT(LID_OPEN, PIN(F, 3), GPIO_INT_BOTH, lid_interrupt) +GPIO_INT(LID_360_L, PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr) +GPIO_INT(VOLDN_BTN_ODL, PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD, PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt) +GPIO_INT(BASE_SIXAXIS_INT_L, PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt) +GPIO_INT(EC_WP_OD, PIN(A, 6), GPIO_INT_BOTH, switch_interrupt) +GPIO_INT(PEN_DET_ODL, PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt) + +/* Power sequence GPIOs */ +GPIO(EC_AP_RTCRST, PIN(K, 2), GPIO_OUT_LOW) +GPIO(EC_AP_PWR_BTN_ODL, PIN(B, 6), GPIO_ODR_HIGH) +GPIO(EC_AP_DPWROK, PIN(L, 7), GPIO_OUT_LOW) +GPIO(EC_AP_RSMRST_L, PIN(H, 0), GPIO_OUT_LOW) +GPIO(EC_AP_WAKE_ODL, PIN(D, 5), GPIO_ODR_HIGH) +GPIO(SYS_RST_ODL, PIN(D, 1), GPIO_ODR_HIGH) +GPIO(EC_AP_SYS_PWROK, PIN(F, 2), GPIO_OUT_LOW) +GPIO(PG_PP5000_U_OD, PIN(E, 3), GPIO_INPUT) +GPIO(EN_PP3300_A, PIN(C, 5), GPIO_OUT_LOW) +GPIO(EC_AP_PCH_PWROK_OD, PIN(D, 6), GPIO_ODR_LOW) +GPIO(EN_PP5000_U, PIN(K, 5), GPIO_OUT_LOW) +/* TODO(b:149775160) - Modify if needed if we ever use this signal. */ +GPIO(EN_VCCST, PIN(D, 4), GPIO_INPUT) +GPIO(EN_VCCIO_EXT, PIN(B, 2), GPIO_OUT_LOW) +GPIO(EC_PROCHOT_ODL, PIN(I, 1), GPIO_ODR_HIGH | GPIO_SEL_1P8V) +GPIO(EC_AP_VCCST_PWRGD_OD, PIN(E, 5), GPIO_ODR_LOW) +GPIO(ALL_SYS_PWRGD, PIN(B, 7), GPIO_OUT_LOW) +GPIO(EN_SLP_Z, PIN(K, 3), GPIO_OUT_LOW) + +/* Required for icelake chipset code, but implemented through other means for dedede */ +UNIMPLEMENTED(AC_PRESENT) +UNIMPLEMENTED(PG_EC_DSW_PWROK) +UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD) + +/* I2C pins - Alternate function below configures I2C module on these pins */ +GPIO(EC_I2C_EEPROM_SCL, PIN(B, 3), GPIO_INPUT) +GPIO(EC_I2C_EEPROM_SDA, PIN(B, 4), GPIO_INPUT) +GPIO(EC_I2C_BATTERY_SCL, PIN(C, 1), GPIO_INPUT) +GPIO(EC_I2C_BATTERY_SDA, PIN(C, 2), GPIO_INPUT) +GPIO(EC_I2C_SENSOR_SCL, PIN(F, 6), GPIO_INPUT | GPIO_SEL_1P8V) +GPIO(EC_I2C_SENSOR_SDA, PIN(F, 7), GPIO_INPUT | GPIO_SEL_1P8V) +GPIO(EC_I2C_SUB_USB_C1_SCL, PIN(E, 0), GPIO_INPUT) +GPIO(EC_I2C_SUB_USB_C1_SDA, PIN(E, 7), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_SCL, PIN(A, 4), GPIO_INPUT) +GPIO(EC_I2C_USB_C0_SDA, PIN(A, 5), GPIO_INPUT) + +/* USB pins */ +GPIO(EN_USB_A_5V, PIN(L, 6), GPIO_OUT_LOW) +GPIO(EN_USB_C0_CC1_VCONN, PIN(H, 4), GPIO_OUT_LOW) +GPIO(EN_USB_C0_CC2_VCONN, PIN(H, 6), GPIO_OUT_LOW) +GPIO(EC_AP_USB_C0_HPD, PIN(L, 4), GPIO_OUT_LOW) +GPIO(EC_AP_USB_C1_HDMI_HPD, PIN(K, 7), GPIO_OUT_LOW) +GPIO(USB_C0_FRS, PIN(C, 4), GPIO_OUT_LOW) +GPIO(HDMI_SEL_L, PIN(C, 6), GPIO_OUT_HIGH) + +/* MKBP event synchronization */ +GPIO(EC_AP_MKBP_INT_L, PIN(L, 5), GPIO_ODR_HIGH) + +/* Misc pins which will run to the I/O board */ +GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT) +GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT) + +/* Misc */ +GPIO(EN_BL_OD, PIN(K, 4), GPIO_ODR_LOW) +GPIO(EC_ENTERING_RW, PIN(G, 0), GPIO_OUT_LOW) +GPIO(EC_ENTERING_RW2, PIN(C, 7), GPIO_OUT_LOW) +GPIO(CCD_MODE_ODL, PIN(H, 5), GPIO_ODR_HIGH) +GPIO(EC_BATTERY_PRES_ODL, PIN(I, 4), GPIO_INPUT) +GPIO(EN_KB_BL, PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */ +GPIO(ECH1_PACKET_MODE, PIN(H, 1), GPIO_OUT_LOW) +GPIO(EN_PP5000_PEN, PIN(B, 5), GPIO_OUT_LOW) + +/* NC pins, enable internal pull-down to avoid floating state. */ +GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN) +GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN) + +/* LED */ +GPIO(BAT_LED_AMBER_L, PIN(A, 1), GPIO_OUT_HIGH) +GPIO(BAT_LED_WHITE_L, PIN(A, 2), GPIO_OUT_HIGH) +GPIO(PWR_LED_WHITE_L, PIN(A, 3), GPIO_OUT_HIGH) + +/* Alternate functions GPIO definitions */ +/* Keyboard */ +ALTERNATE(PIN_MASK(KSI, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSI0-7 */ +ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO8-15 */ +ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0) /* KSO0-1, 3-7 */ +GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH) /* KSO2 inverted */ + +/* UART */ +ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), 0, MODULE_UART, 0) /* UART for debug */ + +/* I2C */ +ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), 0, MODULE_I2C, 0) /* I2C0 */ +ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), 0, MODULE_I2C, 0) /* I2C1 */ +ALTERNATE(PIN_MASK(F, BIT(6) | BIT(7)), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C2 - 1.8V */ +ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), 0, MODULE_I2C, 0) /* I2C4 */ +ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0) /* I2C5 */ + +/* ADC */ +ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0) /* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */ +ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0) /* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */ + +/* PWM */ +ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) /* KB_BL_PWM */ diff --git a/board/shotzo/led.c b/board/shotzo/led.c new file mode 100644 index 0000000000..761b4b4047 --- /dev/null +++ b/board/shotzo/led.c @@ -0,0 +1,204 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shotzo specific LED settings. */ + +#include "cbi_fw_config.h" +#include "charge_state.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "led_common.h" + +#define BAT_LED_ON 0 +#define BAT_LED_OFF 1 + +#define POWER_LED_ON 0 +#define POWER_LED_OFF 1 + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +enum led_color { + LED_OFF = 0, + LED_AMBER, + LED_WHITE, + LED_COLOR_COUNT /* Number of colors, not a color itself */ +}; + +static int led_set_color_battery(enum led_color color) +{ + switch (color) { + case LED_OFF: + gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF); + gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF); + break; + case LED_WHITE: + gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON); + gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF); + break; + case LED_AMBER: + gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF); + gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON); + break; + default: + return EC_ERROR_UNKNOWN; + } + return EC_SUCCESS; +} + +static int led_set_color_power(enum led_color color) +{ + switch (color) { + case LED_OFF: + gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_OFF); + break; + case LED_WHITE: + gpio_set_level(GPIO_PWR_LED_WHITE_L, POWER_LED_ON); + break; + default: + return EC_ERROR_UNKNOWN; + } + return EC_SUCCESS; +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + switch (led_id) { + case EC_LED_ID_BATTERY_LED: + brightness_range[EC_LED_COLOR_WHITE] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + break; + case EC_LED_ID_POWER_LED: + brightness_range[EC_LED_COLOR_WHITE] = 1; + break; + default: + break; + } +} + +static int led_set_color(enum ec_led_id led_id, enum led_color color) +{ + int rv; + + switch (led_id) { + case EC_LED_ID_BATTERY_LED: + rv = led_set_color_battery(color); + break; + case EC_LED_ID_POWER_LED: + rv = led_set_color_power(color); + break; + default: + return EC_ERROR_UNKNOWN; + } + return rv; +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color(led_id, LED_WHITE); + else if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color(led_id, LED_AMBER); + else + led_set_color(led_id, LED_OFF); + + return EC_SUCCESS; +} + +static void led_set_battery(void) +{ + static int battery_ticks; + static int power_ticks; + uint32_t chflags = charge_get_flags(); + + battery_ticks++; + + /* + * Override battery LED for Drawlet/Drawman, Drawlet/Drawman + * don't have power LED, blinking battery white LED to indicate + * system suspend without charging. + */ + if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) { + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && + charge_get_state() != PWR_STATE_CHARGE) { + led_set_color_battery(power_ticks++ & 0x2 ? + LED_WHITE : LED_OFF); + return; + } + } + + power_ticks = 0; + + switch (charge_get_state()) { + case PWR_STATE_CHARGE: + led_set_color_battery(LED_AMBER); + break; + case PWR_STATE_DISCHARGE_FULL: + if (extpower_is_present()) { + led_set_color_battery(LED_WHITE); + break; + } + /* Intentional fall-through */ + case PWR_STATE_DISCHARGE: + /* + * Blink white light (1 sec on, 1 sec off) + * when battery capacity is less than 10% + */ + if (charge_get_percent() < 10) + led_set_color_battery( + (battery_ticks & 0x2) ? LED_WHITE : LED_OFF); + else + led_set_color_battery(LED_OFF); + break; + case PWR_STATE_ERROR: + led_set_color_battery( + (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + break; + case PWR_STATE_CHARGE_NEAR_FULL: + led_set_color_battery(LED_WHITE); + break; + case PWR_STATE_IDLE: /* External power connected in IDLE */ + if (chflags & CHARGE_FLAG_FORCE_IDLE) + led_set_color_battery( + (battery_ticks & 0x2) ? LED_AMBER : LED_OFF); + else + led_set_color_battery(LED_WHITE); + break; + default: + /* Other states don't alter LED behavior */ + break; + } +} + +static void led_set_power(void) +{ + static int power_tick; + + power_tick++; + + if (chipset_in_state(CHIPSET_STATE_ON)) + led_set_color_power(LED_WHITE); + else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) + led_set_color_power( + (power_tick & 0x2) ? LED_WHITE : LED_OFF); + else + led_set_color_power(LED_OFF); +} + +/* Called by hook task every TICK */ +static void led_tick(void) +{ + if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) + led_set_power(); + + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) + led_set_battery(); +} +DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT); diff --git a/board/shotzo/usb_pd_policy.c b/board/shotzo/usb_pd_policy.c new file mode 100644 index 0000000000..1bba648eba --- /dev/null +++ b/board/shotzo/usb_pd_policy.c @@ -0,0 +1,85 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "battery_smart.h" +#include "charge_manager.h" +#include "charger.h" +#include "chipset.h" +#include "common.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/tcpci.h" +#include "usb_pd.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +int pd_check_vconn_swap(int port) +{ + /* Allow VCONN swaps if the AP is on */ + return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON); +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) + return rv; + + /* Disable Vbus discharge */ + sm5803_set_vbus_disch(port, 0); + + /* Provide Vbus */ + charger_enable_otg_power(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + int vbus_voltage; + + /* If we're unable to speak to the charger, best to guess false */ + if (charger_get_vbus_voltage(port, &vbus_voltage)) + return false; + + if (level == VBUS_SAFE0V) + return vbus_voltage < PD_V_SAFE0V_MAX; + else if (level == VBUS_PRESENT) + return vbus_voltage > PD_V_SAFE5V_MIN; + else + return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; +} + +int pd_snk_is_vbus_provided(int port) +{ + return sm5803_is_vbus_present(port); +} diff --git a/board/shotzo/vif_override.xml b/board/shotzo/vif_override.xml new file mode 100644 index 0000000000..32736caf64 --- /dev/null +++ b/board/shotzo/vif_override.xml @@ -0,0 +1,3 @@ +<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File + Definition from the USB-IF. +--> diff --git a/board/taniks/board.c b/board/taniks/board.c index 2c2cf4cb44..894e055b9a 100644 --- a/board/taniks/board.c +++ b/board/taniks/board.c @@ -29,6 +29,7 @@ #include "tablet_mode.h" #include "throttle_ap.h" #include "usbc_config.h" +#include "rgb_keyboard.h" #include "gpio_list.h" /* Must come after other header files. */ @@ -46,6 +47,12 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); /******************************************************************************/ +const struct rgbkbd_init rgbkbd_init_taniks = { + .gcc = RGBKBD_MAX_GCC_LEVEL / 2, + .scale = { .r = 190, .g = 255, .b = 255 }, + .color = { .r = 255, .g = 255, .b = 255 }, +}; + __override void board_cbi_init(void) { config_usb_db_type(); @@ -53,16 +60,9 @@ __override void board_cbi_init(void) void board_init(void) { - - if (ec_cfg_has_tabletmode()) { - - } else { - /* only clamshell todo */ - gpio_set_flags(GPIO_EC_VOLUP_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_EC_VOLDN_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN); - button_disable_gpio(BUTTON_VOLUME_UP); - button_disable_gpio(BUTTON_VOLUME_DOWN); - } +#ifdef SECTION_IS_RW + rgbkbd_register_init_setting(&rgbkbd_init_taniks); +#endif } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/taniks/board.h b/board/taniks/board.h index 7e04872bb6..0756395afa 100644 --- a/board/taniks/board.h +++ b/board/taniks/board.h @@ -23,10 +23,12 @@ /* Baseboard features */ #include "baseboard.h" -#define CONFIG_SYSTEM_UNLOCKED -#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK - +#undef CONFIG_CMD_POWERINDEBUG #undef CONFIG_MKBP_INPUT_DEVICES +#undef CONFIG_TABLET_MODE +#undef CONFIG_GMR_TABLET_MODE +#undef CONFIG_TABLET_MODE_SWITCH +#undef CONFIG_VOLUME_BUTTONS /* * This will happen automatically on NPCX9 ES2 and later. Do not remove @@ -168,8 +170,6 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL #define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL #define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL #define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ @@ -244,7 +244,7 @@ #define CONFIG_RGB_KEYBOARD #define CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ #endif -#define RGB_GRID0_COL 11 +#define RGB_GRID0_COL 8 #define RGB_GRID0_ROW 6 #ifndef __ASSEMBLER__ diff --git a/board/taniks/gpio.inc b/board/taniks/gpio.inc index 33d541785a..0dff3216de 100644 --- a/board/taniks/gpio.inc +++ b/board/taniks/gpio.inc @@ -9,10 +9,7 @@ /* INTERRUPT GPIOs: */ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) -GPIO_INT(EC_IMU_INT_R_L, PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt) GPIO_INT(EC_PROCHOT_IN_L, PIN(2, 4), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt) -GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_WP_ODL, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) GPIO_INT(GSC_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) @@ -22,7 +19,6 @@ GPIO_INT(SEQ_EC_RSMRST_ODL, PIN(E, 2), GPIO_INT_BOTH, power_signal_ GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_SUS_L, PIN(2, 5), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SYS_SLP_S0IX_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(TABLET_MODE_L, PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr) GPIO_INT(USB_C0_BC12_INT_ODL, PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(USB_C0_TCPC_INT_ODL, PIN(2, 3), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C0_PPC_INT_ODL, PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt) @@ -144,6 +140,10 @@ UNUSED(PIN(3, 2)) /* GPO32/TRIS_L */ UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */ UNUSED(PIN(6, 6)) /* GPIO66 */ UNUSED(PIN(5, 7)) /* GPIO57/SER_IRQ/ESPI_ALERT_L */ +UNUSED(PIN(9, 5)) /* GPIO95/SPIP_MISO */ +UNUSED(PIN(5, 6)) /* GPIO56/CLKRUN# */ +UNUSED(PIN(9, 3)) /* GPIO93/TA1/F_DIO2 */ +UNUSED(PIN(9, 7)) /* GPIO97 */ /* Pre-configured PSL balls: J8 K6 */ diff --git a/board/taniks/keyboard.c b/board/taniks/keyboard.c index 9cecf57f51..99099b4661 100644 --- a/board/taniks/keyboard.c +++ b/board/taniks/keyboard.c @@ -58,7 +58,6 @@ struct rgbkbd rgbkbds[] = { .col_len = RGB_GRID0_COL, .row_len = RGB_GRID0_ROW, }, - .init = &rgbkbd_default, .buf = grid0, }, }; diff --git a/board/taniks/sensors.c b/board/taniks/sensors.c index 8212a07069..d480849036 100644 --- a/board/taniks/sensors.c +++ b/board/taniks/sensors.c @@ -337,38 +337,8 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor, static void baseboard_sensors_init(void) { CPRINTS("baseboard_sensors_init"); - /* b/194765820 - * Dynamic motion sensor count - * All board supports tablet mode if board id > 0 - */ - if (ec_cfg_has_tabletmode()) { - /* - * GPIO_EC_ACCEL_INT_R_L - * The interrupt of lid accel is disabled by default. - * We'll enable it later if lid accel is LIS2DW12. - */ - /* Change Request (b/199529373) - * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C - * LSM6DSOETR3TR base accel/gyro if board id = 0 - * LSM6DS3TR-C Base accel/gyro if board id > 0 - */ - if (get_board_id() > 0) { - motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel; - motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro; - } - - /* Enable gpio interrupt for base accelgyro sensor */ - gpio_enable_interrupt(GPIO_EC_IMU_INT_R_L); - } else { - CPRINTS("Clamshell"); - motion_sensor_count = 0; - gmr_tablet_switch_disable(); - gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_DOWN); - /* Gyro is not present, don't allow line to float */ - gpio_set_flags(GPIO_EC_IMU_INT_R_L, GPIO_INPUT | - GPIO_PULL_DOWN); - } + CPRINTS("Clamshell"); } DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); diff --git a/builtin/assert.h b/builtin/assert.h index fb87f844ce..010198fd1b 100644 --- a/builtin/assert.h +++ b/builtin/assert.h @@ -21,7 +21,7 @@ extern "C" { #ifdef CONFIG_DEBUG_ASSERT_REBOOTS #ifdef CONFIG_DEBUG_ASSERT_BRIEF -extern noreturn void panic_assert_fail(const char *fname, int linenum); +noreturn void panic_assert_fail(const char *fname, int linenum); #define ASSERT(cond) \ do { \ if (!(cond)) \ @@ -30,8 +30,8 @@ extern noreturn void panic_assert_fail(const char *fname, int linenum); #else /* !CONFIG_DEBUG_ASSERT_BRIEF */ -extern noreturn void panic_assert_fail(const char *msg, const char *func, - const char *fname, int linenum); +noreturn void panic_assert_fail(const char *msg, const char *func, + const char *fname, int linenum); #define ASSERT(cond) \ do { \ if (!(cond)) \ diff --git a/builtin/sys/types.h b/builtin/sys/types.h new file mode 100644 index 0000000000..3f8de955e0 --- /dev/null +++ b/builtin/sys/types.h @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_SYS_TYPES_H__ +#define __CROS_EC_SYS_TYPES_H__ + +/* Data type for POSIX style clock() implementation */ +typedef long clock_t; + +#endif /* __CROS_EC_SYS_TYPES_H__ */ diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index d06aa8d204..0bbfe89b59 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -6,6 +6,8 @@ #ifndef __CROS_EC_CONFIG_CHIP_IT8XXX2_H #define __CROS_EC_CONFIG_CHIP_IT8XXX2_H +#define __RAM_CODE_ILM0_SECTION_NAME ".ram_code_ilm0" + /* CPU core BFD configuration */ #include "core/riscv-rv32i/config_core.h" @@ -85,6 +87,13 @@ || defined(CHIP_VARIANT_IT81302BX_512) \ || defined(CHIP_VARIANT_IT81202BX_1024) +/* + * Workaround mul instruction bug, see: + * https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf + */ +#undef CONFIG_RISCV_EXTENSION_M +#define CONFIG_IT8XXX2_MUL_WORKAROUND + #if defined(CHIP_VARIANT_IT81302BX_512) #define CONFIG_FLASH_SIZE_BYTES 0x00080000 #define CONFIG_RAM_BASE 0x80080000 diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk index e0f5636b2e..ea1ea6c330 100644 --- a/chip/max32660/build.mk +++ b/chip/max32660/build.mk @@ -9,7 +9,7 @@ # MAX32660 SoC has a Cortex-M4F ARM core CORE:=cortex-m # Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +CFLAGS_CPU+=-mcpu=cortex-m4 # Required chip modules chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o @@ -18,4 +18,3 @@ chip-$(CONFIG_I2C)+=i2c_chip.o # Optional chip modules chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o chip-$(CONFIG_WATCHDOG)+=wdt_chip.o - diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk index 6dec772ce3..1e3de24d06 100644 --- a/chip/mchp/build.mk +++ b/chip/mchp/build.mk @@ -15,7 +15,7 @@ endif # MCHP MEC SoC's have a Cortex-M4 ARM core CORE:=cortex-m # Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +CFLAGS_CPU+=-mcpu=cortex-m4 # JTAG debug with Keil ARM MDK debugger # do not allow GCC dwarf debug extensions diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk index a17a2cad5f..7dadf60c88 100644 --- a/chip/mec1322/build.mk +++ b/chip/mec1322/build.mk @@ -9,7 +9,7 @@ # MEC1322 SoC has a Cortex-M4 ARM core CORE:=cortex-m # Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +CFLAGS_CPU+=-mcpu=cortex-m4 ifeq ($(CONFIG_LTO),y) # Re-include the core's build.mk file so we can remove the lto flag. diff --git a/chip/mt_scp/mt818x/build.mk b/chip/mt_scp/mt818x/build.mk index bf450fb135..e9f77a2833 100644 --- a/chip/mt_scp/mt818x/build.mk +++ b/chip/mt_scp/mt818x/build.mk @@ -4,7 +4,7 @@ # found in the LICENSE file. CORE:=cortex-m -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +CFLAGS_CPU+=-mcpu=cortex-m4 # Required chip modules chip-y+=mt818x/clock_$(CHIP_VARIANT).o diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk index c81bd83595..e61cdafb01 100644 --- a/chip/mt_scp/mt8192/build.mk +++ b/chip/mt_scp/mt8192/build.mk @@ -7,4 +7,3 @@ chip-y+=$(CHIP_VARIANT)/uart.o chip-y+=$(CHIP_VARIANT)/clock.o chip-y+=$(CHIP_VARIANT)/video.o - diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk index c81bd83595..e61cdafb01 100644 --- a/chip/mt_scp/mt8195/build.mk +++ b/chip/mt_scp/mt8195/build.mk @@ -7,4 +7,3 @@ chip-y+=$(CHIP_VARIANT)/uart.o chip-y+=$(CHIP_VARIANT)/clock.o chip-y+=$(CHIP_VARIANT)/video.o - diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index 1fe524763b..d7e61de4de 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -9,7 +9,7 @@ # NPCX SoC has a Cortex-M4F ARM core CORE:=cortex-m # Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +CFLAGS_CPU+=-mcpu=cortex-m4 # Disable overlapping section warning that linker emits due to NPCX_RO_HEADER. LDFLAGS_EXTRA+=-Wl,--no-check-sections diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk index 13a6aa752a..0d47a0131a 100644 --- a/chip/stm32/build.mk +++ b/chip/stm32/build.mk @@ -9,33 +9,28 @@ ifeq ($(CHIP_FAMILY),stm32f0) # STM32F0xx sub-family has a Cortex-M0 ARM core CORE:=cortex-m0 -# Force ARMv6-M ISA used by the Cortex-M0 -# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M -# without "svc" instruction, but that was short-lived. ARMv6S-M was the option -# with "svc". GCC kept that naming scheme even though the distinction is long -# gone. -CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0 +CFLAGS_CPU+=-mcpu=cortex-m0 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \ stm32g4)) # STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core CORE:=cortex-m # Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +CFLAGS_CPU+=-mcpu=cortex-m4 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7)) # STM32FH7xx family has a Cortex-M7 ARM core CORE:=cortex-m -# Allow the full Cortex-M4 instruction set (identical to M7) -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +# Allow the full Cortex-M7 instruction set. +CFLAGS_CPU+=-mcpu=cortex-m7 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5)) # STM32FL5xx family has a Cortex-M33 ARM core CORE:=cortex-m # Allow the full Cortex-M33 instruction set -CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33 +CFLAGS_CPU+=-mcpu=cortex-m33 else # other STM32 SoCs have a Cortex-M3 ARM core CORE:=cortex-m # Force Cortex-M3 subset of instructions -CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3 +CFLAGS_CPU+=-mcpu=cortex-m3 endif # Select between 16-bit and 32-bit timer for clock source diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c index 17bb5d8e32..e34afde7e1 100644 --- a/chip/stm32/spi_controller.c +++ b/chip/stm32/spi_controller.c @@ -334,6 +334,8 @@ static int spi_dma_wait(int port) return rv; } +static uint8_t spi_chip_select_already_asserted[ARRAY_SIZE(SPI_REGS)]; + int spi_transaction_async(const struct spi_device_t *spi_device, const uint8_t *txdata, int txlen, uint8_t *rxdata, int rxlen) @@ -360,6 +362,11 @@ int spi_transaction_async(const struct spi_device_t *spi_device, } #endif + if (IS_ENABLED(CONFIG_USB_SPI)) { + spi_chip_select_already_asserted[port] = + !gpio_get_level(spi_device->gpio_cs); + } + /* Drive SS low */ gpio_set_level(spi_device->gpio_cs, 0); @@ -403,8 +410,11 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) { int rv = spi_dma_wait(spi_device->port); - /* Drive SS high */ - gpio_set_level(spi_device->gpio_cs, 1); + if (!IS_ENABLED(CONFIG_USB_SPI) + || !spi_chip_select_already_asserted[spi_device->port]) { + /* Drive SS high */ + gpio_set_level(spi_device->gpio_cs, 1); + } return rv; } diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c index 86254ddaac..e80d15b6cd 100644 --- a/chip/stm32/usb_spi.c +++ b/chip/stm32/usb_spi.c @@ -4,6 +4,7 @@ */ #include "common.h" +#include "gpio.h" #include "link_defs.h" #include "registers.h" #include "spi.h" @@ -178,6 +179,15 @@ static void create_spi_config_response(struct usb_spi_config const *config, sizeof(struct usb_spi_response_configuration_v2); } +static void create_spi_chip_select_response(struct usb_spi_config const *config, + struct usb_spi_packet_ctx *packet) +{ + /* Construct the response packet. */ + packet->rsp_cs.packet_id = USB_SPI_PKT_ID_RSP_CHIP_SELECT; + packet->rsp_cs.status_code = 0; + packet->packet_size = sizeof(packet->rsp_cs); +} + /* * If we have a transfer response in progress, this will construct the * next entry. If no transfer is in progress or if we are unable to @@ -334,6 +344,24 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, break; } + case USB_SPI_PKT_ID_CMD_CHIP_SELECT: + { + /* + * The host is requesting the chip select line be + * asserted or deasserted. + */ + uint16_t flags = packet->cmd_cs.flags; + + if (flags & USB_SPI_CHIP_SELECT) { + /* Set chip select low (asserted). */ + gpio_set_level(SPI_FLASH_DEVICE->gpio_cs, 0); + } else { + /* Set chip select high (adesserted). */ + gpio_set_level(SPI_FLASH_DEVICE->gpio_cs, 1); + } + config->state->mode = USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE; + break; + } default: { /* An unknown USB packet was delivered. */ @@ -388,6 +416,13 @@ void usb_spi_deferred(struct usb_spi_config const *config) config->state->mode = USB_SPI_MODE_IDLE; return; } + /* Need to send response to USB SPI chip select. */ + if (config->state->mode == USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE) { + create_spi_chip_select_response(config, transmit_packet); + usb_spi_write_packet(config, transmit_packet); + config->state->mode = USB_SPI_MODE_IDLE; + return; + } /* Start a new SPI transfer. */ if (config->state->mode == USB_SPI_MODE_START_SPI) { diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h index a1be2c11fb..fa86ba3651 100644 --- a/chip/stm32/usb_spi.h +++ b/chip/stm32/usb_spi.h @@ -232,6 +232,30 @@ * * packet id: 2 byte enum USB_SPI_PKT_ID_CMD_RESTART_RESPONSE * + * Command chip select Packet (Host to Device): + * + * +----------------+-------------+ + * | packet id : 2B | action : 2B | + * +----------------+-------------+ + * + * packet id: 2 byte enum USB_SPI_PKT_ID_CMD_CHIP_SELECT + * + * action: 2 byte, current options: + * 0: Deassert chip select + * 1: Assert chip select + * + * Response chip select Packet (Device to Host): + * + * +----------------+------------------+ + * | packet id : 2B | status code : 2B | + * +----------------+------------------+ + * + * packet id: 2 byte enum USB_SPI_PKT_ID_RSP_CHIP_SELECT + * + * status code: 2 byte status code + * 0x0000: Success + * others: Error + * * USB Error Codes: * * send_command return codes have the following format: @@ -280,6 +304,12 @@ enum packet_id_type { USB_SPI_PKT_ID_RSP_TRANSFER_START = 5, /* Additional packets containing read payload. */ USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6, + /* + * Request assertion or deassertion of chip select + */ + USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7, + /* Response to above request. */ + USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8, }; enum feature_bitmap { @@ -314,6 +344,21 @@ struct usb_spi_continue_v2 { uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_CONTINUE]; } __packed; +enum chip_select_flags { + /* Indicates chip select should be asserted. */ + USB_SPI_CHIP_SELECT = BIT(0) +}; + +struct usb_spi_chip_select_command { + uint16_t packet_id; + uint16_t flags; +} __packed; + +struct usb_spi_chip_select_response { + uint16_t packet_id; + uint16_t status_code; +} __packed; + struct usb_spi_packet_ctx { union { uint8_t bytes[USB_MAX_PACKET_SIZE]; @@ -323,6 +368,8 @@ struct usb_spi_packet_ctx { struct usb_spi_response_configuration_v2 rsp_config; struct usb_spi_response_v2 rsp_start; struct usb_spi_continue_v2 rsp_continue; + struct usb_spi_chip_select_command cmd_cs; + struct usb_spi_chip_select_response rsp_cs; } __packed; /* * By storing the number of bytes in the header and knowing that the @@ -392,6 +439,8 @@ enum usb_spi_mode { USB_SPI_MODE_IDLE = 0, /* Indicates the device needs to send it's USB SPI configuration.*/ USB_SPI_MODE_SEND_CONFIGURATION, + /* Indicates the device needs to respond to chip select. */ + USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE, /* Indicates we device needs start the SPI transfer. */ USB_SPI_MODE_START_SPI, /* Indicates we should start a transfer response. */ diff --git a/common/cbi.c b/common/cbi.c index 217dffd6f4..e18f15e5a9 100644 --- a/common/cbi.c +++ b/common/cbi.c @@ -5,6 +5,7 @@ * Cros Board Info */ +#include "chipset.h" #include "common.h" #include "console.h" #include "crc8.h" @@ -546,7 +547,7 @@ DECLARE_CONSOLE_COMMAND(cbi, cc_cbi, "[set <tag> <value> <size> | " "Print or change Cros Board Info from flash"); #endif /* CONFIG_CMD_CBI */ -#ifndef HAS_TASK_CHIPSET +#ifndef CONFIG_AP_POWER_CONTROL int cbi_set_fw_config(uint32_t fw_config) { /* Check write protect status */ diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c index 25d416a8e2..12904c0b39 100644 --- a/common/fpsensor/fpsensor.c +++ b/common/fpsensor/fpsensor.c @@ -338,7 +338,7 @@ static enum ec_status fp_command_passthru(struct host_cmd_handler_args *args) const struct ec_params_fp_passthru *params = args->params; void *out = args->response; int rc; - int ret = EC_RES_SUCCESS; + enum ec_status ret = EC_RES_SUCCESS; if (system_is_locked()) return EC_RES_ACCESS_DENIED; @@ -754,7 +754,7 @@ static enum ec_error_list fp_console_action(uint32_t mode) while (tries--) { if (!(sensor_mode & FP_MODE_ANY_CAPTURE)) { CPRINTS("done (events:%x)", (int)fp_events); - return 0; + return EC_SUCCESS; } usleep(100 * MSEC); } diff --git a/common/host_command.c b/common/host_command.c index 0edd188984..e05475ce48 100644 --- a/common/host_command.c +++ b/common/host_command.c @@ -660,11 +660,11 @@ static void host_command_debug_request(struct host_cmd_handler_args *args) } if (hcdebug >= HCDEBUG_PARAMS && args->params_size) - CPRINTS("HC 0x%02x.%d:%ph", args->command, + CPRINTS("HC 0x%04x.%d:%ph", args->command, args->version, HEX_BUF(args->params, args->params_size)); else - CPRINTS("HC 0x%02x", args->command); + CPRINTS("HC 0x%04x", args->command); } uint16_t host_command_process(struct host_cmd_handler_args *args) @@ -717,7 +717,7 @@ uint16_t host_command_process(struct host_cmd_handler_args *args) } if (rv != EC_RES_SUCCESS) - CPRINTS("HC 0x%02x err %d", args->command, rv); + CPRINTS("HC 0x%04x err %d", args->command, rv); if (hcdebug >= HCDEBUG_PARAMS && args->response_size) CPRINTS("HC resp:%ph", diff --git a/common/host_command_controller.c b/common/host_command_controller.c index befa1865a6..eb35622ab3 100644 --- a/common/host_command_controller.c +++ b/common/host_command_controller.c @@ -119,7 +119,7 @@ static int pd_host_command_internal(int command, int version, /* Check for host command error code */ ret = resp_buf[0]; if (ret) { - CPRINTS("command 0x%02x returned error %d", command, ret); + CPRINTS("command 0x%04x returned error %d", command, ret); return -ret; } @@ -154,7 +154,7 @@ static int pd_host_command_internal(int command, int version, if ((uint8_t)sum) { - CPRINTS("command 0x%02x bad checksum returned: %d", + CPRINTS("command 0x%04x bad checksum returned: %d", command, sum); return -EC_RES_INVALID_CHECKSUM; } diff --git a/common/host_event_commands.c b/common/host_event_commands.c index 6fa1227272..177e7cb877 100644 --- a/common/host_event_commands.c +++ b/common/host_event_commands.c @@ -5,6 +5,7 @@ /* Host event commands for Chrome EC */ +#include "chipset.h" #include "common.h" #include "console.h" #include "hooks.h" diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c index da09edc91c..755b26f360 100644 --- a/common/keyboard_8042.c +++ b/common/keyboard_8042.c @@ -5,8 +5,8 @@ * 8042 keyboard protocol */ -#include "chipset.h" #include "button.h" +#include "chipset.h" #include "common.h" #include "console.h" #include "device_event.h" diff --git a/common/keyboard_backlight.c b/common/keyboard_backlight.c index 8cf400dc34..62da361d73 100644 --- a/common/keyboard_backlight.c +++ b/common/keyboard_backlight.c @@ -3,6 +3,7 @@ * found in the LICENSE file. */ +#include "chipset.h" #include "console.h" #include "ec_commands.h" #include "gpio.h" @@ -113,9 +114,15 @@ static void keyboard_backlight_init(void) /* Don't leave kblight enable state undetermined */ kblight_enable(0); } +#ifdef HAS_TASK_CHIPSET +/* We're running on a system EC. Initialize kblight once per AP start-up. */ +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, keyboard_backlight_init, HOOK_PRIO_DEFAULT); +#else +/* We're running on a KBMCU thus powered when AP starts. Do init on reset. */ DECLARE_HOOK(HOOK_INIT, keyboard_backlight_init, HOOK_PRIO_DEFAULT); +#endif -#ifdef HAS_TASK_CHIPSET +#ifdef CONFIG_AP_POWER_CONTROL static void kblight_suspend(void) { kblight_enable(0); @@ -130,7 +137,7 @@ static void kblight_resume(void) } } DECLARE_HOOK(HOOK_CHIPSET_RESUME, kblight_resume, HOOK_PRIO_DEFAULT); -#endif // HAS_TASK_CHIPSET +#endif /* CONFIG_AP_POWER_CONTROL */ #ifdef CONFIG_LID_SWITCH static void kblight_lid_change(void) diff --git a/common/led_policy_std.c b/common/led_policy_std.c index b18dc1bc27..65bf8cedbd 100644 --- a/common/led_policy_std.c +++ b/common/led_policy_std.c @@ -124,7 +124,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) return EC_SUCCESS; } -#ifdef HAS_TASK_CHIPSET +#ifdef CONFIG_AP_POWER_CONTROL static void std_led_shutdown(void) { pwr_led_set_color(LED_OFF); diff --git a/common/mkbp_info.c b/common/mkbp_info.c index b3835367cf..52d26f407b 100644 --- a/common/mkbp_info.c +++ b/common/mkbp_info.c @@ -12,16 +12,26 @@ #include "keyboard_config.h" #include "keyboard_mkbp.h" #include "keyboard_scan.h" +#include "mkbp_info.h" #include "mkbp_input_devices.h" #include "util.h" +__overridable int mkbp_support_volume_buttons(void) +{ +#ifdef CONFIG_VOLUME_BUTTONS + return 1; +#else + return 0; +#endif +} + static uint32_t get_supported_buttons(void) { uint32_t val = 0; -#ifdef CONFIG_VOLUME_BUTTONS - val |= BIT(EC_MKBP_VOL_UP) | BIT(EC_MKBP_VOL_DOWN); -#endif /* defined(CONFIG_VOLUME_BUTTONS) */ + if (mkbp_support_volume_buttons()) { + val |= BIT(EC_MKBP_VOL_UP) | BIT(EC_MKBP_VOL_DOWN); + } #ifdef CONFIG_DEDICATED_RECOVERY_BUTTON val |= BIT(EC_MKBP_RECOVERY); diff --git a/common/rgb_keyboard.c b/common/rgb_keyboard.c index e77939ff9e..815e4a3435 100644 --- a/common/rgb_keyboard.c +++ b/common/rgb_keyboard.c @@ -23,15 +23,14 @@ #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "RGBKBD: " fmt, ##args) #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args) -test_export_static enum rgbkbd_demo demo = +test_export_static enum ec_rgbkbd_demo demo = #if defined(CONFIG_RGBKBD_DEMO_FLOW) - RGBKBD_DEMO_FLOW + EC_RGBKBD_DEMO_FLOW; #elif defined(CONFIG_RGBKBD_DEMO_DOT) - RGBKBD_DEMO_DOT + EC_RGBKBD_DEMO_DOT; #else - RGBKBD_DEMO_OFF + EC_RGBKBD_DEMO_OFF; #endif - ; const int default_demo_interval_ms = 250; test_export_static int demo_interval_ms = -1; @@ -41,31 +40,48 @@ uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT]; static enum rgbkbd_state rgbkbd_state; -const struct rgbkbd_init rgbkbd_default = { +const struct rgbkbd_init rgbkbd_init_default = { .gcc = RGBKBD_MAX_GCC_LEVEL / 2, - .scale = RGBKBD_MAX_SCALE, + .scale = { RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE }, .color = { .r = 0xff, .g = 0xff, .b = 0xff }, /* white */ }; +const struct rgbkbd_init *rgbkbd_init_setting = &rgbkbd_init_default; + +void rgbkbd_register_init_setting(const struct rgbkbd_init *setting) +{ + rgbkbd_init_setting = setting; +} + +/* Search the grid where x belongs to. */ +static struct rgbkbd *find_grid_from_x(int x, uint8_t *col) +{ + struct rgbkbd *ctx = NULL; + uint8_t grid; + + *col = 0; + for (grid = 0; grid < rgbkbd_count; grid++) { + ctx = &rgbkbds[grid]; + if (x < *col + ctx->cfg->col_len) + break; + *col += ctx->cfg->col_len; + } + + return ctx; +} + static int set_color_single(struct rgb_s color, int x, int y) { struct rgbkbd *ctx = &rgbkbds[0]; - uint8_t grid; - uint8_t col = 0; - uint8_t offset; + uint8_t grid, col, offset; int rv; if (rgbkbd_hsize <= x || rgbkbd_vsize <= y) { return EC_ERROR_OVERFLOW; } - /* Search the grid where x belongs to. */ - for (grid = 0; grid < rgbkbd_count; grid++, ctx++) { - if (x < col + ctx->cfg->col_len) - break; - col += ctx->cfg->col_len; - } - + ctx = find_grid_from_x(x, &col); + grid = RGBKBD_CTX_TO_GRID(ctx); offset = ctx->cfg->row_len * (x - col) + y; ctx->buf[offset] = color; @@ -183,16 +199,16 @@ static void rgbkbd_demo_dot(void) #endif } -static void rgbkbd_demo_run(enum rgbkbd_demo id) +static void rgbkbd_demo_run(enum ec_rgbkbd_demo id) { switch (id) { - case RGBKBD_DEMO_FLOW: + case EC_RGBKBD_DEMO_FLOW: rgbkbd_demo_flow(); break; - case RGBKBD_DEMO_DOT: + case EC_RGBKBD_DEMO_DOT: rgbkbd_demo_dot(); break; - case RGBKBD_DEMO_OFF: + case EC_RGBKBD_DEMO_OFF: default: break; } @@ -264,7 +280,7 @@ static int rgbkbd_set_global_brightness(uint8_t gcc) return rv; } -static int rgbkbd_set_scale(uint8_t scale) +static int rgbkbd_reset_scale(struct rgb_s scale) { int e, i, rv = EC_SUCCESS; @@ -273,8 +289,8 @@ static int rgbkbd_set_scale(uint8_t scale) e = ctx->cfg->drv->set_scale(ctx, 0, scale, get_grid_size(ctx)); if (e) { - CPRINTS("Failed to set scale of GRID%d to %d (%d)", - i, scale, e); + CPRINTS("Failed to set scale to [%d,%d,%d] Grid%d (%d)", + scale.r, scale.g, scale.b, i, e); rv = e; } } @@ -282,6 +298,46 @@ static int rgbkbd_set_scale(uint8_t scale) return rv; } +static int rgbkbd_set_scale(struct rgb_s scale, uint8_t key) +{ + struct rgbkbd *ctx; + uint8_t j, col, grid, offset; + union rgbkbd_coord_u8 led; + int rv = EC_SUCCESS; + + j = rgbkbd_table[key]; + if (j == RGBKBD_NONE) + return rv; + + do { + led.u8 = rgbkbd_map[j++]; + if (led.u8 == RGBKBD_DELM) + /* Reached end of the group. */ + break; + ctx = find_grid_from_x(led.coord.x, &col); + grid = RGBKBD_CTX_TO_GRID(ctx); + /* + * offset is the relative position in our buffer where LED + * colors are cached. RGB is grouped as one. Note this differs + * from the external buffer (LED drivers' buffer) where RGB is + * individually counted. + * + * offset can be calculated by multiplying the horizontal + * position (x) by the size of the rows, then, adding the + * vertical position (y). + */ + offset = ctx->cfg->row_len * (led.coord.x - col) + led.coord.y; + rv = ctx->cfg->drv->set_scale(ctx, offset, scale, 1); + if (rv) { + CPRINTS("Failed to set scale to [%d,%d,%d] Grid%d (%d)", + scale.r, scale.g, scale.b, grid, rv); + return rv; + } + } while (led.u8 != RGBKBD_DELM); + + return rv; +} + static int rgbkbd_init(void) { int rv = EC_SUCCESS; @@ -289,8 +345,7 @@ static int rgbkbd_init(void) for (i = 0; i < rgbkbd_count; i++) { struct rgbkbd *ctx = &rgbkbds[i]; - uint8_t scale = ctx->init->scale; - uint8_t gcc = ctx->init->gcc; + uint8_t gcc = rgbkbd_init_setting->gcc; e = ctx->cfg->drv->init(ctx); if (e) { @@ -299,14 +354,6 @@ static int rgbkbd_init(void) continue; } - e = ctx->cfg->drv->set_scale(ctx, 0, scale, get_grid_size(ctx)); - if (e) { - CPRINTS("Failed to set scale of GRID%d to %d (%d)", - i, scale, rv); - rv = e; - continue; - } - e = ctx->cfg->drv->set_gcc(ctx, gcc); if (e) { CPRINTS("Failed to set GCC to %u for grid=%d (%d)", @@ -315,11 +362,12 @@ static int rgbkbd_init(void) continue; } - rgbkbd_reset_color(ctx->init->color); - CPRINTS("Initialized GRID%d", i); } + rv |= rgbkbd_reset_scale(rgbkbd_init_setting->scale); + rgbkbd_reset_color(rgbkbd_init_setting->color); + if (rv == EC_SUCCESS) rgbkbd_state = RGBKBD_STATE_INITIALIZED; @@ -383,7 +431,7 @@ static int rgbkbd_enable(int enable) return rv; } -static void rgbkbd_demo_set(enum rgbkbd_demo new_demo) +static void rgbkbd_demo_set(enum ec_rgbkbd_demo new_demo) { CPRINTS("Setting demo %d with %d ms interval", demo, demo_interval_ms); @@ -394,7 +442,7 @@ static void rgbkbd_demo_set(enum rgbkbd_demo new_demo) rgbkbd_init(); rgbkbd_enable(1); - if (demo == RGBKBD_DEMO_OFF) + if (demo == EC_RGBKBD_DEMO_OFF) return; demo_interval_ms = default_demo_interval_ms; @@ -484,7 +532,7 @@ DECLARE_HOST_COMMAND(EC_CMD_RGBKBD_SET_COLOR, hc_rgbkbd_set_color, static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) { const struct ec_params_rgbkbd *p = args->params; - enum ec_status rv = EC_RES_ERROR; + enum ec_status rv = EC_RES_SUCCESS; if (rgbkbd_late_init()) return EC_RES_ERROR; @@ -492,7 +540,15 @@ static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) switch (p->subcmd) { case EC_RGBKBD_SUBCMD_CLEAR: rgbkbd_reset_color(p->color); - rv = EC_RES_SUCCESS; + break; + case EC_RGBKBD_SUBCMD_DEMO: + if (p->demo >= EC_RGBKBD_DEMO_COUNT) + return EC_RES_INVALID_PARAM; + rgbkbd_demo_set(p->demo); + break; + case EC_RGBKBD_SUBCMD_SET_SCALE: + if (rgbkbd_set_scale(p->set_scale.scale, p->set_scale.key)) + rv = EC_RES_ERROR; break; default: rv = EC_RES_INVALID_PARAM; @@ -503,10 +559,26 @@ static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) } DECLARE_HOST_COMMAND(EC_CMD_RGBKBD, hc_rgbkbd, EC_VER_MASK(0)); +static int int_to_rgb(const char *code, struct rgb_s *rgb) +{ + int val; + char *end; + + val = strtoi(code, &end, 0); + if (*end || val > EC_RGBKBD_MAX_RGB_COLOR) + return EC_ERROR_INVAL; + + rgb->r = (val >> 16) & 0xff; + rgb->g = (val >> 8) & 0xff; + rgb->b = (val >> 0) & 0xff; + + return EC_SUCCESS; +} + test_export_static int cc_rgb(int argc, char **argv) { char *end, *comma; - struct rgb_s color; + struct rgb_s rgb, scale; int gcc, x, y, val; int i, rv = EC_SUCCESS; @@ -525,39 +597,68 @@ test_export_static int cc_rgb(int argc, char **argv) y = strtoi(comma + 1, &end, 0); if (*end || y >= rgbkbd_vsize) return EC_ERROR_PARAM1; + + rv = int_to_rgb(argv[2], &rgb); + if (rv) + return EC_ERROR_PARAM2; + + rgbkbd_demo_set(EC_RGBKBD_DEMO_OFF); + + if (y < 0) { + /* Set all LEDs on column x. */ + ccprintf("Set column %d to 0x%02x%02x%02x\n", + x, rgb.r, rgb.g, rgb.b); + for (i = 0; i < rgbkbd_vsize; i++) + rv = set_color_single(rgb, x, i); + } else if (x < 0) { + /* Set all LEDs on row y. */ + ccprintf("Set row %d to 0x%02x%02x%02x\n", + y, rgb.r, rgb.g, rgb.b); + for (i = 0; i < rgbkbd_hsize; i++) + rv = set_color_single(rgb, i, y); + } else { + ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n", + x, y, rgb.r, rgb.g, rgb.b); + rv = set_color_single(rgb, x, y); + } } else if (!strcasecmp(argv[1], "all")) { /* Usage 3 */ - x = -1; - y = -1; + rv = int_to_rgb(argv[2], &rgb); + if (rv) + return EC_ERROR_PARAM2; + + rgbkbd_demo_set(EC_RGBKBD_DEMO_OFF); + rgbkbd_reset_color(rgb); } else if (!strcasecmp(argv[1], "demo")) { /* Usage 4 */ val = strtoi(argv[2], &end, 0); - if (*end || val >= RGBKBD_DEMO_COUNT) + if (*end || val >= EC_RGBKBD_DEMO_COUNT) return EC_ERROR_PARAM1; rgbkbd_demo_set(val); - return EC_SUCCESS; } else if (!strcasecmp(argv[1], "reset")) { + /* Usage 5: Reset */ rgbkbd_reset(); rv = rgbkbd_init(); if (rv) return rv; - return rgbkbd_enable(0); + rv = rgbkbd_enable(0); } else if (!strcasecmp(argv[1], "enable")) { - return rgbkbd_enable(1); + /* Usage 5: Enable */ + rv = rgbkbd_enable(1); } else if (!strcasecmp(argv[1], "disable")) { - return rgbkbd_enable(0); + /* Usage 5: Disable */ + rv = rgbkbd_enable(0); } else if (!strcasecmp(argv[1], "scale")) { /* Usage 6 */ - val = strtoi(argv[2], &end, 0); - if (*end || val > RGBKBD_MAX_SCALE) + rv = int_to_rgb(argv[2], &scale); + if (rv) return EC_ERROR_PARAM2; - return rgbkbd_set_scale(val); + rv = rgbkbd_reset_scale(scale); } else if (!strcasecmp(argv[1], "red")) { - color.r = 255; - color.g = 0; - color.b = 0; - rgbkbd_reset_color(color); - return EC_SUCCESS; + rgb.r = 255; + rgb.g = 0; + rgb.b = 0; + rgbkbd_reset_color(rgb); } else { /* Usage 1 */ if (argc != 2) @@ -565,46 +666,7 @@ test_export_static int cc_rgb(int argc, char **argv) gcc = strtoi(argv[1], &end, 0); if (*end || gcc < 0 || gcc > UINT8_MAX) return EC_ERROR_PARAM1; - return rgbkbd_set_global_brightness(gcc); - } - - if (argc != 5) - return EC_ERROR_PARAM_COUNT; - - val = strtoi(argv[2], &end, 0); - if (*end || val < 0 || val > UINT8_MAX) - return EC_ERROR_PARAM2; - color.r = val; - val = strtoi(argv[3], &end, 0); - if (*end || val < 0 || val > UINT8_MAX) - return EC_ERROR_PARAM3; - color.g = val; - val = strtoi(argv[4], &end, 0); - if (*end || val < 0 || val > UINT8_MAX) - return EC_ERROR_PARAM4; - color.b = val; - - rgbkbd_demo_set(RGBKBD_DEMO_OFF); - if (y < 0 && x < 0) { - /* Usage 3 */ - rgbkbd_reset_color(color); - } else if (y < 0) { - /* Usage 2: Set all LEDs on column x. */ - ccprintf("Set column %d to 0x%02x%02x%02x\n", - x, color.r, color.g, color.b); - for (i = 0; i < rgbkbd_vsize; i++) - rv = set_color_single(color, x, i); - } else if (x < 0) { - /* Usage 2: Set all LEDs on row y. */ - ccprintf("Set row %d to 0x%02x%02x%02x\n", - y, color.r, color.g, color.b); - for (i = 0; i < rgbkbd_hsize; i++) - rv = set_color_single(color, i, y); - } else { - /* Usage 2 */ - ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n", - x, y, color.r, color.g, color.b); - rv = set_color_single(color, x, y); + rv = rgbkbd_set_global_brightness(gcc); } return rv; @@ -612,12 +674,12 @@ test_export_static int cc_rgb(int argc, char **argv) #ifndef TEST_BUILD DECLARE_CONSOLE_COMMAND(rgb, cc_rgb, "\n" - "1. rgbk <global-brightness>\n" - "2. rgbk <col,row> <r-bright> <g-bright> <b-bright>\n" - "3. rgbk all <r-bright> <g-bright> <b-bright>\n" - "4. rgbk demo <id>\n" - "5. rgbk reset/enable/disable/red\n" - "6. rgbk scale <val>\n", - "Set color of RGB keyboard" + "1. rgb <global-brightness>\n" + "2. rgb <col,row> <24-bit RGB code>\n" + "3. rgb all <24-bit RGB code>\n" + "4. rgb demo <id>\n" + "5. rgb reset/enable/disable/red\n" + "6. rgb scale <24-bit RGB scale>\n", + "Control RGB keyboard" ); #endif diff --git a/common/system.c b/common/system.c index 9b0e6f25a0..013452c21a 100644 --- a/common/system.c +++ b/common/system.c @@ -12,7 +12,6 @@ #include "console.h" #include "cpu.h" #include "cros_board_info.h" -#include "ec_version.h" #include "dma.h" #include "extpower.h" #include "flash.h" @@ -1056,13 +1055,12 @@ void system_enter_hibernate(uint32_t seconds, uint32_t microseconds) * On ChromeOS devices, if AC is present, don't hibernate. * It might trigger an immediate wake up (since AC is present), * resulting in an AP reboot. - * Hibernate when AC is present never occurs in normal circumstantces, + * Hibernate when AC is present never occurs in normal circumstances, * this is to prevent an action triggered by developers. * See: b/192259035 */ - if (IS_ENABLED(CONFIG_EXTPOWER) && - (IS_ENABLED(HAS_TASK_CHIPSET) || IS_ENABLED(CONFIG_AP_PWRSEQ)) && - extpower_is_present()) { + if (IS_ENABLED(CONFIG_EXTPOWER) && IS_ENABLED(CONFIG_AP_POWER_CONTROL) + && extpower_is_present()) { CPRINTS("AC on, skip hibernate"); return; } diff --git a/common/usb_pd_alt_mode_dfp.c b/common/usb_pd_alt_mode_dfp.c index feda92c74e..1de01f9c48 100644 --- a/common/usb_pd_alt_mode_dfp.c +++ b/common/usb_pd_alt_mode_dfp.c @@ -1174,7 +1174,7 @@ __overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps) * could cause a wake up.) When in S5->S3 transition state, we * should treat it as a SoC off state. */ -#if defined(HAS_TASK_CHIPSET) || defined(CONFIG_AP_PWRSEQ) +#ifdef CONFIG_AP_POWER_CONTROL if (!chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON)) return -1; #endif diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c index 5dc133cb45..3f0408eedf 100644 --- a/common/usb_pd_protocol.c +++ b/common/usb_pd_protocol.c @@ -2754,7 +2754,7 @@ static void pd_init_tasks(void) if (initialized) return; -#if defined(HAS_TASK_CHIPSET) && defined(CONFIG_USB_PD_DUAL_ROLE) +#if defined(CONFIG_AP_POWER_CONTROL) && defined(CONFIG_USB_PD_DUAL_ROLE) /* Set dual-role state based on chipset power state */ if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) for (i = 0; i < board_get_usb_pd_port_count(); i++) diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c index 745454b647..159331171e 100644 --- a/common/usbc/usb_pd_dpm.c +++ b/common/usbc/usb_pd_dpm.c @@ -278,7 +278,7 @@ static void dpm_attempt_mode_entry(int port) return; } -#if defined(HAS_TASK_CHIPSET) || defined(CONFIG_AP_PWRSEQ) +#ifdef CONFIG_AP_POWER_CONTROL /* * Do not try to enter mode while CPU is off. * CPU transitions (e.g b/158634281) can occur during the discovery @@ -887,7 +887,7 @@ static uint8_t get_status_power_state_change(void) { enum pd_sdb_power_state ret = PD_SDB_POWER_STATE_NOT_SUPPORTED; -#ifdef HAS_TASK_CHIPSET +#ifdef CONFIG_AP_POWER_CONTROL if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_HARD_OFF)) { ret = PD_SDB_POWER_STATE_G3; } else if (chipset_in_or_transitioning_to_state( @@ -906,7 +906,7 @@ static uint8_t get_status_power_state_change(void) CHIPSET_STATE_STANDBY)) { ret = PD_SDB_POWER_STATE_MODERN_STANDBY; } -#endif /* HAS_TASK_CHIPSET */ +#endif /* CONFIG_AP_POWER_CONTROL */ return ret | board_get_pd_sdb_power_indicator(ret); } diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c index 046461b7a8..2da6b59f0a 100644 --- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c +++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c @@ -547,7 +547,7 @@ int pd_get_rev(int port, enum tcpci_msg_type type) #endif /* !CONFIG_USB_PR_SM */ -#if !defined(HAS_TASK_CHIPSET) && !defined(CONFIG_AP_PWRSEQ) +#ifndef CONFIG_AP_POWER_CONTROL __overridable enum pd_dual_role_states board_tc_get_initial_drp_mode(int port) { /* @@ -1577,7 +1577,7 @@ void tc_state_init(int port) */ tc_policy_pd_enable(port, pd_comm_allowed_by_policy()); -#if defined(HAS_TASK_CHIPSET) || defined(CONFIG_AP_PWRSEQ) +#ifdef CONFIG_AP_POWER_CONTROL /* Set dual-role state based on chipset power state */ if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) pd_set_dual_role_and_event(port, PD_DRP_FORCE_SINK, 0); diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk index 489990ec7a..bcffe16e8d 100644 --- a/core/cortex-m/build.mk +++ b/core/cortex-m/build.mk @@ -6,13 +6,33 @@ # Cortex-M4 core OS files build # -# Use coreboot-sdk + +ifeq ($(cc-name),gcc) +# coreboot sdk +CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- +else +# llvm sdk +CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi- +endif + $(call set-option,CROSS_COMPILE,\ $(CROSS_COMPILE_arm),\ - /opt/coreboot-sdk/bin/arm-eabi-) + $(CROSS_COMPILE_ARM_DEFAULT)) # FPU compilation flags -CFLAGS_FPU-$(CONFIG_FPU)=-mfpu=fpv4-sp-d16 -mfloat-abi=hard +CFLAGS_FPU-$(CONFIG_FPU)=-mfloat-abi=hard +ifeq ($(cc-name),gcc) +# -mfpu=auto will choose correct hardware based on settings of -mcpu and -march +# https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html. +# +# According to the above doc "-mfpu=auto" is the default and shouldn't be +# required, but compilation using gcc fails without the flag. +# +# clang does not support "-mfpu=auto" flag, but will choose the correct floating +# point unit based on the -mcpu flag: +# https://lists.llvm.org/pipermail/llvm-dev/2018-September/126468.html +CFLAGS_FPU-$(CONFIG_FPU)+=-mfpu=auto +endif # CPU specific compilation flags CFLAGS_CPU+=-mthumb diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S index bc650c4c64..9d4815ac79 100644 --- a/core/cortex-m/init.S +++ b/core/cortex-m/init.S @@ -117,19 +117,9 @@ _data_end: _data_lma_start: .long __data_lma_start -/* Mock functions to avoid linker complaints */ -.global __aeabi_unwind_cpp_pr0 -.global __aeabi_unwind_cpp_pr1 -.global __aeabi_unwind_cpp_pr2 -__aeabi_unwind_cpp_pr0: -__aeabi_unwind_cpp_pr1: -__aeabi_unwind_cpp_pr2: - bx lr - /* Reserve space for system stack */ .section .bss.system_stack stack_start: .space CONFIG_STACK_SIZE, 0 stack_end: .global stack_end - diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S index f56c5e4c74..6573e0ecaa 100644 --- a/core/cortex-m/switch.S +++ b/core/cortex-m/switch.S @@ -98,4 +98,3 @@ __task_start: /* we should never return here */ mov r0, #1 @ set to EC_ERROR_UNKNOWN bx lr - diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk index 6777e8edda..eab2a1eb1c 100644 --- a/core/cortex-m0/build.mk +++ b/core/cortex-m0/build.mk @@ -6,10 +6,17 @@ # Cortex-M0 core OS files build # -# Use coreboot-sdk +ifeq ($(cc-name),gcc) +# coreboot sdk +CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- +else +# llvm sdk +CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi- +endif + $(call set-option,CROSS_COMPILE,\ $(CROSS_COMPILE_arm),\ - /opt/coreboot-sdk/bin/arm-eabi-) + $(CROSS_COMPILE_ARM_DEFAULT)) # CPU specific compilation flags CFLAGS_CPU+=-mthumb diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S index 5047d18380..6ccb75bbe8 100644 --- a/core/cortex-m0/init.S +++ b/core/cortex-m0/init.S @@ -111,19 +111,9 @@ _data_end: _data_lma_start: .long __data_lma_start -/* Mock functions to avoid linker complaints */ -.global __aeabi_unwind_cpp_pr0 -.global __aeabi_unwind_cpp_pr1 -.global __aeabi_unwind_cpp_pr2 -__aeabi_unwind_cpp_pr0: -__aeabi_unwind_cpp_pr1: -__aeabi_unwind_cpp_pr2: - bx lr - /* Reserve space for system stack */ .section .bss.system_stack stack_start: .space CONFIG_STACK_SIZE, 0 stack_end: .global stack_end - diff --git a/core/nds32/switch.S b/core/nds32/switch.S index 631b0e0fe2..13d1b14345 100644 --- a/core/nds32/switch.S +++ b/core/nds32/switch.S @@ -106,4 +106,3 @@ __task_start: /* we should never return here: set code to EC_ERROR_UNKNOWN */ movi55 $r0, 0x1 ret5 $lp - diff --git a/core/riscv-rv32i/__it8xxx2_arithmetic.S b/core/riscv-rv32i/__it8xxx2_arithmetic.S new file mode 100644 index 0000000000..8e477863fc --- /dev/null +++ b/core/riscv-rv32i/__it8xxx2_arithmetic.S @@ -0,0 +1,45 @@ +/* + * Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * When the 'M' extension is disabled, compiler can not recognize div/mul + * instructions. So mul/div instructions in the below integer arithmetic + * routines are hard coded by opcodes. + * + * IMPORTANT: + * The workaround requires the nop instruction, please don't optimize it. + */ + +.macro __int_arithmetic func opcode +.section .ram_code_ilm0 +.align 2 +.globl \func +.type \func, @function +\func: +.word \opcode +nop +ret +.size \func, .-\func +.endm + +/* signed 32 bit multiplication. opcode of mul a0,a0,a1 is 0x02b50533 */ +__int_arithmetic __mulsi3 0x02b50533 + +/* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */ +__int_arithmetic __divsi3 0x02b54533 + +/* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */ +__int_arithmetic __udivsi3 0x02b55533 + +/* + * This function return the remainder of the signed division. + * opcode of rem a0,a0,a1 is 0x02b56533 + */ +__int_arithmetic __modsi3 0x02b56533 + +/* + * This function return the remainder of the unsigned division. + * opcode of remu a0,a0,a1 is 0x02b57533 + */ +__int_arithmetic __umodsi3 0x02b57533 diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index 34f059e70c..7e5ce0e8a7 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -12,8 +12,11 @@ $(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ # Enable FPU extension if config option of FPU is enabled. _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) +# Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled. +_M_EXTENSION=$(if $(CONFIG_RISCV_EXTENSION_M),m,) # CPU specific compilation flags -CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os +CFLAGS_CPU+=-march=rv32i$(_M_EXTENSION)a$(_FPU_EXTENSION)c +CFLAGS_CPU+=-mabi=ilp32$(_FPU_EXTENSION) -Os # RISC-V does not trap division by zero, enable the sanitizer to check those. # With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the # exact issue, but the added code is as small as it gets. @@ -27,3 +30,4 @@ LDFLAGS_EXTRA+=-flto endif core-y=cpu.o init.o panic.o task.o switch.o __builtin.o math.o +core-$(CONFIG_IT8XXX2_MUL_WORKAROUND)+=__it8xxx2_arithmetic.o diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index 21c3de1143..1e629a5779 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -83,6 +83,7 @@ SECTIONS "__flash_dma_size < IT83XX_ILM_BLOCK_SIZE"); . = ALIGN(IT83XX_ILM_BLOCK_SIZE); __ilm0_ram_code = .; + KEEP(*(.ram_code_ilm0)) OUTDIR/chip/it83xx/i2c.o (.text*) OUTDIR/chip/it83xx/i2c.o (.rodata) OUTDIR/chip/it83xx/hwtimer.o (.text*) diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S index 8760667c6b..f58ac26e63 100644 --- a/core/riscv-rv32i/switch.S +++ b/core/riscv-rv32i/switch.S @@ -8,8 +8,8 @@ #include "config.h" #include "cpu.h" -#ifdef __RAM_CODE_SECTION_NAME -.section __RAM_CODE_SECTION_NAME +#ifdef __RAM_CODE_ILM0_SECTION_NAME +.section __RAM_CODE_ILM0_SECTION_NAME #endif /** diff --git a/docs/fingerprint/fingerprint-debugging.md b/docs/fingerprint/fingerprint-debugging.md index 772ea91e81..d098ca4427 100644 --- a/docs/fingerprint/fingerprint-debugging.md +++ b/docs/fingerprint/fingerprint-debugging.md @@ -32,8 +32,8 @@ used for JTAG and SWD for ARM devices. is the only software required for flashing. * In order to perform breakpoint debugging, you will need a tool that supports connecting `gdbserver`. This document will assume [CLion] \(Googlers see - [CLion for ChromeOS]) and was tested with `JLink v6.94a`. Alternatively, - you can use [Ozone], a standalone debugger from Segger. + [CLion for ChromeOS]) and was tested with `JLink v6.94a`. Alternatively, you + can use [Ozone], a standalone debugger from Segger. ## JLink Software {#software} diff --git a/docs/fingerprint/fingerprint-factory-quick-guide.md b/docs/fingerprint/fingerprint-factory-quick-guide.md index a2dd69ebe4..0e095bf9fe 100644 --- a/docs/fingerprint/fingerprint-factory-quick-guide.md +++ b/docs/fingerprint/fingerprint-factory-quick-guide.md @@ -13,48 +13,44 @@ FPMCU firmware must be flashed before fingerprint functional test is run. ODM partners may work with the module house to preflash FPMCU firmware before factory SMT. However, this way ODM partners have to coordinate with the module house to make sure the preflash FPMCU firmware blob is extracted from the FSI -release image (from /opt/google/biod/fw/). If the FPMCU firmware doesn’t match +release image (from `/opt/google/biod/fw/`). If the FPMCU firmware doesn’t match the FPMCU firmware blob checked into the release image, the end users will see the ‘critical update’ screen in their out-of-box experience, because -bio\_fw\_updater tries to update FPMCU firmware at boot time. This is a bad user +`bio_fw_updater` tries to update FPMCU firmware at boot time. This is a bad user experience we want to avoid. Most importantly, in PVT/MP build, only the FPMCU firmware in the release image would be signed by MP key. So you **MUST** ensure FPMCU is flashed with the MP-signed firmware blob extracted from FSI, before shipping the devices. As opposed to pre-flashing FPMCU in the module house, ODM partners are -encouraged to make use of -[update\_fpmcu\_firmware.py](https://chromium.googlesource.com/chromiumos/platform/factory/+/e5e903d0a0d8327dd8b9e47d2c808fd845ed73a4/py/test/pytests/update_fpmcu_firmware.py) -to update FPMCU firmware in the factory flow. This script can detect fingerprint -MCU board name, find the right FPMCU firmware blob for the DUT from the release -partition, and then flash FPMCU by flash\_fp\_mcu tool. Please note that this -script may take more than 30 secs to complete, which is slow. - -Since bio\_fw\_update has been disabled in factory test image via +encouraged to make use of [`update_fpmcu_firmware.py`] to update FPMCU firmware +in the factory flow. This script can detect fingerprint MCU board name, find the +right FPMCU firmware blob for the DUT from the release partition, and then flash +FPMCU by [`flash_fp_mcu`] tool. Please note that this script may take more than +30 secs to complete, which is slow. + +Since `bio_fw_updater` has been disabled in factory test image via [crrev/c/1913645](https://chromium-review.googlesource.com/c/chromiumos/platform2/+/1913645), in the factory flow, the FPMCU firmware should not be overwritten by -boot-update-firmware service during reboot. +`boot-update-firmware` service during reboot. ### Run fingerprint sensor functional test -Please add -[fingerprint\_mcu.py](https://chromium.git.corp.google.com/chromiumos/platform/factory/+/a283609cd8446ba4a4b75c2e1d84c9ba24ea8422/py/test/pytests/fingerprint_mcu.py) -to your device test list. A more detailed description about this test can be -found -[here](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/fingerprint/fingerprint-factory-requirements.md). +Please add [`fingerprint_mcu.py`] to your device test list. A more detailed +description about this test can be found [here][factory requirements]. ### Initialize FPMCU entropy in factory finalization The support for FPMCU entropy initialization has been integrated into the factory finalization script. So FPMCU entropy should be automatically initialized in factory finalization, if a FPMCU is found on DUT. Note that FPMCU -entropy initialization would fail if rollback\_block\_id is not equal to zero, +entropy initialization would fail if `rollback_block_id` is not equal to zero, which means the entropy has been initialized before. It is usually caused by -biod trying to initialize FPMCU entropy and increment rollback\_block\_id at -boot time. Since we have disabled biod and bio\_crypto\_init in factory test +biod trying to initialize FPMCU entropy and increment `rollback_block_id` at +boot time. Since we have disabled biod and `bio_crypto_init` in factory test image via [crrev/c/1910290](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1910290), -we expect rollback\_block\_id would stay zero during the factory flow, and FPMCU +we expect `rollback_block_id` would stay zero during the factory flow, and FPMCU entropy initialization should succeed in factory finalization. So just run factory finalization as any other CrOS boards. @@ -62,8 +58,8 @@ factory finalization as any other CrOS boards. The support for FPMCU SWWP has been integrated into factory finalization script. So FPMCU SWWP should be automatically enabled in factory finalization together -with AP/EC SWWP when write\_protection arg is set to true and a FPMCU is found -on DUT. Just run factory finalization as any other CrOS boards. +with AP/EC SWWP when `write_protection` arg is set to `true` and a FPMCU is +found on DUT. Just run factory finalization as any other CrOS boards. ### Reset entropy for factory re-finalization (in case of RMA or OQC) @@ -71,14 +67,12 @@ For the boards that have been finalized, FPMCU entropy has been initialized. So running re-finalization for those boards are expected to fail at FPMCU entropy initialization. Before running re-finalization for those boards, ODM partners have to remove hardware write protection (HWWP) and then run -[update\_fpmcu\_firmware.py](https://chromium.googlesource.com/chromiumos/platform/factory/+/d399a0a1bdeb7249de2721b269e7365e4486e23c/py/test/pytests/update_fpmcu_firmware.py) -to reset rollback\_block\_id and entropy. So the follow-up re-finalization -(which re-initialize entropy) can succeed. +[`update_fpmcu_firmware.py`] to reset `rollback_block_id` and entropy. So the +follow-up re-finalization (which re-initialize entropy) can succeed. ## References -* CrOS fingerprint factory requirements: - [doc link](https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/docs/fingerprint/fingerprint-factory-requirements.md) +* CrOS fingerprint factory requirements: [doc link][factory requirements] * The summary of CLs: * Add a factory script to update FPMCU firmware: [crrev/c/1918679](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1918679), @@ -95,3 +89,8 @@ to reset rollback\_block\_id and entropy. So the follow-up re-finalization [crrev/c/1900503](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1900503), [crrev/c/1925927](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1925927), [crrev/c/1948163](https://chromium-review.googlesource.com/c/chromiumos/platform/factory/+/1948163) + +[`update_fpmcu_firmware.py`]: https://crsrc.org/o/src/platform/factory/py/test/pytests/update_fpmcu_firmware.py;drc=672e24bb3e2dd0dec7578dcd4c52805d022662d1 +[factory requirements]: ./fingerprint-factory-requirements.md +[`fingerprint_mcu.py`]: https://crsrc.org/o/src/platform/factory/py/test/pytests/fingerprint_mcu.py;drc=672e24bb3e2dd0dec7578dcd4c52805d022662d1 +[`flash_fp_mcu`]: https://crsrc.org/o/src/platform/ec/util/flash_fp_mcu;drc=12c473337e3bdcce6d180d266c9e9f8127448f33 diff --git a/docs/fingerprint/fingerprint-factory-requirements.md b/docs/fingerprint/fingerprint-factory-requirements.md index 486d103c45..76b3ada517 100644 --- a/docs/fingerprint/fingerprint-factory-requirements.md +++ b/docs/fingerprint/fingerprint-factory-requirements.md @@ -77,10 +77,7 @@ factory branch. When the FPMCU is completely blank a low-level flashing tool must be used to program an initial version of the FPMCU firmware. It’s possible to use the -[`flash_fp_mcu`] script as this low-level flashing tool, though since it -requires the AP and is not necessarily robust against failures, it is not -recommended for mass-production. More details about [`flash_fp_mcu`] are in the -[Fingerprint flashing documentation]. +factory script [`update_fpmcu_firmware.py`] as this low-level flashing tool. The initial version of the FPMCU firmware should be flashed either by the module house or by the factory. Once an initial version of the FPMCU firmware has been @@ -497,6 +494,6 @@ Wrote /tmp/fp.1.png (14025 bytes) [ChromeOS Fingerprint Team]: http://go/cros-fingerprint-docs [Factory Fingerprint Sensor Testing for `nocturne`]: http://go/fingerprint-factory-testing-nocturne [`flash_fp_mcu`]: https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/flash_fp_mcu -[Fingerprint flashing documentation]: ./fingerprint.md#factory-rma-dev-updates [ChromeOS Config]: https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/chromeos-config/README.md [updating ChromeOS Config]: ./fingerprint.md#update-chromeos-config +[`update_fpmcu_firmware.py`]: https://crsrc.org/o/src/platform/factory/py/test/pytests/update_fpmcu_firmware.py;drc=672e24bb3e2dd0dec7578dcd4c52805d022662d1 diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md index 1185ef131c..04f5a6bab9 100644 --- a/docs/fingerprint/fingerprint.md +++ b/docs/fingerprint/fingerprint.md @@ -52,8 +52,8 @@ to determine the FPMCU that it contains: (dut) $ cros_config /fingerprint board ``` -Alternatively, if you have a Chromium OS build, you can use [ChromeOS Config] -in the chroot to determine the FPMCU: +Alternatively, if you have a Chromium OS build, you can use [ChromeOS Config] in +the chroot to determine the FPMCU: ```bash (chroot) $ cros_config_host -c /build/<BOARD>/usr/share/chromeos-config/yaml/config.yaml -m <MODEL> get /fingerprint board @@ -121,6 +121,12 @@ See the [Unit Tests] documentation for details on how to [run the unit tests]. ## Build and run the `host_command` fuzz test +<!-- mdformat off(b/139308852) --> +*** note +NOTE: For more details on fuzzing, see [Fuzz Testing in ChromeOS]. +*** +<!-- mdformat on --> + ```bash (chroot) ~/trunk/src/platform/ec $ make run-host_command_fuzz ``` @@ -523,8 +529,8 @@ detail. The fingerprint sensor may only be included on certain SKUs for a given device. The fingerprint code uses [ChromeOS Config] to determine whether a device has a fingerprint sensor or not. For each SKU, there is an associated -[fingerprint config][ChromeOS Config fingerprint]. [ChromeOS Config] -determines the [SKU information][ChromeOS Config SKU] (and thus the +[fingerprint config][ChromeOS Config fingerprint]. [ChromeOS Config] determines +the [SKU information][ChromeOS Config SKU] (and thus the [fingerprint config][ChromeOS Config fingerprint]) from [CBI Info]. The SKU for a given device can be found by viewing `chrome://system/#platform_identity_sku`. @@ -602,3 +608,4 @@ that are connected via UART use [`cros_ec_uart.c`]. [`cros_ec`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/cros_ec.c [`cros_ec_spi.c`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/cros_ec_spi.c [`cros_ec_uart.c`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/platform/chrome/cros_ec_uart.c +[Fuzz Testing in ChromeOS]: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/testing/fuzzing.md diff --git a/docs/zephyr/zephyr_motionsense.md b/docs/zephyr/zephyr_motionsense.md index b93d1ef490..4e6d0102ca 100644 --- a/docs/zephyr/zephyr_motionsense.md +++ b/docs/zephyr/zephyr_motionsense.md @@ -22,6 +22,7 @@ Kconfig Option | Default | Documentation `CONFIG_PLATFORM_EC_LID_ANGLE` | n | [LID ANGLE] `CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS` | n | [ACCELS CMD] `CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE` | n | [ACCEL SPOOF MODE] +`CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ` | n | [MAX SENSOR FREQUENCY] Additional Kconfig options are available at [Kconfig.sensor_devices](./zephyr_sensor_devices.md). @@ -282,4 +283,5 @@ lid_accel: lid-accel { [GMR TABLET MODE]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_GMR_TABLET_MODE"&ss=chromiumos [ACCEL INFO CMD]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO"&ss=chromiumos [ACCEL SPOOF CMD]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF"&ss=chromiumos +[MAX SENSOR FREQUENCY ]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.motionsense;?q="config%20PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ"&ss=chromiumos [ectool]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/util/ectool.c;?q=function:ms_help&ss=chromiumos diff --git a/driver/bc12/max14637.c b/driver/bc12/max14637.c index 60e9be8054..4c7cbffd18 100644 --- a/driver/bc12/max14637.c +++ b/driver/bc12/max14637.c @@ -147,7 +147,7 @@ static void detect_or_power_down_ic(const int port) #endif /* !defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) */ if (vbus_present) { -#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET) +#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(CONFIG_AP_POWER_CONTROL) /* Turn on the 5V rail to allow the chip to be powered. */ power_5v_enable(task_get_current(), 1); #endif @@ -167,7 +167,7 @@ static void detect_or_power_down_ic(const int port) * switch of USB2.0 can be kept close from now on. */ bc12_detect(port); -#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET) +#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(CONFIG_AP_POWER_CONTROL) /* Issue a request to turn off the rail. */ power_5v_enable(task_get_current(), 0); #endif diff --git a/driver/bc12/pi3usb9201.c b/driver/bc12/pi3usb9201.c index 6d47ed5d04..9e60c9b4fd 100644 --- a/driver/bc12/pi3usb9201.c +++ b/driver/bc12/pi3usb9201.c @@ -203,7 +203,7 @@ static void bc12_power_down(int port) if (pi3usb9201_bc12_chips[port].flags & PI3USB9201_ALWAYS_POWERED) return; -#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(HAS_TASK_CHIPSET) +#if defined(CONFIG_POWER_PP5000_CONTROL) && defined(CONFIG_AP_POWER_CONTROL) /* Indicate PP5000_A rail is not required by USB_CHG task. */ power_5v_enable(task_get_current(), 0); #endif @@ -212,7 +212,7 @@ static void bc12_power_down(int port) static void bc12_power_up(int port) { if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL) && - IS_ENABLED(HAS_TASK_CHIPSET) && + IS_ENABLED(CONFIG_AP_POWER_CONTROL) && !(pi3usb9201_bc12_chips[port].flags & PI3USB9201_ALWAYS_POWERED)) { /* Turn on the 5V rail to allow the chip to be powered. */ power_5v_enable(task_get_current(), 1); diff --git a/driver/build.mk b/driver/build.mk index 1e48d1b895..f8abe50742 100644 --- a/driver/build.mk +++ b/driver/build.mk @@ -113,6 +113,7 @@ driver-$(CONFIG_LED_DRIVER_OZ554)+=led/oz554.o driver-$(CONFIG_LED_DRIVER_IS31FL3733B)+=led/is31fl3733b.o driver-$(CONFIG_LED_DRIVER_IS31FL3743B)+=led/is31fl3743b.o driver-$(CONFIG_LED_DRIVER_AW20198)+=led/aw20198.o +driver-$(CONFIG_LED_DRIVER_TLC59116F)+=led/tlc59116f.o # 7-segment display driver-$(CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY)+=led/max695x.o diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c index f3ea29c9f5..131c611842 100644 --- a/driver/charger/sm5803.c +++ b/driver/charger/sm5803.c @@ -282,8 +282,6 @@ enum ec_error_list sm5803_set_vbus_disch(int chgnum, int enable) return rv; } -static int validate_sink_safety(int chgnum); - enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) { enum ec_error_list rv; @@ -294,16 +292,6 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) return rv; if (enable) { - /* - * Incorrect value for some registers can cause hardware - * damage; verify current configuration is safe before - * enabling sinking to prevent damage and allow debugging. - * - * TODO(b:230712704) remove this check when cause of - * incorrect behavior is understood. - */ - rv |= validate_sink_safety(chgnum); - if (chgnum == CHARGER_PRIMARY) { /* Magic for new silicon */ if (dev_id >= 3) { @@ -1915,25 +1903,6 @@ static void command_sm5803_dump(int chgnum) } #endif /* CONFIG_CMD_CHARGER_DUMP */ -static int validate_sink_safety(int chgnum) -{ - int regval = 0; - int out = chg_read8(chgnum, 0x5C, ®val); - - if (regval != 0x7A) { - CPRINTS("Register 0x5C had unexpected value 0x%02X" - " when enabling sinking", regval); -#ifdef CONFIG_CMD_CHARGER_DUMP - CPRINTS("Dumping all registers:"); - command_sm5803_dump(chgnum); -#endif - CPRINTS("Updating register 5C to expected 0x7A" - " and continuing.."); - out |= chg_write8(chgnum, 0x5C, 0x7A); - } - return out; -} - const struct charger_drv sm5803_drv = { .init = &sm5803_init, .post_init = &sm5803_post_init, diff --git a/driver/led/aw20198.c b/driver/led/aw20198.c index f307ae4a02..1322c08a09 100644 --- a/driver/led/aw20198.c +++ b/driver/led/aw20198.c @@ -107,13 +107,13 @@ static int aw20198_set_color(struct rgbkbd *ctx, uint8_t offset, buf, frame_len, NULL, 0); } -static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset, uint8_t scale, - uint8_t len) +static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset, + struct rgb_s scale, uint8_t len) { uint8_t buf[sizeof(offset) + BUF_SIZE]; const int frame_len = len * SIZE_OF_RGB + sizeof(offset); const int frame_offset = offset * SIZE_OF_RGB; - int rv; + int i, rv; if (frame_offset + frame_len > sizeof(buf)) { return EC_ERROR_OVERFLOW; @@ -124,8 +124,12 @@ static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset, uint8_t scale, return rv; } - buf[0] = offset * SIZE_OF_RGB; - memset(&buf[1], scale, len * SIZE_OF_RGB); + buf[0] = frame_offset; + for (i = 0; i < len; i++) { + buf[i * SIZE_OF_RGB + 1] = scale.r; + buf[i * SIZE_OF_RGB + 2] = scale.g; + buf[i * SIZE_OF_RGB + 3] = scale.b; + } return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len, NULL, 0); @@ -138,18 +142,28 @@ static int aw20198_set_gcc(struct rgbkbd *ctx, uint8_t level) static int aw20198_init(struct rgbkbd *ctx) { - uint8_t id; + uint8_t u8; int rv; rv = aw20198_reset(ctx); msleep(3); /* Read chip ID, assuming page is still 0. */ - rv = aw20198_read(ctx, AW20198_REG_RSTN, &id); + rv = aw20198_read(ctx, AW20198_REG_RSTN, &u8); if (rv) { return rv; } - CPRINTS("ID=0x%02x", id); + CPRINTS("ID=0x%02x", u8); + + /* Modify SWSEL bit4-7 to match the LED layout */ + rv = aw20198_get_config(ctx, AW20198_REG_GCR, &u8); + if (rv) { + return rv; + } + u8 &= ~AW20198_REG_GCR_SWSEL_MASK; + u8 |= ((ctx->cfg->col_len - 1) << AW20198_REG_GCR_SWSEL_SHIFT); + rv = aw20198_write(ctx, AW20198_REG_GCR, u8); + CPRINTS("GCR=0x%02x", u8); return rv; } diff --git a/driver/led/aw20198.h b/driver/led/aw20198.h index 02b862e27e..bbb284cc3a 100644 --- a/driver/led/aw20198.h +++ b/driver/led/aw20198.h @@ -17,7 +17,21 @@ #define AW20198_PAGE_PWM 0xC1 #define AW20198_PAGE_SCALE 0xC2 -#define AW20198_REG_GCR 0x00 +#define AW20198_REG_GCR 0x00 +#define AW20198_REG_GCR_SWSEL_MASK 0xF0 +#define AW20198_REG_GCR_SWSEL_SHIFT 4 +#define AW20198_REG_GCR_SW1_ACTIVE 0 +#define AW20198_REG_GCR_SW1_TO_SW2_ACTIVE 1 +#define AW20198_REG_GCR_SW1_TO_SW3_ACTIVE 2 +#define AW20198_REG_GCR_SW1_TO_SW4_ACTIVE 3 +#define AW20198_REG_GCR_SW1_TO_SW5_ACTIVE 4 +#define AW20198_REG_GCR_SW1_TO_SW6_ACTIVE 5 +#define AW20198_REG_GCR_SW1_TO_SW7_ACTIVE 6 +#define AW20198_REG_GCR_SW1_TO_SW8_ACTIVE 7 +#define AW20198_REG_GCR_SW1_TO_SW9_ACTIVE 8 +#define AW20198_REG_GCR_SW1_TO_SW10_ACTIVE 9 +#define AW20198_REG_GCR_SW1_TO_SW11_ACTIVE 10 + #define AW20198_REG_GCC 0x01 #define AW20198_REG_RSTN 0x2F #define AW20198_REG_MIXCR 0x46 diff --git a/driver/led/is31fl3733b.c b/driver/led/is31fl3733b.c index 429743e51b..5b1df890f1 100644 --- a/driver/led/is31fl3733b.c +++ b/driver/led/is31fl3733b.c @@ -178,7 +178,7 @@ static int is31fl3733b_set_color(struct rgbkbd *ctx, uint8_t offset, } static int is31fl3733b_set_scale(struct rgbkbd *ctx, uint8_t offset, - uint8_t scale, uint8_t len) + struct rgb_s scale, uint8_t len) { /* is31fl3733b not support scale function */ return EC_SUCCESS; diff --git a/driver/led/is31fl3743b.c b/driver/led/is31fl3743b.c index df333f2c8e..a07b2f63f8 100644 --- a/driver/led/is31fl3743b.c +++ b/driver/led/is31fl3743b.c @@ -106,31 +106,37 @@ static int is31fl3743b_set_color(struct rgbkbd *ctx, uint8_t offset, msg->addr = frame_offset + 1; /* Register addr base is 1. */ for (i = 0; i < len; i++) { - msg->payload[i * SIZE_OF_RGB +0] = color[i].r; - msg->payload[i * SIZE_OF_RGB +1] = color[i].g; - msg->payload[i * SIZE_OF_RGB +2] = color[i].b; + msg->payload[i * SIZE_OF_RGB + 0] = color[i].r; + msg->payload[i * SIZE_OF_RGB + 1] = color[i].g; + msg->payload[i * SIZE_OF_RGB + 2] = color[i].b; } return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, NULL, 0); } static int is31fl3743b_set_scale(struct rgbkbd *ctx, uint8_t offset, - uint8_t scale, uint8_t len) + struct rgb_s scale, uint8_t len) { uint8_t buf[sizeof(struct is31fl3743b_msg) + IS31FL3743B_BUF_SIZE]; struct is31fl3743b_msg *msg = (void *)buf; const int frame_len = len * SIZE_OF_RGB + sizeof(*msg); + const int frame_offset = offset * SIZE_OF_RGB; + int i; msg->cmd.read = 0; msg->cmd.id = IS31FL3743B_CMD_ID; msg->cmd.page = IS31FL3743B_PAGE_SCALE; - if (offset + frame_len > sizeof(buf)) { + if (frame_offset + frame_len > sizeof(buf)) { return EC_ERROR_OVERFLOW; } - msg->addr = offset + 1; /* Address base is 1. */ - memset(msg->payload, scale, len * SIZE_OF_RGB); + msg->addr = frame_offset + 1; /* Address base is 1. */ + for (i = 0; i < len; i++) { + msg->payload[i * SIZE_OF_RGB + 0] = scale.r; + msg->payload[i * SIZE_OF_RGB + 1] = scale.g; + msg->payload[i * SIZE_OF_RGB + 2] = scale.b; + } return spi_transaction(SPI(ctx->cfg->spi), buf, frame_len, NULL, 0); } diff --git a/driver/led/tlc59116f.c b/driver/led/tlc59116f.c new file mode 100644 index 0000000000..b1c16a921b --- /dev/null +++ b/driver/led/tlc59116f.c @@ -0,0 +1,129 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <string.h> + +#include "common.h" +#include "console.h" +#include "i2c.h" +#include "rgb_keyboard.h" +#include "stddef.h" +#include "tlc59116f.h" + +#define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "TLC59116F: " fmt, ##args) +#define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "TLC59116F: " fmt, ##args) + +#define TLC59116F_BUF_SIZE (SIZE_OF_RGB * TLC59116F_GRID_SIZE) +#define TLC59116_MODE_BIT_SLEEP 4 + +static int tlc59116f_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value) +{ + return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, + &addr, sizeof(addr), value, sizeof(*value)); +} + +static int tlc59116f_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) +{ + uint8_t buf[2] = { + [0] = addr, + [1] = value, + }; + + return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, + buf, sizeof(buf), NULL, 0); +} + +static int tlc59116f_reset(struct rgbkbd *ctx) +{ + return i2c_write8(ctx->cfg->i2c, TLC59116F_RESET, 0xA5, 0x5A); +} + +static int tlc59116f_init(struct rgbkbd *ctx) +{ + int i, rv; + + for (i = TLC59116F_LEDOUT0; i <= TLC59116F_LEDOUT3; i++) { + rv = tlc59116f_write(ctx, i, TLC59116_LEDOUT_PWM); + if (rv) { + return rv; + } + } + + rv = tlc59116f_write(ctx, TLC59116F_MODE1, 0x01); + if (rv) { + CPRINTS("Failed to set TLC59116F normal mode"); + return rv; + } + + return EC_SUCCESS; +} + +static int tlc59116f_enable(struct rgbkbd *ctx, bool enable) +{ + uint8_t cfg; + int rv; + + rv = tlc59116f_read(ctx, TLC59116F_MODE1, &cfg); + if (rv) { + CPRINTS("Failed to enable TLC59116F"); + return rv; + } + + WRITE_BIT(cfg, TLC59116_MODE_BIT_SLEEP, !enable); + return tlc59116f_write(ctx, TLC59116F_MODE1, cfg); +} + +static int tlc59116f_set_color(struct rgbkbd *ctx, uint8_t offset, + struct rgb_s *color, uint8_t len) +{ + uint8_t buf[sizeof(offset) + TLC59116F_BUF_SIZE]; + const int frame_len = len * SIZE_OF_RGB + sizeof(offset); + const int frame_offset = offset * SIZE_OF_RGB; + int i; + + if (frame_offset + frame_len > sizeof(buf)) { + return EC_ERROR_OVERFLOW; + } + + buf[0] = TLC59116_AI_BRIGHTNESS_ONLY | + (frame_offset + TLC59116F_PWM0); + for (i = 0; i < len; i++) { + buf[i * SIZE_OF_RGB + 1] = color[i].r; + buf[i * SIZE_OF_RGB + 2] = color[i].g; + buf[i * SIZE_OF_RGB + 3] = color[i].b; + } + + return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, + buf, frame_len, NULL, 0); +} + +static int tlc59116f_set_scale(struct rgbkbd *ctx, uint8_t offset, + struct rgb_s scale, uint8_t len) +{ + /* tlc59116f not support scale function */ + return EC_SUCCESS; +} + +static int tlc59116f_set_gcc(struct rgbkbd *ctx, uint8_t level) +{ + int j, rv; + + for (j = TLC59116F_LEDOUT0; j <= TLC59116F_LEDOUT3; j++) { + rv = tlc59116f_write(ctx, j, TLC59116_LEDOUT_GROUP); + if (rv) { + return rv; + } + } + + return tlc59116f_write(ctx, TLC59116F_GRPPWM, level); +} + +const struct rgbkbd_drv tlc59116f_drv = { + .reset = tlc59116f_reset, + .init = tlc59116f_init, + .enable = tlc59116f_enable, + .set_color = tlc59116f_set_color, + .set_scale = tlc59116f_set_scale, + .set_gcc = tlc59116f_set_gcc, +}; diff --git a/driver/led/tlc59116f.h b/driver/led/tlc59116f.h new file mode 100644 index 0000000000..68ce218517 --- /dev/null +++ b/driver/led/tlc59116f.h @@ -0,0 +1,74 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_DRIVER_LED_TLC59116F_H +#define __CROS_EC_DRIVER_LED_TLC59116F_H + +/* TLC59116F secondary address */ +#define TLC59116F_ADDR0_FLAG 0x60 +#define TLC59116F_ADDR1_FLAG 0x61 +#define TLC59116F_ADDR2_FLAG 0x62 +#define TLC59116F_ADDR3_FLAG 0x63 +#define TLC59116F_ADDR4_FLAG 0x64 +#define TLC59116F_ADDR5_FLAG 0x65 +#define TLC59116F_ADDR6_FLAG 0x66 +#define TLC59116F_ADDR7_FLAG 0x67 +#define TLC59116F_ADDR8_FLAG 0x68 +#define TLC59116F_ADDR9_FLAG 0x69 +#define TLC59116F_ADDR10_FLAG 0x6A +#define TLC59116F_RESET 0x6B +#define TLC59116F_ADDR12_FLAG 0x6C +#define TLC59116F_ADDR13_FLAG 0x6D +#define TLC59116F_ADDR14_FLAG 0x6E +#define TLC59116F_ADDR15_FLAG 0x6F + +#define TLC59116F_ROW_SIZE 1 +#define TLC59116F_COL_SIZE 5 +#define TLC59116F_GRID_SIZE (TLC59116F_COL_SIZE * TLC59116F_ROW_SIZE) + +/* TLC59116F registers */ +#define TLC59116F_MODE1 0x00 +#define TLC59116F_MODE2 0x01 +#define TLC59116F_PWM0 0x02 +#define TLC59116F_PWM1 0x03 +#define TLC59116F_PWM2 0x04 +#define TLC59116F_PWM3 0x05 +#define TLC59116F_PWM4 0x06 +#define TLC59116F_PWM5 0x07 +#define TLC59116F_PWM6 0x08 +#define TLC59116F_PWM7 0x09 +#define TLC59116F_PWM8 0x0A +#define TLC59116F_PWM9 0x0B +#define TLC59116F_PWM10 0x0C +#define TLC59116F_PWM11 0x0D +#define TLC59116F_PWM12 0x0E +#define TLC59116F_PWM13 0x0F +#define TLC59116F_PWM14 0x10 +#define TLC59116F_PWM15 0x11 +#define TLC59116F_GRPPWM 0x12 +#define TLC59116F_GRPFREQ 0x13 +#define TLC59116F_LEDOUT0 0x14 +#define TLC59116F_LEDOUT1 0x15 +#define TLC59116F_LEDOUT2 0x16 +#define TLC59116F_LEDOUT3 0x17 +#define TLC59116F_SUBADR1 0x18 +#define TLC59116F_SUBADR2 0x19 +#define TLC59116F_SUBADR3 0x1A +#define TLC59116F_ALLCALLADR 0x1B + +#define TLC59116_LEDOUT_OFF 0x00 +#define TLC59116_LEDOUT_ON 0x55 +#define TLC59116_LEDOUT_PWM 0xAA +#define TLC59116_LEDOUT_GROUP 0xFF + +/* Auto Increment flag */ +#define TLC59116_AI_NONE 0 +#define TLC59116_AI_ALL BIT(7) +#define TLC59116_AI_BRIGHTNESS_ONLY (BIT(7) | BIT(5)) +#define TLC59116_AI_GCR_ONLY (BIT(7) | BIT(6)) + +extern const struct rgbkbd_drv tlc59116f_drv; + +#endif /* __CROS_EC_DRIVER_LED_TLC59116F_H */ diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index 2add843611..6804fd3de8 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -6,6 +6,7 @@ */ #include "anx7483.h" +#include "retimer/anx7483_public.h" #include "chipset.h" #include "common.h" #include "console.h" @@ -315,6 +316,34 @@ enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, return EC_SUCCESS; } +enum ec_error_list anx7483_set_eq(const struct usb_mux *me, + enum anx7483_tune_pin pin, + enum anx7483_eq_setting eq) +{ + int reg, value; + + if (pin == ANX7483_PIN_UTX1) + reg = ANX7483_UTX1_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_UTX2) + reg = ANX7483_UTX2_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_URX1) + reg = ANX7483_URX1_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_URX2) + reg = ANX7483_URX2_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_DRX1) + reg = ANX7483_DRX1_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_DRX2) + reg = ANX7483_DRX2_PORT_CFG0_REG; + else + return EC_ERROR_INVAL; + + RETURN_ERROR(anx7483_read(me, reg, &value)); + value &= ~ANX7483_CFG0_EQ_MASK; + value |= eq << ANX7483_CFG0_EQ_SHIFT; + + return anx7483_write(me, reg, value); +} + const struct usb_mux_driver anx7483_usb_retimer_driver = { .init = anx7483_init, .set = anx7483_set, diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h index 2caf007a03..d5f6723818 100644 --- a/driver/retimer/anx7483.h +++ b/driver/retimer/anx7483.h @@ -50,6 +50,9 @@ #define ANX7483_DRX1_PORT_CFG0_REG 0x5C #define ANX7483_DRX2_PORT_CFG0_REG 0x20 +#define ANX7483_CFG0_EQ_SHIFT 4 +#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4) + /* * Default CFG0 value to apply: 9.2 dB with optimized tuning step */ diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c index 3815b7bdbd..8bd0be36f4 100644 --- a/driver/tcpm/anx7447.c +++ b/driver/tcpm/anx7447.c @@ -877,6 +877,24 @@ static int anx7447_get_chip_info(int port, int live, return EC_SUCCESS; } +enum ec_error_list anx7447_set_bist_test_mode(const int port, const bool enable) +{ + /* + * Set CC debounce type as millisecond if enable BIST mode, + * otherwise microsecond + */ + RETURN_ERROR(tcpc_update8(port, ANX7447_REG_TCPC_CTRL_1, CC_DEBOUNCE_MS, + enable ? MASK_SET : MASK_CLR)); + /* + * Set CC debounce time to 2ms if enable BIST mode, + * otherwise set debounce time to 10us + */ + RETURN_ERROR(tcpc_write(port, ANX7447_REG_CC_DEBOUNCE_TIME, + enable ? 2 : 10)); + + return EC_SUCCESS; +} + /* * ANX7447 is a TCPCI compatible port controller, with some caveats. * It seems to require both CC lines to be set always, instead of just @@ -916,7 +934,7 @@ const struct tcpm_drv anx7447_tcpm_drv = { #ifdef CONFIG_USB_PD_TCPC_LOW_POWER .enter_low_power_mode = &tcpci_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &anx7447_set_bist_test_mode, #ifdef CONFIG_CMD_TCPC_DUMP .dump_registers = &anx7447_dump_registers, #endif diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h index e84ac91a89..30396c26b3 100644 --- a/driver/tcpm/anx7447.h +++ b/driver/tcpm/anx7447.h @@ -42,7 +42,11 @@ #define ANX7447_REG_INTP_MASK_0 0x86 +#define ANX7447_REG_TCPC_CTRL_1 0x9D +#define CC_DEBOUNCE_MS BIT(3) +#define CC_DEBOUNCE_TIME_HI_BIT BIT(0) #define ANX7447_REG_INTP_CTRL_0 0x9E +#define ANX7447_REG_CC_DEBOUNCE_TIME 0x9F #define ANX7447_REG_ANALOG_CTRL_8 0xA8 #define ANX7447_REG_VCONN_OCP_MASK 0x0C diff --git a/driver/tcpm/ccgxxf.c b/driver/tcpm/ccgxxf.c index 61985d90ae..ee1754ce08 100644 --- a/driver/tcpm/ccgxxf.c +++ b/driver/tcpm/ccgxxf.c @@ -6,6 +6,7 @@ */ #include "ccgxxf.h" +#include "console.h" #include "tcpm/tcpci.h" #ifdef CONFIG_USB_PD_TCPM_SBU @@ -15,6 +16,22 @@ static int ccgxxf_tcpc_set_sbu(int port, bool enable) } #endif +#ifdef CONFIG_CMD_TCPC_DUMP +static void ccgxxf_dump_registers(int port) +{ + int fw_ver, fw_build; + + tcpc_dump_std_registers(port); + + /* Get the F/W version and build ID */ + if (!tcpc_read16(port, CCGXXF_REG_FW_VERSION, &fw_ver) && + !tcpc_read16(port, CCGXXF_REG_FW_VERSION_BUILD, &fw_build)) { + ccprintf(" FW_VERSION(build.major.minor) = %d.%d.%d\n", + fw_build & 0xFF, (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); + } +} +#endif + const struct tcpm_drv ccgxxf_tcpm_drv = { .init = &tcpci_tcpm_init, .release = &tcpci_tcpm_release, @@ -57,6 +74,6 @@ const struct tcpm_drv ccgxxf_tcpm_drv = { #endif .set_bist_test_mode = &tcpci_set_bist_test_mode, #ifdef CONFIG_CMD_TCPC_DUMP - .dump_registers = &tcpc_dump_std_registers, + .dump_registers = &ccgxxf_dump_registers, #endif }; diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h index 9d4e3ca0ed..246a231d04 100644 --- a/driver/tcpm/ccgxxf.h +++ b/driver/tcpm/ccgxxf.h @@ -16,6 +16,10 @@ /* SBU FET control register */ #define CCGXXF_REG_SBU_MUX_CTL 0xBB +/* F/W info register */ +#define CCGXXF_REG_FW_VERSION 0x94 +#define CCGXXF_REG_FW_VERSION_BUILD 0x96 + extern const struct tcpm_drv ccgxxf_tcpm_drv; /* CCGXXF built in I/O expander definitions */ diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c index d90e09805d..e985419668 100644 --- a/driver/tcpm/rt1718s.c +++ b/driver/tcpm/rt1718s.c @@ -207,7 +207,7 @@ static int rt1718s_workaround(int port) 0xFF)); RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4, RT1718S_VCON_CTRL4_UVP_CP_EN | - RT1718S_VCON_CTRL4_OVP_CP_EN, + RT1718S_VCON_CTRL4_OCP_CP_EN, 0)); RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_2, RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 | @@ -222,6 +222,42 @@ static int rt1718s_workaround(int port) return EC_SUCCESS; } +static int rt1718s_set_vconn(int port, int enable) +{ + if (enable) { + /* + * b/233698718#comment9: The initial output spike will be likely + * trigger the Vconn OCP. Workaround this by disabling the OCP + * at the beginning of sourcing Vconn, and then enable OCP back + * after Vconn sourced. + */ + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL3, + RT1718S_VCON_LIMIT_MODE, + 0xFF)); + + /* Enable Vconn RVP */ + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_VCONN_CONTROL_2, + RT1718S_VCONN_CONTROL_2_RVP_EN, 0xFF)); + } + + RETURN_ERROR(tcpci_tcpm_set_vconn(port, enable)); + + if (enable) { + /* It takes 10ms that we can switch back to shutdown mode. */ + msleep(10); + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL3, + RT1718S_VCON_LIMIT_MODE, 0)); + } else { + /* Disable Vconn RVP */ + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_VCONN_CONTROL_2, + RT1718S_VCONN_CONTROL_2_RVP_EN, 0x0)); + } + + return EC_SUCCESS; +} + static int rt1718s_init(int port) { static bool need_sw_reset = true; @@ -242,6 +278,10 @@ static int rt1718s_init(int port) RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3, RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL, 0x7F)); + /* Increase the Vconn OCP shoot detection from 200ns to 3~5us */ + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4, + RT1718S_VCON_CTRL4_OCP_CP_EN, 0)); + /* Disable FOD function */ RETURN_ERROR(rt1718s_update_bits8(port, 0xCF, 0x40, 0x00)); @@ -722,6 +762,22 @@ static int command_rt1718s_gpio(int argc, char **argv) } DECLARE_CONSOLE_COMMAND(rt1718s_gpio, command_rt1718s_gpio, "", "RT1718S GPIO"); +#ifdef CONFIG_USB_PD_TCPM_SBU +static int rt1718s_set_sbu(int port, bool enable) +{ + /* + * The `enable` here means to enable the SBU line (set 1) + * - true: connect SBU lines from outer to the host + * - false: isolate the SBU lines + */ + return rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, + RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | + RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN | + RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN, + enable ? 0xFF : 0); +} +#endif + /* RT1718S is a TCPCI compatible port controller */ const struct tcpm_drv rt1718s_tcpm_drv = { .init = &rt1718s_init, @@ -736,7 +792,7 @@ const struct tcpm_drv rt1718s_tcpm_drv = { #ifdef CONFIG_USB_PD_DECODE_SOP .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, + .set_vconn = &rt1718s_set_vconn, .set_msg_header = &tcpci_tcpm_set_msg_header, .set_rx_enable = &tcpci_tcpm_set_rx_enable, .get_message_raw = &tcpci_tcpm_get_message_raw, @@ -758,6 +814,9 @@ const struct tcpm_drv rt1718s_tcpm_drv = { .set_frs_enable = &rt1718s_set_frs_enable, #endif .set_bist_test_mode = &tcpci_set_bist_test_mode, +#ifdef CONFIG_USB_PD_TCPM_SBU + .set_sbu = &rt1718s_set_sbu, +#endif }; const struct bc12_drv rt1718s_bc12_drv = { diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h index e108c41db2..a4f7545a06 100644 --- a/driver/tcpm/rt1718s.h +++ b/driver/tcpm/rt1718s.h @@ -26,6 +26,7 @@ #define RT1718S_PHYCTRL7 0x86 #define RT1718S_VCON_CTRL1 0x8A #define RT1718S_VCON_CTRL3 0x8C +#define RT1718S_VCON_LIMIT_MODE BIT(0) #define RT1718S_SYS_CTRL1 0x8F #define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID BIT(6) #define RT1718S_SYS_CTRL1_SHIPPING_OFF BIT(5) @@ -36,6 +37,7 @@ #define RT1718S_VCONN_CONTROL_2 0x8B #define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7) #define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6) +#define RT1718S_VCONN_CONTROL_2_RVP_EN BIT(3) #define RT1718S_VCONN_CONTROL_3 0x8C #define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL GENMASK(7, 5) #define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1) @@ -128,7 +130,7 @@ #define RT1718S_VCON_CTRL4 0xF211 #define RT1718S_VCON_CTRL4_UVP_CP_EN BIT(5) -#define RT1718S_VCON_CTRL4_OVP_CP_EN BIT(4) +#define RT1718S_VCON_CTRL4_OCP_CP_EN BIT(4) #define RT1718S_RT2_VBUS_OCRC_EN 0xF214 #define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN BIT(0) diff --git a/driver/usb_mux/ps8743.c b/driver/usb_mux/ps8743.c index f126d36378..28ad5e9546 100644 --- a/driver/usb_mux/ps8743.c +++ b/driver/usb_mux/ps8743.c @@ -6,11 +6,23 @@ */ #include "common.h" +#include "hooks.h" #include "i2c.h" #include "ps8743.h" #include "usb_mux.h" +#include "usb_mux/ps8743_public.h" +#include "usb_pd.h" #include "util.h" +enum usb_conn_status { + NO_DEVICE, + USB2_CONNECTED, + USB3_CONNECTED, + UNKNOWN, +}; + +static enum usb_conn_status saved_usb_conn_status[CONFIG_USB_PD_PORT_MAX_COUNT]; + int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, @@ -119,6 +131,9 @@ static int ps8743_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_USB_ENABLED) reg |= PS8743_MODE_USB_ENABLE; + else + saved_usb_conn_status[me->usb_port] = NO_DEVICE; + if (mux_state & USB_PD_MUX_DP_ENABLED) reg |= PS8743_MODE_DP_ENABLE | PS8743_MODE_IN_HPD_ASSERT; if (mux_state & USB_PD_MUX_POLARITY_INVERTED) @@ -164,3 +179,74 @@ const struct usb_mux_driver ps8743_usb_mux_driver = { .set = ps8743_set_mux, .get = ps8743_get_mux, }; + +static bool ps8743_port_is_usb_mode_only(const struct usb_mux *me) +{ + int val; + + if (ps8743_read(me, PS8743_MISC_HPD_DP_USB_FLIP, &val)) + return false; + + val &= (PS8743_USB_MODE_STATUS | PS8743_DP_MODE_STATUS); + + return val == PS8743_USB_MODE_STATUS; +} + +static enum usb_conn_status ps8743_get_usb_conn_status(const struct usb_mux *me) +{ + int val; + + if (ps8743_read(me, PS8743_MISC_DCI_SS_MODES, &val)) + return UNKNOWN; + + if (val == 0) + return NO_DEVICE; + + val &= (PS8743_SSTX_NORMAL_OPERATION_MODE | + PS8743_SSTX_POWER_SAVING_MODE | PS8743_SSTX_SUSPEND_MODE); + + return (val != PS8743_SSTX_NORMAL_OPERATION_MODE && + val != PS8743_SSTX_POWER_SAVING_MODE) ? + USB2_CONNECTED : + USB3_CONNECTED; +} + +static void ps8743_suspend(void) +{ + for (int i = 0; i < board_get_usb_pd_port_count(); i++) { + const struct usb_mux *mux = &usb_muxes[i]; + + if (mux->driver != &ps8743_usb_mux_driver) + continue; + + saved_usb_conn_status[i] = ps8743_get_usb_conn_status(mux); + + if (ps8743_port_is_usb_mode_only(mux) && + saved_usb_conn_status[i] == USB2_CONNECTED) { + ps8743_field_update(mux, PS8743_REG_MODE, + PS8743_MODE_USB_ENABLE, 0); + } + } +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, ps8743_suspend, HOOK_PRIO_DEFAULT); + +static void ps8743_resume(void) +{ + for (int i = 0; i < board_get_usb_pd_port_count(); i++) { + const struct usb_mux *mux = &usb_muxes[i]; + + if (mux->driver != &ps8743_usb_mux_driver) + continue; + + if (saved_usb_conn_status[i] != NO_DEVICE) { + ps8743_field_update(mux, PS8743_REG_MODE, + PS8743_MODE_USB_ENABLE, + PS8743_MODE_USB_ENABLE); + } + } +} +#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK +DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, ps8743_resume, HOOK_PRIO_DEFAULT); +#else +DECLARE_HOOK(HOOK_CHIPSET_RESUME, ps8743_resume, HOOK_PRIO_DEFAULT); +#endif diff --git a/driver/usb_mux/ps8743.h b/driver/usb_mux/ps8743.h index 741b93e98a..8e3a9d9b4c 100644 --- a/driver/usb_mux/ps8743.h +++ b/driver/usb_mux/ps8743.h @@ -29,4 +29,15 @@ #define PS8743_CHIP_ID1 0x41 #define PS8743_CHIP_ID2 0x87 +/* Misc register for checking DCI / SS pair mode status */ +#define PS8743_MISC_DCI_SS_MODES 0x42 +#define PS8743_SSTX_NORMAL_OPERATION_MODE BIT(4) +#define PS8743_SSTX_POWER_SAVING_MODE BIT(5) +#define PS8743_SSTX_SUSPEND_MODE BIT(6) + +/* Misc resiger for checking HPD / DP / USB / FLIP mode status */ +#define PS8743_MISC_HPD_DP_USB_FLIP 0x09 +#define PS8743_USB_MODE_STATUS BIT(3) +#define PS8743_DP_MODE_STATUS BIT(4) + #endif /* __CROS_EC_PS8743_H */ diff --git a/fuzz/build.mk b/fuzz/build.mk index 3b5f117d20..ebb5a3a839 100644 --- a/fuzz/build.mk +++ b/fuzz/build.mk @@ -31,4 +31,4 @@ usb_tcpm_v2_rev30_fuzz-y = usb_pd_fuzz.o usb_tcpm_v2_rev30_fuzz.o \ ../test/fake_battery.o usb_tcpm_v2_rev20_fuzz-y = usb_pd_fuzz.o usb_tcpm_v2_rev20_fuzz.o \ ../test/fake_battery.o -pchg_fuzz-y = pchg_fuzz.o
\ No newline at end of file +pchg_fuzz-y = pchg_fuzz.o diff --git a/include/charge_state.h b/include/charge_state.h index 9349c3ea4c..ed777c1a64 100644 --- a/include/charge_state.h +++ b/include/charge_state.h @@ -96,17 +96,15 @@ int charge_keep_power_off(void); */ uint32_t charge_get_flags(void); -#if defined(CONFIG_CHARGER) /** * Return current battery charge percentage. */ int charge_get_percent(void); -#elif defined(CONFIG_BATTERY) + /** * Return current battery charge if not using charge manager sub-system. */ int board_get_battery_soc(void); -#endif /** * Return current display charge in 10ths of a percent (e.g. 1000 = 100.0%) diff --git a/include/chipset.h b/include/chipset.h index 51a9018dfb..840db3aa60 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -48,7 +48,7 @@ enum critical_shutdown { CRITICAL_SHUTDOWN_CUTOFF, }; -#if defined(HAS_TASK_CHIPSET) || defined(CONFIG_ZEPHYR) +#ifdef CONFIG_AP_POWER_CONTROL /** * Check if chipset is in a given state. @@ -125,7 +125,7 @@ void chipset_pre_init_callback(void); */ void init_reset_log(void); -#else /* !HAS_TASK_CHIPSET */ +#else /* !CONFIG_AP_POWER_CONTROL */ /* When no chipset is present, assume it is always off. */ static inline int chipset_in_state(int state_mask) @@ -156,7 +156,7 @@ static inline void chipset_watchdog_interrupt(enum gpio_signal signal) { } static inline void init_reset_log(void) { } -#endif /* !HAS_TASK_CHIPSET */ +#endif /* !CONFIG_AP_POWER_CONTROL */ /** * Optional chipset check if PLTRST# is valid. diff --git a/include/common.h b/include/common.h index 33c9ab97c2..02989c692b 100644 --- a/include/common.h +++ b/include/common.h @@ -238,6 +238,22 @@ return error; \ } while (0) +/* + * Define test_mockable and test_mockable_static for mocking + * functions. + */ +#ifdef TEST_BUILD +#define test_mockable __attribute__((weak)) +#define test_mockable_static __attribute__((weak)) +#define test_mockable_static_inline __attribute__((weak)) +#define test_export_static +#else +#define test_mockable +#define test_mockable_static static +#define test_mockable_static_inline static inline +#define test_export_static static +#endif + /* Include top-level configuration file */ #include "config.h" @@ -336,22 +352,6 @@ enum ec_error_list { }; /* - * Define test_mockable and test_mockable_static for mocking - * functions. - */ -#ifdef TEST_BUILD -#define test_mockable __attribute__((weak)) -#define test_mockable_static __attribute__((weak)) -#define test_mockable_static_inline __attribute__((weak)) -#define test_export_static -#else -#define test_mockable -#define test_mockable_static static -#define test_mockable_static_inline static inline -#define test_export_static static -#endif - -/* * Attribute to define functions to only be used in test code, causing * a compiler error if used without TEST_BUILD defined. * diff --git a/include/config.h b/include/config.h index b19f76f614..523d94a8a8 100644 --- a/include/config.h +++ b/include/config.h @@ -2879,6 +2879,18 @@ #undef CONFIG_IT83XX_VCC_3P3V /* + * Overwrite integer multiplication and division arithmetic library routines + * with using hardware multiplication and division and nop instructions. + */ +#undef CONFIG_IT8XXX2_MUL_WORKAROUND + +/* + * Support the standard integer multiplication and division instruction + * extension. + */ +#define CONFIG_RISCV_EXTENSION_M + +/* * If this is not defined, the firmware will revert the JTAG selection * triggered by the hardware strap pin. * Un-define this flag by default for all real platforms. see (b/129908668) @@ -3150,6 +3162,7 @@ #undef CONFIG_LED_DRIVER_IS31FL3733B /* Lumissil IS31FL3733B on I2C */ #undef CONFIG_LED_DRIVER_IS31FL3743B /* Lumissil IS31FL3743B on SPI */ #undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ +#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ /* Enable late init for is31fl3743b. Work around b:232443638. */ #undef CONFIG_IS31FL3743B_LATE_INIT @@ -6266,6 +6279,17 @@ #endif /* + * If the chipset task is enabled, this implies there is an AP to manage power + * for. In Zephyr this can be implied by multiple options, so we provide the + * same symbol here instead of making code examine HAS_TASK_CHIPSET. + */ +#ifndef CONFIG_AP_POWER_CONTROL +#ifdef HAS_TASK_CHIPSET +#define CONFIG_AP_POWER_CONTROL +#endif /* HAS_TASK_CHIPSET */ +#endif /* CONFIG_AP_POWER_CONTROL */ + +/* * If a board has a chipset task, set the minimum charger power required for * powering on to 15W. This is also the highest power discovered over Type-C by * analog signaling. The EC normally does not communicate using USB PD when the diff --git a/include/console.h b/include/console.h index 6197b84ce2..457d24cc95 100644 --- a/include/console.h +++ b/include/console.h @@ -256,7 +256,7 @@ void console_has_input(void); #define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ static int (ROUTINE)(int argc, char **argv); \ static const char __con_cmd_label_##NAME[] = #NAME; \ - _Static_assert(sizeof(__con_cmd_label_##NAME) < 16, \ + _STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16, \ "command name '" #NAME "' is too long"); \ const struct console_command __keep __no_sanitize_address \ __con_cmd_##NAME \ diff --git a/include/cros_board_info.h b/include/cros_board_info.h index 7a79cfee2a..9ed5e1777b 100644 --- a/include/cros_board_info.h +++ b/include/cros_board_info.h @@ -191,9 +191,9 @@ int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size); /** * Set and update FW_CONFIG tag field * - * This function is only included when HAS_TASK_CHIPSET is not defined. It is - * intended to be used for projects which want CBI functions, but do not have an - * AP and ectool host command access. + * This function is only included when CONFIG_AP_POWER_CONTROL is disabled. It + * is intended to be used for projects which want CBI functions, but do not + * have an AP and ectool host command access. * * @param fw_config updated value for FW_CONFIG tag * @return EC_SUCCESS to indicate the field was written correctly. diff --git a/include/cros_version.h b/include/cros_version.h index 585c2c1013..47fa8d1774 100644 --- a/include/cros_version.h +++ b/include/cros_version.h @@ -17,6 +17,8 @@ #define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8) #define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0) +#define CROS_FWID_MISSING_STR "CROS_FWID_MISSING" + struct image_data { uint32_t cookie1; char version[32]; diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index f7654837db..8c3b9eaf60 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -18,6 +18,40 @@ #define ANX7483_I2C_ADDR2_FLAGS 0x40 #define ANX7483_I2C_ADDR3_FLAGS 0x44 +/* Equalization tuning */ +enum anx7483_eq_setting { + ANX7483_EQ_SETTING_3_9DB = 0, + ANX7483_EQ_SETTING_4_7DB = 1, + ANX7483_EQ_SETTING_5_5DB = 2, + ANX7483_EQ_SETTING_6_1DB = 3, + ANX7483_EQ_SETTING_6_8DB = 4, + ANX7483_EQ_SETTING_7_3DB = 5, + ANX7483_EQ_SETTING_7_8DB = 6, + ANX7483_EQ_SETTING_8_1DB = 7, + ANX7483_EQ_SETTING_8_4DB = 8, + ANX7483_EQ_SETTING_8_7DB = 9, + ANX7483_EQ_SETTING_9_2DB = 10, + ANX7483_EQ_SETTING_9_7DB = 11, + ANX7483_EQ_SETTING_10_3DB = 12, + ANX7483_EQ_SETTING_11_1DB = 13, + ANX7483_EQ_SETTING_11_8DB = 14, + ANX7483_EQ_SETTING_12_5DB = 15, +}; + +enum anx7483_tune_pin { + ANX7483_PIN_UTX1, + ANX7483_PIN_UTX2, + ANX7483_PIN_URX1, + ANX7483_PIN_URX2, + ANX7483_PIN_DRX1, + ANX7483_PIN_DRX2, +}; + +/* Adjust the equalization for a pin */ +enum ec_error_list anx7483_set_eq(const struct usb_mux *me, + enum anx7483_tune_pin pin, + enum anx7483_eq_setting eq); + /* Configure datasheet defaults for tuning registers at this mux setting */ enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state); diff --git a/include/ec_commands.h b/include/ec_commands.h index 3755acce19..b11b34b5fd 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -4727,7 +4727,7 @@ struct ec_params_dedicated_charger_limit { /* * Get and set charging splashscreen variables */ -#define EC_CMD_CHARGESPLASH 0x00A4 +#define EC_CMD_CHARGESPLASH 0x00A5 enum ec_chargesplash_cmd { /* Get the current state variables */ @@ -7139,6 +7139,7 @@ struct ec_response_i2c_control { #define EC_RGBKBD_MAX_KEY_COUNT 128 #define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF +#define EC_RGBKBD_MAX_SCALE 0xFF enum rgbkbd_state { /* RGB keyboard is reset and not initialized. */ @@ -7156,13 +7157,31 @@ enum rgbkbd_state { enum ec_rgbkbd_subcmd { EC_RGBKBD_SUBCMD_CLEAR = 1, + EC_RGBKBD_SUBCMD_DEMO = 2, + EC_RGBKBD_SUBCMD_SET_SCALE = 3, EC_RGBKBD_SUBCMD_COUNT }; +enum ec_rgbkbd_demo { + EC_RGBKBD_DEMO_OFF = 0, + EC_RGBKBD_DEMO_FLOW = 1, + EC_RGBKBD_DEMO_DOT = 2, + EC_RGBKBD_DEMO_COUNT, +}; + +BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255); + +struct ec_rgbkbd_set_scale { + uint8_t key; + struct rgb_s scale; +}; + struct ec_params_rgbkbd { uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ union { - struct rgb_s color; + struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ + uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ + struct ec_rgbkbd_set_scale set_scale; }; } __ec_align1; diff --git a/include/host_command.h b/include/host_command.h index 74f68f9891..3ab3d54351 100644 --- a/include/host_command.h +++ b/include/host_command.h @@ -273,7 +273,7 @@ struct host_command *zephyr_find_host_command(int command); static enum ec_status(routine)(struct host_cmd_handler_args *args); \ const struct host_command __keep __no_sanitize_address \ EXPAND(0x0000, command) \ - __attribute__((section(".rodata.hcmds."EXPANDSTR(0x0000, command)))) \ + __attribute__((section(".rodata.hcmds." EXPANDSTR(0x0000, command)))) \ = {routine, command, version_mask} /* diff --git a/include/mkbp_info.h b/include/mkbp_info.h new file mode 100644 index 0000000000..64daa52dce --- /dev/null +++ b/include/mkbp_info.h @@ -0,0 +1,22 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* MKBP info host command for Chrome EC */ + +#ifndef __CROS_EC_MKBP_INFO_H +#define __CROS_EC_MKBP_INFO_H + +/** + * Board specific function to set support volume buttons. + * + * Although we're able to define CONFIG_VOLUME_BUTTONS for ec volume buttons, + * some boards might need to configure this settings at run time by several + * cases such as sharing the firmware with different designs. + * + * @return 1 if volume buttons supported else 0 + */ +__override_proto int mkbp_support_volume_buttons(void); + +#endif /* __CROS_EC_MKBP_INFO_H */ diff --git a/include/power.h b/include/power.h index 547a4d93ab..6200392b95 100644 --- a/include/power.h +++ b/include/power.h @@ -8,6 +8,7 @@ #ifndef __CROS_EC_POWER_H #define __CROS_EC_POWER_H +#include "chipset.h" #include "common.h" #include "compiler.h" #include "gpio_signal.h" @@ -173,7 +174,7 @@ void power_set_state(enum power_state new_state); * * @return Current chipset power state */ -#ifdef HAS_TASK_CHIPSET +#ifdef CONFIG_AP_POWER_CONTROL enum power_state power_get_state(void); #else static inline enum power_state power_get_state(void) { @@ -204,11 +205,11 @@ enum power_state power_handle_state(enum power_state state); /** * Interrupt handler for power signal GPIOs. */ -#ifdef HAS_TASK_CHIPSET +#ifdef CONFIG_AP_POWER_CONTROL void power_signal_interrupt(enum gpio_signal signal); #else static inline void power_signal_interrupt(enum gpio_signal signal) { } -#endif /* !HAS_TASK_CHIPSET */ +#endif /* !CONFIG_AP_POWER_CONTROL */ /** * Interrupt handler for rsmrst signal GPIO. This interrupt handler should be diff --git a/include/rgb_keyboard.h b/include/rgb_keyboard.h index 58dc3c30f6..e795389225 100644 --- a/include/rgb_keyboard.h +++ b/include/rgb_keyboard.h @@ -15,12 +15,7 @@ #define RGBKBD_MAX_GCC_LEVEL 0xff #define RGBKBD_MAX_SCALE 0xff -enum rgbkbd_demo { - RGBKBD_DEMO_OFF = 0, - RGBKBD_DEMO_FLOW = 1, - RGBKBD_DEMO_DOT = 2, - RGBKBD_DEMO_COUNT -}; +#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0]) struct rgbkbd_cfg { /* Driver for LED IC */ @@ -39,18 +34,23 @@ struct rgbkbd_init { /* Global current control */ const uint8_t gcc; /* LED brightness */ - const uint8_t scale; + const struct rgb_s scale; /* Color */ const struct rgb_s color; }; -extern const struct rgbkbd_init rgbkbd_default; +/** + * Register init settings. + * + * Must be called before rgbkbd_drv->init() is called. + * + * @param setting + */ +void rgbkbd_register_init_setting(const struct rgbkbd_init *setting); struct rgbkbd { /* Static configuration */ const struct rgbkbd_cfg * const cfg; - /* Start-up settings */ - const struct rgbkbd_init * const init; /* Current state of the port */ enum rgbkbd_state state; /* Buffer containing color info for each dot. */ @@ -86,7 +86,7 @@ struct rgbkbd_drv { * @return enum ec_error_list */ int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, - uint8_t scale, uint8_t len); + struct rgb_s scale, uint8_t len); /** * Set global current control. * diff --git a/include/timer.h b/include/timer.h index 340dd8c5e8..6f9b4ea7b0 100644 --- a/include/timer.h +++ b/include/timer.h @@ -8,6 +8,13 @@ #ifndef __CROS_EC_TIMER_H #define __CROS_EC_TIMER_H +#ifndef CONFIG_ZEPHYR +#include <sys/types.h> +#else +/* Data type for POSIX style clock() implementation */ +typedef long clock_t; +#endif + #include "common.h" #include "task_id.h" @@ -27,8 +34,6 @@ typedef union { } le /* little endian words */; } timestamp_t; -/* Data type for POSIX style clock() implementation */ -typedef long clock_t; /** * Initialize the timer module. diff --git a/power/mt8186.c b/power/mt8186.c index eeb3f8a384..39fc636127 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -379,6 +379,8 @@ enum power_state power_handle_state(enum power_state state) return POWER_S3; case POWER_S3S0: + hook_notify(HOOK_CHIPSET_RESUME_INIT); + if (power_wait_mask_signals_timeout(0, IN_AP_RST, SECOND)) { chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT); return POWER_S0S3; diff --git a/test/rgb_keyboard.c b/test/rgb_keyboard.c index 9f49db2ab1..a8da437f7c 100644 --- a/test/rgb_keyboard.c +++ b/test/rgb_keyboard.c @@ -35,7 +35,6 @@ struct rgbkbd rgbkbds[] = { .col_len = RGB_GRID0_COL, .row_len = RGB_GRID0_ROW, }, - .init = &rgbkbd_default, .buf = grid0, }, [1] = { @@ -45,7 +44,6 @@ struct rgbkbd rgbkbds[] = { .col_len = RGB_GRID1_COL, .row_len = RGB_GRID1_ROW, }, - .init = &rgbkbd_default, .buf = grid1, }, }; @@ -110,7 +108,7 @@ static int test_drv_set_color(struct rgbkbd *ctx, uint8_t offset, static int test_drv_set_scale(struct rgbkbd *ctx, uint8_t offset, - uint8_t scale, uint8_t len) + struct rgb_s scale, uint8_t len) { mock_state.count_drv_set_scale++; return EC_SUCCESS; @@ -213,7 +211,7 @@ static int test_rgbkbd_startup(void) } int cc_rgb(int argc, char **argv); -extern enum rgbkbd_demo demo; +extern enum ec_rgbkbd_demo demo; static int test_rgbkbd_console_command(void) { @@ -224,8 +222,8 @@ static int test_rgbkbd_console_command(void) uint8_t offset; char *argv_demo[] = {"rgbk", "demo", "0"}; char *argv_gcc[] = {"rgbk", "100"}; - char *argv_color[] = {"rgbk", buf, "1", "2", "3"}; - char *argv_all[] = {"rgbk", "all", "1", "2", "3"}; + char *argv_color[] = {"rgbk", buf, "0x010203"}; + char *argv_all[] = {"rgbk", "all", "0x010203"}; /* Test 'rgbk demo 0'. */ before_test(); @@ -251,7 +249,7 @@ static int test_rgbkbd_console_command(void) sprintf(buf, "%d,%d", x, y); argc = ARRAY_SIZE(argv_color); zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, - "rgbk %s 1 2 3", buf); + "rgbk %s 0x010203", buf); zassert_equal(ctx->buf[offset].r, 1, "R = 1"); zassert_equal(ctx->buf[offset].g, 2, "G = 2"); zassert_equal(ctx->buf[offset].b, 3, "B = 3"); diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S index d2a467459b..0f847a2484 100644 --- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S +++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mpy121666.S @@ -178,4 +178,3 @@ fe25519_mpyWith121666_asm: pop {r4,r5,r6,r7,r15} .size fe25519_mpyWith121666_asm, .-fe25519_mpyWith121666_asm - diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S index 366713a7a3..cb272b9393 100644 --- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S +++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/mul.S @@ -1108,4 +1108,3 @@ multiply256x256_asm: pop {r4-r7,pc} bx lr .size multiply256x256_asm, .-multiply256x256_asm - diff --git a/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S b/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S index 9a3c29a0f6..73e613330f 100644 --- a/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S +++ b/third_party/unacl-curve25519/core/cortex-m0/curve25519/reduce25519.S @@ -160,4 +160,3 @@ fe25519_reduceTo256Bits_asm: pop {r4,r5,r6,r7,r15} .size fe25519_reduceTo256Bits_asm, .-fe25519_reduceTo256Bits_asm - diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 0d85c5f9e6..933f22a83c 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -571,6 +571,7 @@ CONFIG_IT83XX_SMCLK2_ON_GPC7 CONFIG_IT83XX_TUNE_CC_PHY CONFIG_IT83XX_VCC_1P8V CONFIG_IT83XX_VCC_3P3V +CONFIG_IT8XXX2_MUL_WORKAROUND CONFIG_ITE_FLASH_SUPPORT CONFIG_KEYBOARD_ASSISTANT_KEY CONFIG_KEYBOARD_BACKLIGHT @@ -731,6 +732,7 @@ CONFIG_RAM_BASE CONFIG_RAM_SIZE CONFIG_REGULATOR_IR357X CONFIG_RESTRICTED_CONSOLE_COMMANDS +CONFIG_RISCV_EXTENSION_M CONFIG_RMA_AUTH CONFIG_RMA_AUTH_USE_P256 CONFIG_RNG diff --git a/util/ectool.c b/util/ectool.c index 9d2f8f29fa..028828ebd5 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -1293,13 +1293,22 @@ int cmd_reboot_ap_on_g3(int argc, char *argv[]) static void cmd_rgbkbd_help(char *cmd) { fprintf(stderr, - " Usage1: %s <key> <RGB>\n" - " Set the color of <key> to <RGB>.\n" + " Usage1: %s <key> <RGB> [<RGB> ...]\n" + " Set the color of <key> to <RGB>. Multiple colors for\n" + " adjacent keys can be set at once.\n" "\n" " Usage2: %s clear <RGB>\n" " Set the color of all keys to <RGB>.\n" + "\n" + " Usage3: %s demo <num>\n" + " Run demo-<num>. 0: Off, 1: Flow, 2: Dot.\n" + "\n" + " Usage4: %s scale <key> <val>\n" + " Set the scale parameter of key_<key> to <val>.\n" + " <val> is a 24-bit integer where scale values are encoded\n" + " as R=23:16, G=15:8, B=7:0.\n" "\n", - cmd, cmd); + cmd, cmd, cmd, cmd); } static int cmd_rgbkbd_parse_rgb_text(const char *text, struct rgb_s *color) @@ -1361,6 +1370,8 @@ out: static int cmd_rgbkbd(int argc, char *argv[]) { + int val; + char *e; int rv = -1;; if (argc < 3) { @@ -1377,7 +1388,35 @@ static int cmd_rgbkbd(int argc, char *argv[]) return -1; rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0); - } else if (2 < argc) { + } else if (argc == 3 && !strcasecmp(argv[1], "demo")) { + /* Usage 3 */ + struct ec_params_rgbkbd p; + + val = strtol(argv[2], &e, 0); + if ((e && *e) || val >= EC_RGBKBD_DEMO_COUNT) { + fprintf(stderr, "Invalid demo id: %s\n", argv[2]); + return -1; + } + p.subcmd = EC_RGBKBD_SUBCMD_DEMO; + p.demo = val; + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0); + } else if (argc == 4 && !strcasecmp(argv[1], "scale")) { + /* Usage 4 */ + struct ec_params_rgbkbd p; + + val = strtol(argv[2], &e, 0); + if ((e && *e) || val > EC_RGBKBD_MAX_KEY_COUNT) { + fprintf(stderr, "Invalid key number: %s\n", argv[2]); + return -1; + } + p.set_scale.key = val; + if (cmd_rgbkbd_parse_rgb_text(argv[3], &p.set_scale.scale)) { + fprintf(stderr, "Invalid scale value: %s\n", argv[3]); + return -1; + } + p.subcmd = EC_RGBKBD_SUBCMD_SET_SCALE; + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0); + } else { /* Usage 1 */ rv = cmd_rgbkbd_set_color(argc, argv); } diff --git a/util/fptool.py b/util/fptool.py index 28c377360c..5d73302bbc 100755 --- a/util/fptool.py +++ b/util/fptool.py @@ -3,7 +3,7 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -"""A tool to manage the fingerprint system on Chrome OS.""" +"""A tool to manage the fingerprint system on ChromeOS.""" import argparse import os diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index cf2a9645ce..451406c8b3 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -533,6 +533,8 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MATH_UTIL "${PLATFORM_EC}/common/math_util.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY "${PLATFORM_EC}/driver/led/max695x.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DRIVER_TLC59116F + "${PLATFORM_EC}/driver/led/tlc59116f.c") zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_HOST_SLEEP "${PLATFORM_EC}/power/host_sleep.c") # Switch to ec_shim library for all Zephyr sources diff --git a/zephyr/Kconfig.ap_power b/zephyr/Kconfig.ap_power index 3db5a1fef8..03c92759f0 100644 --- a/zephyr/Kconfig.ap_power +++ b/zephyr/Kconfig.ap_power @@ -2,6 +2,15 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. +config AP_POWER_CONTROL + bool + default y if PLATFORM_EC_POWERSEQ || AP_PWRSEQ + help + Whether the EC has control over AP power states. + + This is automatically enabled if an implementation of AP power + sequencing is enabled. + menuconfig PLATFORM_EC_BOOT_AP_POWER_REQUIREMENTS bool "Power requirements to boot AP" default y diff --git a/zephyr/Kconfig.cbi b/zephyr/Kconfig.cbi index 0ab5025a97..962392e56c 100644 --- a/zephyr/Kconfig.cbi +++ b/zephyr/Kconfig.cbi @@ -18,7 +18,6 @@ config PLATFORM_EC_EEPROM_CBI_WP Define this if the EC can independently set the CBI EEPROM WP signal. The accompanying hardware must ensure that the CBI WP gets latched and is only reset when EC_RST_ODL is asserted. - select PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK choice PLATFORM_EC_CBI_STORAGE_TYPE prompt "Select CBI storage Type" diff --git a/zephyr/Kconfig.defaults b/zephyr/Kconfig.defaults index faea48adef..a92971b3c7 100644 --- a/zephyr/Kconfig.defaults +++ b/zephyr/Kconfig.defaults @@ -21,7 +21,4 @@ config THREAD_MAX_NAME_LEN config SHELL_PROMPT_UART default "ec:~$ " -config LEGACY_INCLUDE_PATH - default n - orsource "Kconfig.defaults-$(ARCH)" diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header index e5c137b99e..931d7dbaf1 100644 --- a/zephyr/Kconfig.header +++ b/zephyr/Kconfig.header @@ -16,6 +16,7 @@ config PLATFORM_EC_RO_HEADER config PLATFORM_EC_RO_HEADER_OFFSET hex "Offset in memory for the location of the header" + default 0x1000 if SOC_SERIES_MEC172X default 0x0 help The offset (in bytes) of the header relative to the start address of @@ -24,7 +25,6 @@ config PLATFORM_EC_RO_HEADER_OFFSET config PLATFORM_EC_RO_HEADER_SIZE hex "Size of the RO header" default 0x40 if SOC_FAMILY_NPCX - default 0x140 if SOC_SERIES_MEC172X default 0x0 help The size of the RO header in bytes. This values should come from the diff --git a/zephyr/Kconfig.led b/zephyr/Kconfig.led index 785aa64f89..03f2ebed56 100644 --- a/zephyr/Kconfig.led +++ b/zephyr/Kconfig.led @@ -3,6 +3,7 @@ # found in the LICENSE file. menuconfig PLATFORM_EC_LED_COMMON + depends on !PLATFORM_EC_LED_DT bool "LED Support" help Enable the common LED module supporting automatic control of the diff --git a/zephyr/Kconfig.motionsense b/zephyr/Kconfig.motionsense index f76e11dbc0..abfdacc5be 100644 --- a/zephyr/Kconfig.motionsense +++ b/zephyr/Kconfig.motionsense @@ -61,6 +61,12 @@ config PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS # if PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA #endif # PLATFORM_EC_MOTION_FILL_LPC_SENSE_DATA +config PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ + int "Maximal EC sampling rate" + default 250000 + help + Lower this limit for slower EC (in mHz). + config PLATFORM_EC_ALS bool "Ambient Light Sensor(ALS)" help diff --git a/zephyr/Kconfig.pd_vbus_detection b/zephyr/Kconfig.pd_vbus_detection index f3f410c9dc..019eca654a 100644 --- a/zephyr/Kconfig.pd_vbus_detection +++ b/zephyr/Kconfig.pd_vbus_detection @@ -5,10 +5,6 @@ if PLATFORM_EC_USBC if PLATFORM_EC_USB_POWER_DELIVERY -choice PLATFORM_EC_USB_PD_VBUS_DETECTION_TYPE - prompt "Select the method to detect VBUS" - default PLATFORM_EC_USB_PD_VBUS_DETECT_NONE - config PLATFORM_EC_USB_PD_VBUS_DETECT_NONE bool "No way to detect VBUS" help @@ -32,7 +28,5 @@ config PLATFORM_EC_USB_PD_VBUS_DETECT_PPC Choose this option if the Power-Path Controller (PPC) can detect the presence of VBUS -endchoice # PLATFORM_EC_USB_PD_VBUS_DETECTION_TYPE - endif # PLATFORM_EC_USB_POWER_DELIVERY endif # PLATFORM_EC_USBC diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq index cee5be53a4..f0db496082 100644 --- a/zephyr/Kconfig.powerseq +++ b/zephyr/Kconfig.powerseq @@ -5,6 +5,7 @@ menuconfig PLATFORM_EC_POWERSEQ bool "Power sequencing" depends on AP + depends on !AP_PWRSEQ select HAS_TASK_CHIPSET help Enable shimming the platform/ec AP power sequencing code. This @@ -15,6 +16,14 @@ menuconfig PLATFORM_EC_POWERSEQ if PLATFORM_EC_POWERSEQ +config PLATFORM_EC_POWERSEQ_S0IX + bool "Enable S0ix sleep states" + select PLATFORM_EC_POWERSEQ_HOST_SLEEP + help + Enable the CONFIG_POWER_S0IX platform/ec configuration + option, Intel's low-power idle sleep state, also known as + "modern sleep". + config PLATFORM_EC_POWERSEQ_HOST_SLEEP bool "Track host sleep states" help @@ -120,14 +129,6 @@ config PLATFORM_EC_POWERSEQ_RTC_RESET gpio_map.h, which can be used to reset the AP's RTC when set high. -config PLATFORM_EC_POWERSEQ_S0IX - bool "Enable S0ix sleep states" - select PLATFORM_EC_POWERSEQ_HOST_SLEEP - help - Enable the CONFIG_POWER_S0IX platform/ec configuration - option, Intel's low-power idle sleep state, also known as - "modern sleep". - config PLATFORM_EC_POWERSEQ_S4 bool "Advertise S4 residency" depends on PLATFORM_EC_ESPI_VW_SLP_S5 diff --git a/zephyr/Kconfig.watchdog b/zephyr/Kconfig.watchdog index e1a51c29eb..57d93d7c39 100644 --- a/zephyr/Kconfig.watchdog +++ b/zephyr/Kconfig.watchdog @@ -14,7 +14,7 @@ config PLATFORM_EC_WATCHDOG_PERIOD_MS config PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS int "Leading time of the watchdog warning timer in ms" default 500 - depends on !WDT_NPCX && !WDT_ITE_IT8XXX2 && !WDT_XEC + depends on !WDT_NPCX && !WDT_ITE_IT8XXX2 help Set the leading time of the watchdog warning timer. Chromium EC system uses an auxiliary timer to handle the system warning event. The diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x index 998116c243..9e37b6a534 100644 --- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x @@ -20,16 +20,18 @@ if SOC_SERIES_MEC172X config CROS_EC_PROGRAM_MEMORY_BASE default 0xc0000 +# Data SRAM base config CROS_EC_RAM_BASE - default 0xc0000 + default 0x118000 -# Data size: 64K - 2K, top 1KB is persistent +# Total data SRAM size config CROS_EC_DATA_RAM_SIZE - default 0x00F800 + default 0x010000 -# Code + Data: Top 1KB is peristent +# Top 2KB reserved for PUF leaving 62KB +# 61KB for data + 1KB persistent across chip reset. config CROS_EC_RAM_SIZE - default 0x067800 + default 0x00f800 config FLASH_SIZE default 512 @@ -37,8 +39,9 @@ config FLASH_SIZE config CROS_EC_RO_MEM_OFF default 0x0 +# was 0x40000 config CROS_EC_RO_SIZE - default 0x40000 + default 0x3F000 # RW firmware in program memory - Identical to RO, only one image loaded at a # time. diff --git a/zephyr/app/ec/soc/Kconfig b/zephyr/app/ec/soc/Kconfig index 7789ad7866..9d3c851a36 100644 --- a/zephyr/app/ec/soc/Kconfig +++ b/zephyr/app/ec/soc/Kconfig @@ -34,7 +34,7 @@ config AP_X86_INTEL_ADL config AP_X86_AMD bool "AP is an AMD chipset" - select AP_x86 + select AP_X86 help The application processor is a product of AMD. diff --git a/zephyr/boards/arm/mec1727/mec1727.dts b/zephyr/boards/arm/mec1727/mec1727.dts index c88e61b692..d371f8a2dc 100644 --- a/zephyr/boards/arm/mec1727/mec1727.dts +++ b/zephyr/boards/arm/mec1727/mec1727.dts @@ -8,8 +8,7 @@ #include <cros/microchip/mec1727.dtsi> #include <cros/thermistor/thermistor.dtsi> #include <dt-bindings/gpio_defines.h> -#include <microchip/mec172xnsz.dtsi> -#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi> +#include <microchip/mec1727nsz.dtsi> / { model = "MEC1727"; diff --git a/zephyr/boards/arm/npcx9/npcx9.dtsi b/zephyr/boards/arm/npcx9/npcx9.dtsi index 4b43bda08a..27ece8cdd6 100644 --- a/zephyr/boards/arm/npcx9/npcx9.dtsi +++ b/zephyr/boards/arm/npcx9/npcx9.dtsi @@ -56,32 +56,3 @@ pinmux-gpio; }; }; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&ksi0_gp31 - &ksi1_gp30 - &ksi2_gp27 - &ksi3_gp26 - &ksi4_gp25 - &ksi5_gp24 - &ksi6_gp23 - &ksi7_gp22 - &kso00_gp21 - &kso01_gp20 - &kso03_gp16 - &kso04_gp15 - &kso05_gp14 - &kso06_gp13 - &kso07_gp12 - &kso08_gp11 - &kso09_gp10 - &kso10_gp07 - &kso11_gp06 - &kso12_gp05 - &kso13_gp04 - &kso14_gp82 - >; - pinctrl-names = "default"; -}; diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py index 1a8ce32469..21767d635a 100755 --- a/zephyr/firmware_builder.py +++ b/zephyr/firmware_builder.py @@ -193,7 +193,7 @@ def test(opts): cmd = [ '/usr/bin/lcov', '-o', - build_dir / 'fullpaths.info', + build_dir / 'lcov.info', '--rc', 'lcov_branch_coverage=1', '-a', @@ -211,18 +211,6 @@ def test(opts): cwd=pathlib.Path(__file__).parent, check=True, stdout=subprocess.PIPE, universal_newlines=True).stdout _extract_lcov_summary('EC_ZEPHYR_TESTS', metrics, output) - # Make filenames relative to platform/ec - cmd = ['sed', '-e', 's|^SF:.*/platform/ec/|SF:|'] - with open(build_dir / 'fullpaths.info') as infile, open( - build_dir / 'lcov.info', 'w' - ) as outfile: - subprocess.run( - cmd, - cwd=pathlib.Path(__file__).parent, - stdin=infile, - stdout=outfile, - check=True, - ) with open(opts.metrics, 'w') as file: file.write(json_format.MessageToJson(metrics)) diff --git a/zephyr/include/cros/microchip/mec1727.dtsi b/zephyr/include/cros/microchip/mec1727.dtsi index b388f456d2..340cff1956 100644 --- a/zephyr/include/cros/microchip/mec1727.dtsi +++ b/zephyr/include/cros/microchip/mec1727.dtsi @@ -5,13 +5,76 @@ /dts-v1/; -#include <cros/microchip/mec172x.dtsi> +#include <cros/binman.dtsi> +#include <microchip/mec1727nsz.dtsi> / { + chosen { + cros-ec,adc = &adc0; + cros-ec,bbram = &bbram; + cros-ec,espi = &espi0; + cros-ec,flash = &flash1; + cros-ec,flash-controller = &fiu0; + cros-ec,raw-kb = &cros_kb_raw; + cros-ec,watchdog = &wdog; + cros,rtc = &crtc; + }; - soc { + named-bbram-regions { + compatible = "named-bbram-regions"; + scratchpad { + offset = <0x00>; + size = <0x04>; + }; + saved-reset-flags { + offset = <0x04>; + size = <0x04>; + }; + wake { + offset = <0x08>; + size = <0x04>; + }; + pd0 { + offset = <0x0c>; + size = <0x01>; + }; + pd1 { + offset = <0x0d>; + size = <0x01>; + }; + try_slot { + offset = <0x0e>; + size = <0x01>; + }; + pd2 { + offset = <0x0f>; + size = <0x01>; + }; + ramlog { + offset = <0x20>; + size = <0x01>; + }; + panic_flags { + offset = <0x23>; + size = <0x01>; + }; + panic_bkup { + offset = <0x24>; + size = <0x1c>; + }; + lct_time { + offset = <0x40>; + size = <0x04>; + }; + ec_img_load { + offset = <0x44>; + size = <0x01>; + }; }; + fiu0: cros-flash { + compatible = "microchip,xec-cros-flash"; + label = "INTERNAL_FLASH"; + }; }; - diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h index 0c74f4b4ce..4988c48576 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h @@ -347,7 +347,7 @@ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data, * @param type Type of message * @param data_obj Pointer to array of data objects * @param data_obj_num Number of data objects - * @param delay Optional delay + * @param delay Optional delay in milliseconds * * @return TCPCI_EMUL_TX_SUCCESS on success * @return TCPCI_EMUL_TX_FAILED when TCPCI is configured to not handle diff --git a/zephyr/projects/brya/keyboard.dts b/zephyr/projects/brya/keyboard.dts index 88b8ba8c65..4f06764810 100644 --- a/zephyr/projects/brya/keyboard.dts +++ b/zephyr/projects/brya/keyboard.dts @@ -16,3 +16,31 @@ pinctrl-0 = <&pwm3_gp80>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/prj.conf b/zephyr/projects/brya/prj.conf index 931053c5f2..7ce897ae5f 100644 --- a/zephyr/projects/brya/prj.conf +++ b/zephyr/projects/brya/prj.conf @@ -92,7 +92,7 @@ CONFIG_PLATFORM_EC_HIBERNATE_PSL=y # MKBP event CONFIG_PLATFORM_EC_MKBP_EVENT=y CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y -CONFIG_PLATFORM_EC_MKBP_USE_HOST_EVENT=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y # PMIC CONFIG_PLATFORM_EC_PMIC=y diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index c75418f294..83ad865cb1 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -58,6 +58,7 @@ register_corsola_project( here / "interrupts_kingler.dts", here / "cbi_eeprom.dts", here / "gpio_kingler.dts", + here / "npcx_keyboard.dts", here / "led_kingler.dts", here / "motionsense_kingler.dts", here / "usbc_kingler.dts", @@ -77,8 +78,10 @@ register_corsola_project( here / "interrupts_kingler.dts", here / "cbi_eeprom.dts", here / "gpio_steelix.dts", + here / "npcx_keyboard.dts", here / "led_steelix.dts", here / "motionsense_kingler.dts", + here / "motionsense_steelix.dts", here / "usba_steelix.dts", here / "usbc_kingler.dts", here / "default_gpio_pinctrl_kingler.dts", diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts index 6ef6f02e03..0199f985fa 100644 --- a/zephyr/projects/corsola/gpio_kingler.dts +++ b/zephyr/projects/corsola/gpio_kingler.dts @@ -91,7 +91,7 @@ lid_accel_int_l { gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; - tablet_mode_l { + gpio_tablet_mode_l: tablet_mode_l { gpios = <&gpiob 2 GPIO_INPUT>; enum-name = "GPIO_TABLET_MODE_L"; }; diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts index 29c1bbe75a..3e0375564f 100644 --- a/zephyr/projects/corsola/gpio_steelix.dts +++ b/zephyr/projects/corsola/gpio_steelix.dts @@ -98,7 +98,7 @@ lid_accel_int_l { gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; - tablet_mode_l { + gpio_tablet_mode_l: tablet_mode_l { gpios = <&gpiob 2 GPIO_INPUT>; enum-name = "GPIO_TABLET_MODE_L"; }; diff --git a/zephyr/projects/corsola/i2c_kingler.dts b/zephyr/projects/corsola/i2c_kingler.dts index 843367668e..c832e55d2e 100644 --- a/zephyr/projects/corsola/i2c_kingler.dts +++ b/zephyr/projects/corsola/i2c_kingler.dts @@ -17,6 +17,7 @@ }; i2c_usb_c0: usb-c0 { i2c-port = <&i2c1_0>; + remote-port = <7>; enum-name = "I2C_PORT_USB_C0"; }; i2c_usb_c1: usb-c1 { diff --git a/zephyr/projects/corsola/interrupts_kingler.dts b/zephyr/projects/corsola/interrupts_kingler.dts index ac7da13e75..b33251624d 100644 --- a/zephyr/projects/corsola/interrupts_kingler.dts +++ b/zephyr/projects/corsola/interrupts_kingler.dts @@ -100,5 +100,10 @@ flags = <GPIO_INT_EDGE_FALLING>; handler = "bmi3xx_interrupt"; }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; }; }; diff --git a/zephyr/projects/corsola/interrupts_krabby.dts b/zephyr/projects/corsola/interrupts_krabby.dts index ddc9639d2b..900ce1611e 100644 --- a/zephyr/projects/corsola/interrupts_krabby.dts +++ b/zephyr/projects/corsola/interrupts_krabby.dts @@ -61,7 +61,7 @@ flags = <GPIO_INT_EDGE_FALLING>; handler = "icm42607_interrupt"; }; - int_accel: accel { + int_lid_imu: lid_imu { irq-pin = <&lid_accel_int_l>; flags = <GPIO_INT_EDGE_FALLING>; handler = "lis2dw12_interrupt"; @@ -91,11 +91,6 @@ flags = <GPIO_INT_EDGE_BOTH>; handler = "x_ec_interrupt"; }; - int_base_imu: base_imu { - irq-pin = <&base_imu_int_l>; - flags = <GPIO_INT_EDGE_FALLING>; - handler = "icm42607_interrupt"; - }; int_usb_c0_ppc_bc12: usb_c0_ppc_bc12 { irq-pin = <&usb_c0_ppc_bc12_int_odl>; flags = <GPIO_INT_EDGE_FALLING>; diff --git a/zephyr/projects/corsola/led_steelix.dts b/zephyr/projects/corsola/led_steelix.dts index 56a54862e6..31d17958d4 100644 --- a/zephyr/projects/corsola/led_steelix.dts +++ b/zephyr/projects/corsola/led_steelix.dts @@ -6,31 +6,14 @@ / { pwmleds { compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED - &pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED - &pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + led_battery_red: ec_led1_odl { + pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <100>; - - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-amber = <100 20 0>; - - brightness-range = <255 255 0 0 0 255>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; + led_battery_green: ec_led2_odl { + pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + led_power_white: ec_led3_odl { + pwms = <&pwm4 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; }; }; }; @@ -59,14 +42,14 @@ pinctrl-names = "default"; }; -/* Blue LED */ -&pwm2_gpc4 { +/* White LED */ +&pwm4_gpb6 { drive-open-drain; }; -&pwm2 { +&pwm4 { status = "okay"; clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; + pinctrl-0 = <&pwm4_gpb6>; pinctrl-names = "default"; }; diff --git a/zephyr/projects/corsola/motionsense_krabby.dts b/zephyr/projects/corsola/motionsense_krabby.dts index 730f1a938e..d369db460a 100644 --- a/zephyr/projects/corsola/motionsense_krabby.dts +++ b/zephyr/projects/corsola/motionsense_krabby.dts @@ -150,8 +150,6 @@ * list of GPIO interrupts that have to * be enabled at initial stage */ - sensor-irqs = <&int_base_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; + sensor-irqs = <&int_base_imu &int_lid_imu>; }; }; diff --git a/zephyr/projects/corsola/motionsense_steelix.dts b/zephyr/projects/corsola/motionsense_steelix.dts new file mode 100644 index 0000000000..70aa3679fb --- /dev/null +++ b/zephyr/projects/corsola/motionsense_steelix.dts @@ -0,0 +1,17 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&lid_rot_ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; +}; + +&base_rot_ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; +}; + diff --git a/zephyr/projects/corsola/npcx_keyboard.dts b/zephyr/projects/corsola/npcx_keyboard.dts new file mode 100644 index 0000000000..d3fd354b8f --- /dev/null +++ b/zephyr/projects/corsola/npcx_keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf index b9d07a7227..b26c01461e 100644 --- a/zephyr/projects/corsola/prj.conf +++ b/zephyr/projects/corsola/prj.conf @@ -15,7 +15,6 @@ CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y # MKBP -CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y CONFIG_PLATFORM_EC_MKBP_EVENT=y CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y @@ -30,6 +29,7 @@ CONFIG_PLATFORM_EC_USB_PD_USB4=n CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n # Power Seq +CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y diff --git a/zephyr/projects/corsola/prj_kingler.conf b/zephyr/projects/corsola/prj_kingler.conf index 191a104cde..525d94a886 100644 --- a/zephyr/projects/corsola/prj_kingler.conf +++ b/zephyr/projects/corsola/prj_kingler.conf @@ -74,9 +74,6 @@ CONFIG_PLATFORM_EC_MATH_UTIL=y CONFIG_AP=y CONFIG_AP_ARM_MTK_MT8186=y CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y - -# Treat 2nd reset from H1 as Power-On -CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y CONFIG_PLATFORM_EC_POWERSEQ=y CONFIG_PLATFORM_EC_POWERSEQ_S4=n CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n @@ -93,11 +90,14 @@ CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y CONFIG_PLATFORM_EC_ACCEL_FIFO=y CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y CONFIG_PLATFORM_EC_LID_ANGLE=y CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y CONFIG_PLATFORM_EC_LID_SWITCH=y CONFIG_PLATFORM_EC_MOTIONSENSE=y CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y # USBA CONFIG_PLATFORM_EC_USBA=y @@ -122,6 +122,7 @@ CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y diff --git a/zephyr/projects/corsola/prj_steelix.conf b/zephyr/projects/corsola/prj_steelix.conf index 5354381f9b..48971c9ed4 100644 --- a/zephyr/projects/corsola/prj_steelix.conf +++ b/zephyr/projects/corsola/prj_steelix.conf @@ -4,4 +4,10 @@ # Variant config CONFIG_BOARD_KINGLER=n -CONFIG_BOARD_STEELIX=y
\ No newline at end of file +CONFIG_BOARD_STEELIX=y + +# steelix only use D2, drop the workaround config for H1 +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n + +# LED +CONFIG_PLATFORM_EC_LED_PWM=n diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c index a44f961441..2d2e1431a1 100644 --- a/zephyr/projects/corsola/src/kingler/led_steelix.c +++ b/zephyr/projects/corsola/src/kingler/led_steelix.c @@ -4,11 +4,26 @@ * * Battery LED control for Steelix */ + +#include <zephyr/drivers/pwm.h> +#include <zephyr/logging/log.h> + +#include "board_led.h" #include "common.h" -#include "ec_commands.h" #include "led_common.h" #include "led_onoff_states.h" -#include "led_pwm.h" +#include "util.h" + +LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR); + +#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(100) + +static const struct board_led_pwm_dt_channel board_led_battery_red = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_red)); +static const struct board_led_pwm_dt_channel board_led_battery_green = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_green)); +static const struct board_led_pwm_dt_channel board_led_power_white = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white)); __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; @@ -18,6 +33,7 @@ __override struct led_descriptor [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, @@ -26,20 +42,110 @@ __override struct led_descriptor {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, }; +__override const struct led_descriptor + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, + [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, + {LED_OFF, 0.5 * LED_ONE_SEC} }, + [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, + {LED_OFF, 0.5 * LED_ONE_SEC} }, + [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, +}; + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED, +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, + int percent) +{ + uint32_t pulse_ns; + int rv; + + if (!device_is_ready(ch->dev)) { + LOG_ERR("PWM device %s not ready", ch->dev->name); + return; + } + + pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); + + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", + ch->dev->name, percent, pulse_ns); + + rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, + ch->flags); + if (rv) { + LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv); + } +} + __override void led_set_color_battery(enum ec_led_colors color) { switch (color) { case EC_LED_COLOR_RED: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + board_led_pwm_set_duty(&board_led_battery_red, 100); + board_led_pwm_set_duty(&board_led_battery_green, 0); break; case EC_LED_COLOR_GREEN: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_GREEN); + board_led_pwm_set_duty(&board_led_battery_red, 0); + board_led_pwm_set_duty(&board_led_battery_green, 100); break; case EC_LED_COLOR_AMBER: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + board_led_pwm_set_duty(&board_led_battery_red, 100); + board_led_pwm_set_duty(&board_led_battery_green, 20); break; default: /* LED_OFF and other unsupported colors */ - set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + board_led_pwm_set_duty(&board_led_battery_red, 0); + board_led_pwm_set_duty(&board_led_battery_green, 0); break; } } + +__override void led_set_color_power(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_WHITE: + board_led_pwm_set_duty(&board_led_power_white, 100); + break; + default: + board_led_pwm_set_duty(&board_led_power_white, 0); + break; + } +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + brightness_range[EC_LED_COLOR_RED] = 1; + brightness_range[EC_LED_COLOR_GREEN] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + } else if (led_id == EC_LED_ID_POWER_LED) { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + if (brightness[EC_LED_COLOR_RED] != 0) { + led_set_color_battery(EC_LED_COLOR_RED); + } else if (brightness[EC_LED_COLOR_GREEN] != 0) { + led_set_color_battery(EC_LED_COLOR_GREEN); + } else if (brightness[EC_LED_COLOR_AMBER] != 0) { + led_set_color_battery(EC_LED_COLOR_AMBER); + } else { + led_set_color_battery(LED_OFF); + } + } else if (led_id == EC_LED_ID_POWER_LED) { + if (brightness[EC_LED_COLOR_WHITE] != 0) { + led_set_color_power(EC_LED_COLOR_WHITE); + } else { + led_set_color_power(LED_OFF); + } + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index d710e36187..42aa0a31d6 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -192,12 +192,6 @@ __override int board_rt1718s_init(int port) RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); - /* Turn on SBU switch */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, - RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | - RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | - RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, - 0xFF)); /* Trigger GPIO 1/2 change when FRS signal received */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3, RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | diff --git a/zephyr/projects/corsola/src/usb_pd_policy.c b/zephyr/projects/corsola/src/usb_pd_policy.c index cdcb49ff2e..c9015de776 100644 --- a/zephyr/projects/corsola/src/usb_pd_policy.c +++ b/zephyr/projects/corsola/src/usb_pd_policy.c @@ -8,6 +8,7 @@ #include "chipset.h" #include "hooks.h" #include "timer.h" +#include "typec_control.h" #include "usb_dp_alt_mode.h" #include "usb_mux.h" #include "usb_pd.h" @@ -112,6 +113,8 @@ __override void svdm_dp_post_config(int port) { mux_state_t mux_mode = svdm_dp_get_mux_mode(port); + typec_set_sbu(port, true); + /* * Prior to post-config, the mux will be reset to safe mode, and this * will break mux config and aux path config we did in the first DP diff --git a/zephyr/projects/herobrine/BUILD.py b/zephyr/projects/herobrine/BUILD.py index dd3eed1562..2a15441c55 100644 --- a/zephyr/projects/herobrine/BUILD.py +++ b/zephyr/projects/herobrine/BUILD.py @@ -51,6 +51,8 @@ register_variant( extra_dts_overlays=[ here / "battery_hoglin.dts", here / "gpio_hoglin.dts", + here / "led_pins_hoglin.dts", + here / "led_policy_hoglin.dts", here / "motionsense_hoglin.dts", here / "switchcap_hoglin.dts", here / "usbc_hoglin.dts", @@ -64,8 +66,8 @@ register_variant( extra_dts_overlays=[ here / "battery_villager.dts", here / "gpio_villager.dts", - here / "gpio_led_villager.dts", - here / "led_villager.dts", + here / "led_pins_villager.dts", + here / "led_policy_villager.dts", here / "motionsense_villager.dts", here / "switchcap.dts", here / "usbc_villager.dts", diff --git a/zephyr/projects/herobrine/CMakeLists.txt b/zephyr/projects/herobrine/CMakeLists.txt index 64102e951c..537fa5ef68 100644 --- a/zephyr/projects/herobrine/CMakeLists.txt +++ b/zephyr/projects/herobrine/CMakeLists.txt @@ -12,8 +12,6 @@ cros_ec_library_include_directories(include) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c" "src/usb_pd_policy.c") -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON - "src/led.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/i2c.c") diff --git a/zephyr/projects/herobrine/gpio_hoglin.dts b/zephyr/projects/herobrine/gpio_hoglin.dts index 6f2f05eacf..f0b8a43586 100644 --- a/zephyr/projects/herobrine/gpio_hoglin.dts +++ b/zephyr/projects/herobrine/gpio_hoglin.dts @@ -174,16 +174,18 @@ gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; enum-name = "GPIO_USB_C1_FRS_EN"; }; - gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 { + #led-pin-cells = <1>; gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; }; - gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 { + gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 { + #led-pin-cells = <1>; gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; }; - gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 { + gpio_ec_chg_led_y_c1: ec_chg_led_b_c1 { gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; }; - gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 { + gpio_ec_chg_led_w_c1: ec_chg_led_r_c1 { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; }; ap_ec_spi_mosi { diff --git a/zephyr/projects/herobrine/keyboard.dts b/zephyr/projects/herobrine/keyboard.dts index 8c5f306192..202b61bb4f 100644 --- a/zephyr/projects/herobrine/keyboard.dts +++ b/zephyr/projects/herobrine/keyboard.dts @@ -17,3 +17,31 @@ pinctrl-0 = <&pwm3_gp80>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/herobrine/led_pins_hoglin.dts b/zephyr/projects/herobrine/led_pins_hoglin.dts new file mode 100644 index 0000000000..8603b4e61d --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_hoglin.dts @@ -0,0 +1,33 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_b_c0 0>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_b_c0 1>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_red: color-red { + led-color = "LED_RED"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_RED"; + led-pins = <&gpio_ec_chg_led_b_c0 0>, + <&gpio_ec_chg_led_r_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/gpio_led_villager.dts b/zephyr/projects/herobrine/led_pins_villager.dts index 67a1d1926c..67a1d1926c 100644 --- a/zephyr/projects/herobrine/gpio_led_villager.dts +++ b/zephyr/projects/herobrine/led_pins_villager.dts diff --git a/zephyr/projects/herobrine/led_policy_hoglin.dts b/zephyr/projects/herobrine/led_policy_hoglin.dts new file mode 100644 index 0000000000..80ee9f7829 --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_hoglin.dts @@ -0,0 +1,97 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + led-colors { + compatible = "cros-ec,led-colors"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Blue 1 sec, off 3 sec */ + color-0 { + led-color = <&color_blue>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Red 1 sec, off 1 sec */ + color-0 { + led-color = <&color_red>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_red>; + }; + }; + + power-state-idle-forced { + charge-state = "PWR_STATE_IDLE"; + extra-flag = "LED_CHFLAG_FORCE_IDLE"; + + /* Red 2 sec, Blue 2 sec */ + color-0 { + led-color = <&color_red>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_blue>; + period-ms = <2000>; + }; + }; + + power-state-idle-default { + charge-state = "PWR_STATE_IDLE"; + extra-flag = "LED_CHFLAG_DEFAULT"; + + color-0 { + led-color = <&color_red>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_villager.dts b/zephyr/projects/herobrine/led_policy_villager.dts index 3bdf0147d7..46b0193e61 100644 --- a/zephyr/projects/herobrine/led_villager.dts +++ b/zephyr/projects/herobrine/led_policy_villager.dts @@ -1,3 +1,8 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + / { led-colors { compatible = "cros-ec,led-colors"; diff --git a/zephyr/projects/herobrine/prj.conf b/zephyr/projects/herobrine/prj.conf index 679c5c2424..e16d5c7899 100644 --- a/zephyr/projects/herobrine/prj.conf +++ b/zephyr/projects/herobrine/prj.conf @@ -30,7 +30,8 @@ CONFIG_SHELL_TAB_AUTOCOMPLETION=y CONFIG_PLATFORM_EC_HIBERNATE_PSL=y # LED -CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y # PWM CONFIG_PWM=y @@ -88,7 +89,7 @@ CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2 -CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=12500 CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y CONFIG_PLATFORM_EC_CHARGER_PSYS=y CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y @@ -148,6 +149,7 @@ CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y CONFIG_PLATFORM_EC_TABLET_MODE=y CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 # Sensor Drivers CONFIG_PLATFORM_EC_ACCEL_BMA255=y diff --git a/zephyr/projects/herobrine/prj_herobrine.conf b/zephyr/projects/herobrine/prj_herobrine.conf index c91071d844..3c7eddbae6 100644 --- a/zephyr/projects/herobrine/prj_herobrine.conf +++ b/zephyr/projects/herobrine/prj_herobrine.conf @@ -5,10 +5,6 @@ # Herobrine-NPCX9 reference-board-specific Kconfig settings. CONFIG_BOARD_HEROBRINE=y -# LED -CONFIG_PLATFORM_EC_LED_COMMON=n -CONFIG_PLATFORM_EC_LED_DT=y - # Sensors CONFIG_PLATFORM_EC_ALS=y diff --git a/zephyr/projects/herobrine/prj_hoglin.conf b/zephyr/projects/herobrine/prj_hoglin.conf index f68d139b78..370e942f45 100644 --- a/zephyr/projects/herobrine/prj_hoglin.conf +++ b/zephyr/projects/herobrine/prj_hoglin.conf @@ -13,4 +13,3 @@ CONFIG_PLATFORM_EC_ALS=y # Sensor Drivers CONFIG_PLATFORM_EC_ALS_TCS3400=y CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y - diff --git a/zephyr/projects/herobrine/prj_villager.conf b/zephyr/projects/herobrine/prj_villager.conf index a63e003788..34c366a36f 100644 --- a/zephyr/projects/herobrine/prj_villager.conf +++ b/zephyr/projects/herobrine/prj_villager.conf @@ -5,7 +5,4 @@ # Villager board-specific Kconfig settings. CONFIG_BOARD_VILLAGER=y -# LED -CONFIG_PLATFORM_EC_LED_DT=y -CONFIG_PLATFORM_EC_LED_COMMON=n CONFIG_PLATFORM_EC_ACCEL_KX022=y diff --git a/zephyr/projects/herobrine/src/led.c b/zephyr/projects/herobrine/src/led.c deleted file mode 100644 index ac6092884d..0000000000 --- a/zephyr/projects/herobrine/src/led.c +++ /dev/null @@ -1,175 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Power and battery LED control. - */ - -#include <zephyr/drivers/gpio.h> - -#include "battery.h" -#include "charge_manager.h" -#include "charge_state.h" -#include "chipset.h" -#include "ec_commands.h" -#include "hooks.h" -#include "host_command.h" -#include "led_common.h" -#include "system.h" -#include "util.h" - -#define BAT_LED_ON 1 -#define BAT_LED_OFF 0 - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_RIGHT_LED, -#ifndef CONFIG_BOARD_HOGLIN - EC_LED_ID_LEFT_LED, -#endif -}; - -const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - -enum led_color { - LED_OFF = 0, - LED_AMBER, - LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ -}; - -static void side_led_set_color(int port, enum led_color color) -{ - gpio_pin_set_dt(port ? - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_y_c1) : - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_y_c0), - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); - gpio_pin_set_dt(port ? - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_w_c1) : - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_w_c0), - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); -} - -void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -{ -#ifndef CONFIG_BOARD_HOGLIN - brightness_range[EC_LED_COLOR_AMBER] = 1; - brightness_range[EC_LED_COLOR_WHITE] = 1; -#else - brightness_range[EC_LED_COLOR_RED] = 1; - brightness_range[EC_LED_COLOR_BLUE] = 1; -#endif -} - -int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) -{ - int port; - - switch (led_id) { - case EC_LED_ID_RIGHT_LED: - port = 0; - break; - case EC_LED_ID_LEFT_LED: - port = 1; - break; - default: - return EC_ERROR_PARAM1; - } - - if (brightness[EC_LED_COLOR_WHITE] != 0) - side_led_set_color(port, LED_WHITE); - else if (brightness[EC_LED_COLOR_AMBER] != 0) - side_led_set_color(port, LED_AMBER); - else - side_led_set_color(port, LED_OFF); - - return EC_SUCCESS; -} - -/* - * Set active charge port color to the parameter, turn off all others. - * If no port is active (-1), turn off all LEDs. - */ -static void set_active_port_color(enum led_color color) -{ - int port = charge_manager_get_active_charge_port(); - - if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) - side_led_set_color(0, (port == 0) ? color : LED_OFF); - if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - side_led_set_color(1, (port == 1) ? color : LED_OFF); -} - -static void board_led_set_battery(void) -{ - static int battery_ticks; - uint32_t chflags = charge_get_flags(); - - battery_ticks++; - - switch (charge_get_state()) { - case PWR_STATE_CHARGE: - /* Always indicate when charging, even in suspend. */ - set_active_port_color(LED_AMBER); - break; - case PWR_STATE_DISCHARGE: - if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { - if (charge_get_percent() <= 10) - side_led_set_color(0, - (battery_ticks & 0x4) ? LED_WHITE : LED_OFF); - else - side_led_set_color(0, LED_OFF); - } - - if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - side_led_set_color(1, LED_OFF); - break; - case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); - break; - case PWR_STATE_CHARGE_NEAR_FULL: - set_active_port_color(LED_WHITE); - break; - case PWR_STATE_IDLE: /* External power connected in IDLE */ - if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks & 0x4) ? - LED_AMBER : LED_OFF); - else - set_active_port_color(LED_WHITE); - break; - default: - /* Other states don't alter LED behavior */ - break; - } -} - -/* Called by hook task every TICK */ -static void led_tick(void) -{ - board_led_set_battery(); -} -DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT); - -void led_control(enum ec_led_id led_id, enum ec_led_state state) -{ - enum led_color color; - - if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) && - (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) - return; - - if (state == LED_STATE_RESET) { - led_auto_control(EC_LED_ID_LEFT_LED, 1); - led_auto_control(EC_LED_ID_RIGHT_LED, 1); - board_led_set_battery(); - return; - } - - color = state ? LED_WHITE : LED_OFF; - - led_auto_control(EC_LED_ID_LEFT_LED, 0); - led_auto_control(EC_LED_ID_RIGHT_LED, 0); - - side_led_set_color(0, color); - side_led_set_color(1, color); -} diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py index 7b8bf9cb42..755b6479a6 100644 --- a/zephyr/projects/intelrvp/BUILD.py +++ b/zephyr/projects/intelrvp/BUILD.py @@ -26,7 +26,7 @@ def register_intelrvp_project( dts_overlays.append(here / "adlrvp/ioex.dts") if project_name.startswith("mtlrvp"): kconfig_files.append(here / "mtlrvp/prj.conf") - dts_overlays.append(here / "mtlrvp/battery.dts") + dts_overlays.append(here / "adlrvp/battery.dts") kconfig_files.extend(extra_kconfig_files) dts_overlays.extend(extra_dts_overlays) @@ -65,6 +65,7 @@ register_intelrvp_project( here / "adlrvp/adlrvp_npcx/cbi_eeprom.dts", here / "mtlrvp/mtlrvpp_npcx/fan.dts", here / "mtlrvp/mtlrvpp_npcx/gpio.dts", + here / "mtlrvp/mtlrvpp_npcx/keyboard.dts", here / "mtlrvp/mtlrvpp_npcx/interrupts.dts", here / "mtlrvp/ioex.dts", here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts", diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts index e001827d69..e735234128 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts @@ -29,3 +29,31 @@ >; }; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/battery.dts b/zephyr/projects/intelrvp/mtlrvp/battery.dts deleted file mode 100644 index 505e5878d2..0000000000 --- a/zephyr/projects/intelrvp/mtlrvp/battery.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - batteries { - default_battery: getac_smp_hhp_408_3s { - compatible = "getac,bq40z50-R3-S3", "battery-smart"; - }; - getac_smp_hhp_408_2s { - compatible = "getac,bq40z50-R3-S2", "battery-smart"; - }; - }; -}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts new file mode 100644 index 0000000000..e735234128 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <35>; + debounce-down = <5000>; + debounce-up = <40000>; + poll-timeout = <100000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts index 81219636f0..57b41bd9d2 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts @@ -43,11 +43,18 @@ gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; interrupt-flags = <GPIO_INT_EDGE_BOTH>; }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 3 GPIO_OPEN_DRAIN>; + output; + }; pwr-ec-pch-sys-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_PWROK output to PCH"; enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiof 5 0>; + gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; output; }; pwr-sys-rst-l { diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index c490471bcb..a620e7b9ae 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -4,7 +4,7 @@ """Define zmake projects for nissa.""" -# Nivviks and Craask has NPCX993F, Nereid has ITE81302 +# Nivviks and Craask, Pujjo has NPCX993F, Nereid has ITE81302 def register_nissa_project( @@ -18,7 +18,7 @@ def register_nissa_project( if chip.startswith("npcx"): register_func = register_npcx_project - register_func( + return register_func( project_name=project_name, zephyr_board=chip, dts_overlays=["cbi.dts", *extra_dts_overlays], @@ -26,7 +26,7 @@ def register_nissa_project( ) -register_nissa_project( +nivviks = register_nissa_project( project_name="nivviks", chip="npcx9m3f", extra_dts_overlays=[ @@ -41,7 +41,7 @@ register_nissa_project( extra_kconfig_files=[here / "prj_nivviks.conf"], ) -register_nissa_project( +nereid = register_nissa_project( project_name="nereid", chip="it8xxx2", extra_dts_overlays=[ @@ -55,15 +55,30 @@ register_nissa_project( extra_kconfig_files=[here / "prj_nereid.conf"], ) -register_nissa_project( +craask = register_nissa_project( project_name="craask", chip="npcx9m3f", extra_dts_overlays=[ here / "craask_generated.dts", here / "craask_overlay.dts", here / "craask_motionsense.dts", + here / "craask_keyboard.dts", here / "craask_power_signals.dts", here / "craask_pwm_leds.dts", ], extra_kconfig_files=[here / "prj_craask.conf"], ) + +pujjo = register_nissa_project( + project_name="pujjo", + chip="npcx9m3f", + extra_dts_overlays=[ + here / "pujjo_generated.dts", + here / "pujjo_overlay.dts", + here / "pujjo_motionsense.dts", + here / "pujjo_keyboard.dts", + here / "pujjo_power_signals.dts", + here / "pujjo_pwm_leds.dts", + ], + extra_kconfig_files=[here / "prj_pujjo.conf"], +) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 18a82b9def..afc96e924f 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -35,7 +35,17 @@ if(DEFINED CONFIG_BOARD_CRAASK) zephyr_library_sources( "src/craask/led.c" ) - project(nivviks) + project(craask) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/craask/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/craask/charger.c") endif() +if(DEFINED CONFIG_BOARD_PUJJO) + project(pujjo) + zephyr_library_sources( + "src/led.c" + "src/pujjo/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/pujjo/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") +endif() diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig index 3f0ef5954a..87d7bca977 100644 --- a/zephyr/projects/nissa/Kconfig +++ b/zephyr/projects/nissa/Kconfig @@ -20,6 +20,12 @@ config BOARD_CRAASK Build Google Craask board. Craask has Intel ADL-N SoC with NPCX993FA0BX EC. +config BOARD_PUJJO + bool "Google Pujjo Board" + help + Build Google Pujjo board. Pujjo has Intel ADL-N SoC + with NPCX993FA0BX EC. + module = NISSA module-str = Nissa board-specific code source "subsys/logging/Kconfig.template.log_config" diff --git a/zephyr/projects/nissa/craask_keyboard.dts b/zephyr/projects/nissa/craask_keyboard.dts new file mode 100644 index 0000000000..d3fd354b8f --- /dev/null +++ b/zephyr/projects/nissa/craask_keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks_keyboard.dts b/zephyr/projects/nissa/nivviks_keyboard.dts index 72c573b796..71cb49ce65 100644 --- a/zephyr/projects/nissa/nivviks_keyboard.dts +++ b/zephyr/projects/nissa/nivviks_keyboard.dts @@ -16,3 +16,33 @@ pinctrl-0 = <&pwm6_gpc0>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts index 926dc46129..bc10f510a5 100644 --- a/zephyr/projects/nissa/nivviks_overlay.dts +++ b/zephyr/projects/nissa/nivviks_overlay.dts @@ -261,7 +261,14 @@ */ def-lvol-io-list { compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = <&lvol_iof5 &lvol_iof4>; + lvol-io-pads = < + &lvol_iof5 + &lvol_iof4 + &lvol_io90 /* EC_I2C_SENSOR_SCL */ + &lvol_io87 /* EC_I2C_SENSOR_SDA */ + &lvol_ioe3 /* VCCIN_AUX_VID1 */ + &lvol_io92 /* VCCIN_AUX_VID0 */ + >; }; /* * Declare unused GPIOs so that they are shut down diff --git a/zephyr/projects/nissa/prj.conf b/zephyr/projects/nissa/prj.conf index 621355bf6a..df988de149 100644 --- a/zephyr/projects/nissa/prj.conf +++ b/zephyr/projects/nissa/prj.conf @@ -8,7 +8,6 @@ CONFIG_CROS_EC=y CONFIG_PLATFORM_EC=y CONFIG_SHIMMED_TASKS=y CONFIG_LTO=y -CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y # Debug options and features; can be disabled to save memory or once bringup # is complete. diff --git a/zephyr/projects/nissa/prj_nereid.conf b/zephyr/projects/nissa/prj_nereid.conf index 2508f5b13b..4b0db30556 100644 --- a/zephyr/projects/nissa/prj_nereid.conf +++ b/zephyr/projects/nissa/prj_nereid.conf @@ -8,10 +8,6 @@ CONFIG_CROS_FLASH_IT8XXX2=y CONFIG_CROS_SYSTEM_IT8XXX2=y CONFIG_ESPI_IT8XXX2=y -# Permit more detailed debugging of chargers -# TODO(b:230712704) disable when behavior is better understood -CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y - # Allow more time for the charger to stabilise CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 diff --git a/zephyr/projects/nissa/prj_pujjo.conf b/zephyr/projects/nissa/prj_pujjo.conf new file mode 100644 index 0000000000..e7e9cbd357 --- /dev/null +++ b/zephyr/projects/nissa/prj_pujjo.conf @@ -0,0 +1,40 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_PUJJO=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=y +CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/pujjo_generated.dts b/zephyr/projects/nissa/pujjo_generated.dts new file mode 100644 index 0000000000..1c429ae32c --- /dev/null +++ b/zephyr/projects/nissa/pujjo_generated.dts @@ -0,0 +1,290 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + label = "EC_VSENSE_PP1050_PROC"; + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + label = "EC_VSENSE_PP3300_S5"; + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + label = "TEMP_SENSOR_1"; + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + label = "TEMP_SENSOR_2"; + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/pujjo_keyboard.dts b/zephyr/projects/nissa/pujjo_keyboard.dts new file mode 100644 index 0000000000..71cb49ce65 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_keyboard.dts @@ -0,0 +1,48 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + frequency = <10000>; + }; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts new file mode 100644 index 0000000000..69ebf04c59 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_motionsense.dts @@ -0,0 +1,163 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + label = "LID_MUTEX"; + }; + + base_mutex: base-mutex { + label = "BASE_MUTEX"; + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rot-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_data: lsm6dso-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The label "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO:(b/229577857) The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + label = "Lid Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + label = "Base Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + /* + * May be replaced by alternate depending + * on board config. + */ + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + label = "Base Gyro"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts new file mode 100644 index 0000000000..c185d46e11 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_overlay.dts @@ -0,0 +1,347 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 5 GPIO_INPUT>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpio6 3 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "DDR and SOC"; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "Charger"; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + pwm-frequency = <1000>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach2>; + enable_gpio = <&gpio_fan_enable>; + }; + }; + + /* + * Declare unused GPIOs so that they are shut down + * and use minimal power + */ + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 3 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; + +/* Tachometer for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo_power_signals.dts b/zephyr/projects/nissa/pujjo_power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/pujjo_pwm_leds.dts b/zephyr/projects/nissa/pujjo_pwm_leds.dts new file mode 100644 index 0000000000..b6f657fb03 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_pwm_leds.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <324>; + + /*<red green blue>*/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 20 100>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/src/craask/led.c b/zephyr/projects/nissa/src/craask/led.c index 53274f6c44..a0c0447419 100644 --- a/zephyr/projects/nissa/src/craask/led.c +++ b/zephyr/projects/nissa/src/craask/led.c @@ -18,6 +18,7 @@ __override struct led_descriptor [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, {LED_OFF, 3 * LED_ONE_SEC} }, [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, diff --git a/zephyr/projects/nissa/src/craask/usbc.c b/zephyr/projects/nissa/src/craask/usbc.c index 0604411be0..32a390e502 100644 --- a/zephyr/projects/nissa/src/craask/usbc.c +++ b/zephyr/projects/nissa/src/craask/usbc.c @@ -10,6 +10,7 @@ #include "hooks.h" #include "usb_mux.h" #include "system.h" +#include "driver/charger/isl923x_public.h" #include "driver/retimer/anx7483_public.h" #include "driver/tcpm/tcpci.h" #include "driver/tcpm/raa489000.h" @@ -67,9 +68,11 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } return EC_SUCCESS; } @@ -91,6 +94,7 @@ int board_set_active_charge_port(int port) if (tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW)) LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); } /* @@ -101,7 +105,8 @@ int board_set_active_charge_port(int port) charger_discharge_on_ac(1); /* Enable requested charge port. */ - if (tcpc_write(port, TCPC_REG_COMMAND, + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { LOG_WRN("p%d: sink path enable failed.", port); charger_discharge_on_ac(0); @@ -188,6 +193,10 @@ int pd_set_power_supply_ready(int port) if (rv) return rv; + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + /* Notify host of power info change. */ pd_send_host_event(PD_EVENT_POWER_CHANGE); diff --git a/zephyr/projects/nissa/src/led.c b/zephyr/projects/nissa/src/led.c index fa28ccc179..27c78f8051 100644 --- a/zephyr/projects/nissa/src/led.c +++ b/zephyr/projects/nissa/src/led.c @@ -18,6 +18,8 @@ __override struct led_descriptor [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, + {LED_OFF, 3 * LED_ONE_SEC} }, [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, diff --git a/zephyr/projects/nissa/src/nereid/usbc.c b/zephyr/projects/nissa/src/nereid/usbc.c index e731b73a76..eeab449c32 100644 --- a/zephyr/projects/nissa/src/nereid/usbc.c +++ b/zephyr/projects/nissa/src/nereid/usbc.c @@ -63,22 +63,19 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) __override bool pd_check_vbus_level(int port, enum vbus_level level) { - /* - * While the charger can differentiate SAFE0V from REMOVED, doing so - * requires doing a I2C read of the VBUS analog level. Because this - * function can be polled by the USB state machines and doing the I2C - * read is relatively costly, we only check the cached VBUS presence - * (for which interrupts record transitions). - */ - switch (level) { - case VBUS_PRESENT: - return sm5803_is_vbus_present(port); - case VBUS_SAFE0V: /* Less than vSafe0V */ - case VBUS_REMOVED: /* Less than vSinkDisconnect */ - return !sm5803_is_vbus_present(port); + int vbus_voltage; + + /* If we're unable to speak to the charger, best to guess false */ + if (charger_get_vbus_voltage(port, &vbus_voltage)) { + return false; } - LOG_WRN("Unrecognized vbus_level value: %d", level); - return false; + + if (level == VBUS_SAFE0V) + return vbus_voltage < PD_V_SAFE0V_MAX; + else if (level == VBUS_PRESENT) + return vbus_voltage > PD_V_SAFE5V_MIN; + else + return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; } /* diff --git a/zephyr/projects/nissa/src/nivviks/usbc.c b/zephyr/projects/nissa/src/nivviks/usbc.c index 0b061d2bd5..c068eba6f4 100644 --- a/zephyr/projects/nissa/src/nivviks/usbc.c +++ b/zephyr/projects/nissa/src/nivviks/usbc.c @@ -10,6 +10,7 @@ #include "hooks.h" #include "usb_mux.h" #include "system.h" +#include "driver/charger/isl923x_public.h" #include "driver/retimer/anx7483_public.h" #include "driver/tcpm/tcpci.h" #include "driver/tcpm/raa489000.h" @@ -67,9 +68,11 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } return EC_SUCCESS; } @@ -91,6 +94,7 @@ int board_set_active_charge_port(int port) if (tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW)) LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); } /* @@ -101,7 +105,8 @@ int board_set_active_charge_port(int port) charger_discharge_on_ac(1); /* Enable requested charge port. */ - if (tcpc_write(port, TCPC_REG_COMMAND, + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { LOG_WRN("p%d: sink path enable failed.", port); charger_discharge_on_ac(0); @@ -188,6 +193,10 @@ int pd_set_power_supply_ready(int port) if (rv) return rv; + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + /* Notify host of power info change. */ pd_send_host_event(PD_EVENT_POWER_CHANGE); diff --git a/zephyr/projects/nissa/src/pujjo/charger.c b/zephyr/projects/nissa/src/pujjo/charger.c new file mode 100644 index 0000000000..c6209bdf75 --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Pujjo does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/src/pujjo/fan.c b/zephyr/projects/nissa/src/pujjo/fan.c new file mode 100644 index 0000000000..8914774452 --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/fan.c @@ -0,0 +1,45 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Pujjo fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/src/pujjo/keyboard.c b/zephyr/projects/nissa/src/pujjo/keyboard.c new file mode 100644 index 0000000000..e6d819e348 --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config pujjo_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config +*board_vivaldi_keybd_config(void) +{ + return &pujjo_kb; +} diff --git a/zephyr/projects/nissa/src/pujjo/usbc.c b/zephyr/projects/nissa/src/pujjo/usbc.c new file mode 100644 index 0000000000..020f78dbdd --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/usbc.c @@ -0,0 +1,281 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && + port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, + const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int (void) +{ + poll_usb_gpio(0, + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int (void) +{ + poll_usb_gpio(1, + GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/npcx_evb/npcx9/keyboard.dts b/zephyr/projects/npcx_evb/npcx9/keyboard.dts index e2a5010952..e3ce1b1e20 100644 --- a/zephyr/projects/npcx_evb/npcx9/keyboard.dts +++ b/zephyr/projects/npcx_evb/npcx9/keyboard.dts @@ -41,3 +41,31 @@ pinctrl-0 = <&pwm2_gpc4>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h index 969549bc5d..ca1272a9ed 100644 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ b/zephyr/projects/skyrim/include/gpio_map.h @@ -23,5 +23,6 @@ enum power_signal { #define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/keyboard.dts b/zephyr/projects/skyrim/keyboard.dts index 792e6074d1..216ea97045 100644 --- a/zephyr/projects/skyrim/keyboard.dts +++ b/zephyr/projects/skyrim/keyboard.dts @@ -17,3 +17,31 @@ pinctrl-0 = <&pwm1_gpc2>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf index aea666c234..47e9c1d096 100644 --- a/zephyr/projects/skyrim/prj.conf +++ b/zephyr/projects/skyrim/prj.conf @@ -19,7 +19,9 @@ CONFIG_AP=y CONFIG_AP_X86_AMD=y CONFIG_PLATFORM_EC_POWERSEQ=y CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y +CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y CONFIG_PLATFORM_EC_PORT80=y # Power button diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/usbc_config.c index 7e3b6ba486..fe60db2a69 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/usbc_config.c @@ -3,7 +3,7 @@ * found in the LICENSE file. */ -/* Guybrush family-specific USB-C configuration */ +/* Skyrim family-specific USB-C configuration */ #include <zephyr/drivers/gpio.h> @@ -110,18 +110,69 @@ struct usb_mux usbc1_sbu_mux = { .driver = &ioex_sbu_mux_driver, }; -int baseboard_anx7483_mux_set(const struct usb_mux *me, +int baseboard_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) { return anx7483_set_default_tuning(me, mux_state); } +int baseboard_anx7483_c1_mux_set(const struct usb_mux *me, + mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + struct usb_mux usbc0_anx7483 = { .usb_port = USBC_PORT_C0, .i2c_port = I2C_PORT_TCPC0, .i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS, .driver = &anx7483_usb_retimer_driver, - .board_set = &baseboard_anx7483_mux_set, + .board_set = &baseboard_anx7483_c0_mux_set, .next_mux = &usbc0_sbu_mux, }; @@ -129,6 +180,13 @@ __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) { CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + return 0; } @@ -146,7 +204,7 @@ struct usb_mux usbc1_anx7483 = { .i2c_port = I2C_PORT_TCPC1, .i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS, .driver = &anx7483_usb_retimer_driver, - .board_set = &baseboard_anx7483_mux_set, + .board_set = &baseboard_anx7483_c1_mux_set, .next_mux = &usbc1_sbu_mux, }; @@ -168,8 +226,6 @@ struct usb_mux usb_muxes[] = { }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); -/* TODO: HPD signal on PS8818 DB */ - /* * USB C0 (general) and C1 (just ANX DB) use IOEX pins to * indicate flipped polarity to a protection switch. @@ -350,10 +406,10 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, /* TODO: sbu_fault_interrupt from io expander */ /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 +#define SKYRIM_AC_PROCHOT_CURRENT_MA 3328 static void set_ac_prochot(void) { - isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); + isl9241_set_ac_prochot(CHARGER_SOLO, SKYRIM_AC_PROCHOT_CURRENT_MA); } DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h index 9af8bd330d..b3677fb45c 100644 --- a/zephyr/shim/chip/mchp/include/flash_chip.h +++ b/zephyr/shim/chip/mchp/include/flash_chip.h @@ -11,15 +11,19 @@ * Similar to W25X40, both only have one status reg */ #define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */ - #define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define CONFIG_FLASH_ERASE_SIZE 0x1000 #define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE -/* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE - -#define CONFIG_RW_STORAGE_OFF 0 +/* RO image resides at 4KB offset in protected region + * The first 4KB in the protected region starting at offset 0 contains + * the Boot-ROM TAGs and Boot-ROM Header for EC_RO. These objects are + * not loaded into RAM. + * RW image is never loaded by the Boot-ROM therefore no TAG or Header + * is needed. RW starts at offset 0 in RW storage region. + */ +#define CONFIG_RO_STORAGE_OFF 0x1000 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/mchp/system.c b/zephyr/shim/chip/mchp/system.c index f4e0d09d4d..25fdfc9897 100644 --- a/zephyr/shim/chip/mchp/system.c +++ b/zephyr/shim/chip/mchp/system.c @@ -11,6 +11,29 @@ LOG_MODULE_REGISTER(shim_xec_system, LOG_LEVEL_ERR); +#define GET_BBRAM_OFS(node) \ + DT_PROP(DT_PATH(named_bbram_regions, node), offset) +#define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size) + +/* + * Reset image type back to RO in BBRAM as watchdog resets. + * Watchdog reset will reset EC chip, ROM loader loads RO + * image stored in SPI flash chip in default. + */ +void cros_chip_wdt_handler(const struct device *wdt_dev, int channel_id) +{ + const struct device *bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram)); + uint32_t value = EC_IMAGE_RO; + + if (!device_is_ready(bbram_dev)) { + LOG_ERR("WDT ISR: device %s is not ready", bbram_dev->name); + return; + } + + bbram_write(bbram_dev, GET_BBRAM_OFS(ec_img_load), + GET_BBRAM_SZ(ec_img_load), (uint8_t *)&value); +} + static void chip_bbram_status_check(void) { const struct device *bbram_dev; diff --git a/zephyr/shim/chip/mchp/system_download_from_flash.c b/zephyr/shim/chip/mchp/system_download_from_flash.c index 665db2cccd..99026fe822 100644 --- a/zephyr/shim/chip/mchp/system_download_from_flash.c +++ b/zephyr/shim/chip/mchp/system_download_from_flash.c @@ -10,6 +10,10 @@ #include "system_chip.h" /* Modules Map */ +#define WDT_NODE DT_INST(0, microchip_xec_watchdog) +#define STRUCT_WDT_REG_BASE_ADDR \ + ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE))) + #define PCR_NODE DT_INST(0, microchip_xec_pcr) #define STRUCT_PCR_REG_BASE_ADDR \ ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) @@ -26,15 +30,15 @@ (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE) #define QSPI_STATUS_ERR \ - (MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \ + (MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \ MCHP_QMSPI_STS_PROG_ERR | MCHP_QMSPI_STS_LDMA_RX_ERR) - noreturn void __keep __attribute__ ((section(".code_in_sram2"))) __start_qspi(uint32_t resetVectAddr) { struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR; struct qmspi_regs *qspi = STRUCT_QSPI_REG_BASE_ADDR; + struct wdt_regs *wdt = STRUCT_WDT_REG_BASE_ADDR; uint32_t qsts = 0; uint32_t exeAddr = 0; @@ -47,6 +51,9 @@ __start_qspi(uint32_t resetVectAddr) break; } + /* Stop the watchdog */ + wdt->CTRL &= ~MCHP_WDT_CTRL_EN; + qspi->MODE &= ~(MCHP_QMSPI_M_ACTIVATE); if (qsts & QSPI_STATUS_ERR) { pcr->SYS_RST |= MCHP_PCR_SYS_RESET_NOW; @@ -67,8 +74,7 @@ __start_qspi(uint32_t resetVectAddr) ; } -/* PK SCM */ -uintptr_t __lfw_sram_start = 0x127800; +uintptr_t __lfw_sram_start = CONFIG_CROS_EC_RAM_BASE + CONFIG_CROS_EC_RAM_SIZE; typedef void (*START_QSPI_IN_SRAM_FP)(uint32_t); @@ -85,9 +91,9 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Check valid address for jumpiing */ __ASSERT_NO_MSG(exeAddr != 0x0); - + /* Configure QMSPI controller */ qspi->MODE = MCHP_QMSPI_M_SRST; - fdiv = 4; + fdiv = 2; if (pcr->TURBO_CLK & MCHP_PCR_TURBO_CLK_96M) fdiv *= 2; diff --git a/zephyr/shim/chip/mchp/system_external_storage.c b/zephyr/shim/chip/mchp/system_external_storage.c index 2c7312db3a..c326a07328 100644 --- a/zephyr/shim/chip/mchp/system_external_storage.c +++ b/zephyr/shim/chip/mchp/system_external_storage.c @@ -4,13 +4,35 @@ */ #include <zephyr/devicetree.h> -#include <zephyr/drivers/syscon.h> +#include <zephyr/drivers/bbram.h> +#include <soc.h> #include "clock_chip.h" #include "common.h" #include "system.h" #include "system_chip.h" +#include "config_chip.h" +#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */ +#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */ +#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr) + +#define GET_BBRAM_OFS(node) \ + DT_PROP(DT_PATH(named_bbram_regions, node), offset) +#define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size) + +static const struct device *const bbram_dev = + COND_CODE_1(DT_HAS_CHOSEN(cros_ec_bbram), + DEVICE_DT_GET(DT_CHOSEN(cros_ec_bbram)), NULL); + +/* Build image type string in RO/RW image */ +#ifdef CONFIG_CROS_EC_RO +const uint32_t mchp_image_type = MCHP_ECRO_WORD; +#elif CONFIG_CROS_EC_RW +const uint32_t mchp_image_type = MCHP_ECRW_WORD; +#else +#error "Unsupported image type!" +#endif /* * Make sure CONFIG_XXX flash offsets are correct for MEC172x 512KB SPI flash. @@ -29,19 +51,12 @@ void system_jump_to_booter(void) case EC_IMAGE_RW: flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; - flash_used = CONFIG_RW_SIZE; - break; -#ifdef CONFIG_RW_B - case EC_IMAGE_RW_B: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF; - flash_used = CONFIG_RW_SIZE; + flash_used = CONFIG_CROS_EC_RW_SIZE; break; -#endif case EC_IMAGE_RO: default: /* Jump to RO by default */ - flash_offset = 0x100; /* 256 bytes */ - flash_used = (352 * 1024); + flash_offset = CONFIG_PLATFORM_EC_RO_HEADER_OFFSET; + flash_used = CONFIG_CROS_EC_RO_SIZE; break; } @@ -53,9 +68,11 @@ void system_jump_to_booter(void) /* MCHP Read selected image from SPI flash into SRAM * Need a jump to little-fw (LFW). - * MEC172x Boot-ROM load API is probably not usuable for this. */ - system_download_from_flash(flash_offset, 0xC0000u, flash_used, 0xC0004); + system_download_from_flash(flash_offset, + CONFIG_CROS_EC_PROGRAM_MEMORY_BASE, + flash_used, + (CONFIG_CROS_EC_PROGRAM_MEMORY_BASE + 4u)); } uint32_t system_get_lfw_address(void) @@ -66,13 +83,51 @@ uint32_t system_get_lfw_address(void) enum ec_image system_get_shrspi_image_copy(void) { - return EC_IMAGE_RO; + enum ec_image img = EC_IMAGE_UNKNOWN; + uint32_t value = 0u; + + if (bbram_dev) { + if (!bbram_read(bbram_dev, GET_BBRAM_OFS(ec_img_load), + GET_BBRAM_SZ(ec_img_load), (uint8_t *)&value)) { + img = (enum ec_image)(value & 0x7fu); + } + } + + if (img == EC_IMAGE_UNKNOWN) { + img = EC_IMAGE_RO; + if (mchp_image_type == MCHP_ECRW_WORD) { + img = EC_IMAGE_RW; + } + system_set_image_copy(img); + } + + return img; } -/* - * This configures HW to point to EC_RW or EC_RO. +/* Flash is not memory mapped. Store a flag indicating the image. + * ECS WDT_CNT is register available to applications. It implements bits[3:0] + * which are not reset by a watch dog event only by VTR/chip reset. + * VBAT memory is safer only if the board has a stable VBAT power rail. */ void system_set_image_copy(enum ec_image copy) { - /* TODO(b/226599277): check if further development is requested */ + uint32_t value = (uint32_t)copy; + + if (!bbram_dev) { + return; + } + + switch (copy) { + case EC_IMAGE_RW: + case EC_IMAGE_RW_B: + value = EC_IMAGE_RW; + break; + case EC_IMAGE_RO: + default: + value = EC_IMAGE_RO; + break; + } + + bbram_write(bbram_dev, GET_BBRAM_OFS(ec_img_load), + GET_BBRAM_SZ(ec_img_load), (uint8_t *)&value); } diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 9d86e8551b..73f38a72f4 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -1869,6 +1869,11 @@ extern struct jump_data mock_jump_data; #define CONFIG_ACCEL_SPOOF_MODE #endif +#undef CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ +#ifdef CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ +#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ +#endif + #undef CONFIG_CMD_ACCEL_SPOOF #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF #define CONFIG_CMD_ACCEL_SPOOF diff --git a/zephyr/shim/src/CMakeLists.txt b/zephyr/shim/src/CMakeLists.txt index 9273a41fde..dee8d0af71 100644 --- a/zephyr/shim/src/CMakeLists.txt +++ b/zephyr/shim/src/CMakeLists.txt @@ -2,7 +2,6 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -zephyr_library_sources(chipset_api.c) zephyr_library_sources(console.c) zephyr_library_sources(crc.c) zephyr_library_sources(gpio.c) @@ -27,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_RT9490 bc12_rt9490.c) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER charger.c) +zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ chipset_api.c) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI espi.c) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN fan.c) diff --git a/zephyr/shim/src/chipset_api.c b/zephyr/shim/src/chipset_api.c index 2804de8e78..3bfa420980 100644 --- a/zephyr/shim/src/chipset_api.c +++ b/zephyr/shim/src/chipset_api.c @@ -7,7 +7,6 @@ #include "common.h" -#if defined(CONFIG_AP_PWRSEQ) #include "ap_power/ap_power_interface.h" #include "chipset_state_check.h" @@ -45,34 +44,3 @@ void init_reset_log(void) { ap_power_init_reset_log(); } - -#else - -#if !defined(HAS_TASK_CHIPSET) -#include "chipset.h" - -/* When no chipset is present, assume it is always off. */ -int chipset_in_state(int state_mask) -{ - return state_mask & CHIPSET_STATE_ANY_OFF; -} -int chipset_in_or_transitioning_to_state(int state_mask) -{ - return state_mask & CHIPSET_STATE_ANY_OFF; -} -void chipset_exit_hard_off(void) { } -void chipset_throttle_cpu(int throttle) { } -void chipset_force_shutdown(enum chipset_shutdown_reason reason) { } -void chipset_reset(enum chipset_shutdown_reason reason) { } -void power_interrupt(enum gpio_signal signal) { } -void chipset_handle_espi_reset_assert(void) { } -void chipset_handle_reboot(void) { } -void chipset_reset_request_interrupt(enum gpio_signal signal) { } -void chipset_warm_reset_interrupt(enum gpio_signal signal) { } -void chipset_ap_rst_interrupt(enum gpio_signal signal) { } -void chipset_power_good_interrupt(enum gpio_signal signal) { } -void chipset_watchdog_interrupt(enum gpio_signal signal) { } -void init_reset_log(void) { } - -#endif /* !defined(HAS_TASK_CHIPSET) */ -#endif /*defined(CONFIG_AP_PWRSEQ) */ diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c index 1093a26dff..f8051d8638 100644 --- a/zephyr/shim/src/console.c +++ b/zephyr/shim/src/console.c @@ -344,7 +344,8 @@ static void zephyr_print(const char *buff, size_t size) * Also, console_buf_notify_chars uses a mutex, which may not be * locked in ISRs. */ - if (k_is_in_isr() || shell_stopped) { + if (k_is_in_isr() || shell_stopped || + shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) { printk("%s", buff); } else { shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", buff); diff --git a/zephyr/shim/src/led_driver/led.h b/zephyr/shim/src/led_driver/led.h index af2b11fa92..8c4e7654d5 100644 --- a/zephyr/shim/src/led_driver/led.h +++ b/zephyr/shim/src/led_driver/led.h @@ -119,4 +119,9 @@ void led_set_color(enum led_color color, enum ec_led_id led_id); */ void led_set_color_with_node(const struct led_pins_node_t *pins_node); +#ifdef TEST_BUILD +const struct led_pins_node_t *led_get_node(enum led_color color, + enum ec_led_id led_id); +#endif /* TEST_BUILD */ + #endif /* __CROS_EC_LED_H__ */ diff --git a/zephyr/shim/src/led_driver/led_gpio.c b/zephyr/shim/src/led_driver/led_gpio.c index 598839a30f..5a4735a162 100644 --- a/zephyr/shim/src/led_driver/led_gpio.c +++ b/zephyr/shim/src/led_driver/led_gpio.c @@ -128,4 +128,23 @@ __override int led_is_supported(enum ec_led_id led_id) return ((1 << (int)led_id) & supported_leds); } + +#ifdef TEST_BUILD +const struct led_pins_node_t *led_get_node(enum led_color color, + enum ec_led_id led_id) +{ + const struct led_pins_node_t *pin_node = NULL; + + for (int i = 0; i < ARRAY_SIZE(pins_node); i++) { + if (pins_node[i]->led_id == led_id && + pins_node[i]->led_color == color) { + pin_node = pins_node[i]; + break; + } + } + + return pin_node; +} +#endif /* TEST_BUILD */ + #endif /* DT_HAS_COMPAT_STATUS_OKAY(COMPAT_GPIO_LED) */ diff --git a/zephyr/shim/src/watchdog.c b/zephyr/shim/src/watchdog.c index afb385054b..00cd5c4c30 100644 --- a/zephyr/shim/src/watchdog.c +++ b/zephyr/shim/src/watchdog.c @@ -27,6 +27,11 @@ static void wdt_warning_handler(const struct device *wdt_dev, int channel_id) #ifdef TEST_BUILD wdt_warning_triggered = true; #endif +#ifdef CONFIG_SOC_SERIES_MEC172X + extern void cros_chip_wdt_handler(const struct device *wdt_dev, + int channel_id); + cros_chip_wdt_handler(wdt_dev, channel_id); +#endif } int watchdog_init(void) diff --git a/zephyr/subsys/ap_pwrseq/power_signals.c b/zephyr/subsys/ap_pwrseq/power_signals.c index f3405b4119..135a0d9ac1 100644 --- a/zephyr/subsys/ap_pwrseq/power_signals.c +++ b/zephyr/subsys/ap_pwrseq/power_signals.c @@ -310,7 +310,7 @@ void power_signal_init(void) * don't get OR'ed in later on. */ for (int i = 0; i < ARRAY_SIZE(polled_signals); i++) { - atomic_clear_bit(&power_signals, i); + atomic_clear_bit(&power_signals, polled_signals[i]); } /* * Save the current state so that new changes can be diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c index d6430e906c..5183824117 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c @@ -9,27 +9,32 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); static void ap_off(void) { + power_signal_set(PWR_PCH_PWROK, 0); power_signal_set(PWR_EC_PCH_SYS_PWROK, 0); } /* Generate SYS_PWROK->SOC if needed by system */ -static void generate_sys_pwrok_handler(void) +static void generate_pwrok_handler(void) { + int all_sys_pwrgd_in; + if (power_signal_get(PWR_EC_PCH_SYS_PWROK) == 0) { k_msleep(AP_PWRSEQ_DT_VALUE(sys_pwrok_delay)); - /* - * Loop through all PWROK signals defined by the board and set - * to match the current ALL_SYS_PWRGD input. - */ - if (power_signal_get(PWR_ALL_SYS_PWRGD) == 0) { - LOG_DBG("PG_EC_ALL_SYS_PWRGD deasserted, " - "shutting AP off!"); - ap_off(); - return; - } - LOG_INF("Turning on PWR_EC_PCH_SYS_PWROK"); - power_signal_set(PWR_EC_PCH_SYS_PWROK, 1); } + + all_sys_pwrgd_in = power_signal_get(PWR_ALL_SYS_PWRGD); + /* Loop through all PWROK signals defined by the board */ + if (all_sys_pwrgd_in == 0) { + LOG_DBG("PG_EC_ALL_SYS_PWRGD deasserted, " + "shutting AP off!"); + ap_off(); + return; + } + + power_signal_set(PWR_EC_PCH_SYS_PWROK, all_sys_pwrgd_in); + /* PCH_PWROK is set to combined result of ALL_SYS_PWRGD and SLP_S3 */ + power_signal_set(PWR_PCH_PWROK, all_sys_pwrgd_in && + !power_signal_get(PWR_SLP_S3)); } /* Chipset specific power state machine handler */ @@ -45,7 +50,7 @@ enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state) break; case SYS_POWER_STATE_S0: /* Send SYS_PWROK->SoC if conditions met */ - generate_sys_pwrok_handler(); + generate_pwrok_handler(); break; default: break; diff --git a/zephyr/test/drivers/BUILD.py b/zephyr/test/drivers/BUILD.py index 9e3465c18e..c43579da2e 100644 --- a/zephyr/test/drivers/BUILD.py +++ b/zephyr/test/drivers/BUILD.py @@ -6,6 +6,13 @@ register_host_test( "drivers", - dts_overlays=["overlay.dts"], + dts_overlays=[ + "overlay.dts", + here / "led_driver/led_pins.dts", + here / "led_driver/led_policy.dts", + ], + kconfig_files=[ + here / "led_driver/prj.conf", + ], test_args=["-flash={test_temp_dir}/flash.bin"], ) diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index b4c85defa2..33163427b5 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -53,7 +53,7 @@ target_sources(app PRIVATE src/panic.c src/power_common.c src/ppc_sn5s330.c - src/ppc_syv682c.c + src/ppc_syv682x.c src/ps8xxx.c src/smart.c src/stm_mems_common.c @@ -74,5 +74,6 @@ target_sources(app PRIVATE ) add_subdirectory(isl923x) +add_subdirectory(led_driver) set_compiler_property(APPEND PROPERTY coverage -O0) diff --git a/zephyr/test/drivers/led_driver/CMakeLists.txt b/zephyr/test/drivers/led_driver/CMakeLists.txt new file mode 100644 index 0000000000..2f96eba2d3 --- /dev/null +++ b/zephyr/test/drivers/led_driver/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Create library name based on current directory +zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name) + +# Create interface library +zephyr_interface_library_named(${lib_name}) + +# Add include paths +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}") +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") +zephyr_include_directories("${PLATFORM_EC}/zephyr/shim/src/led_driver") + +# Add source files +zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/led.c") + +# Link in the library +zephyr_library_link_libraries(${lib_name}) diff --git a/zephyr/test/drivers/led_driver/led_pins.dts b/zephyr/test/drivers/led_driver/led_pins.dts new file mode 100644 index 0000000000..0127d762b2 --- /dev/null +++ b/zephyr/test/drivers/led_driver/led_pins.dts @@ -0,0 +1,54 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + /* Based off of `ec/zephyr/projects/herobrine/led_pins_herobrine.dts` + * Modified led-colors to obtain better test coverage. + */ +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off_left: color-off-left { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_SYSRQ_DEBUG_LED"; + led-pins = <&gpio_ec_chg_led_y_c1 0>, + <&gpio_ec_chg_led_w_c1 0>; + }; + color_off_right: color-off-right { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_RIGHT_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 0>; + }; + color_blue_left: color-blue-left { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_SYSRQ_DEBUG_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_y_c1 1>, + <&gpio_ec_chg_led_w_c1 0>; + }; + color_blue_right: color-blue-right { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_y_c0 1>, + <&gpio_ec_chg_led_w_c0 0>; + }; + color_white_left: color-white-left { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_SYSRQ_DEBUG_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&gpio_ec_chg_led_y_c1 0>, + <&gpio_ec_chg_led_w_c1 1>; + }; + color_white_right: color-white-right { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 1>; + }; + }; +}; diff --git a/zephyr/test/drivers/led_driver/led_policy.dts b/zephyr/test/drivers/led_driver/led_policy.dts new file mode 100644 index 0000000000..dbbc23062f --- /dev/null +++ b/zephyr/test/drivers/led_driver/led_policy.dts @@ -0,0 +1,215 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Based off of `ec/zephyr/projects/herobrine/led_policy_herobrine.dts` + * Modified led-colors to obtain better test coverage. + */ + +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-colors"; + + power-state-charge-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to Blue */ + color-1 { + led-color = <&color_blue_left>; + }; + }; + + power-state-charge-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to Blue */ + color-1 { + led-color = <&color_blue_right>; + }; + }; + + power-state-discharge-right-low { + charge-state = "PWR_STATE_DISCHARGE"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-discharge-right { + charge-state = "PWR_STATE_DISCHARGE"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Turn off the right LED */ + color-1 { + led-color = <&color_off_right>; + }; + }; + + power-state-error-left { + charge-state = "PWR_STATE_ERROR"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED - White 2 sec, off 2 sec */ + color-1 { + led-color = <&color_white_left>; + period-ms = <2000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <2000>; + }; + }; + + power-state-error-right { + charge-state = "PWR_STATE_ERROR"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - White 2 sec, off 2 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <2000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <2000>; + }; + }; + + power-state-near-full-left { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to White */ + color-1 { + led-color = <&color_white_left>; + }; + }; + + power-state-near-full-right { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + + power-state-idle-forced-left { + charge-state = "PWR_STATE_IDLE"; + charge-port = <1>; /* Left port */ + extra-flag = "LED_CHFLAG_FORCE_IDLE"; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED - Blue 3 sec, Off 1 sec */ + color-1 { + led-color = <&color_blue_left>; + period-ms = <3000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <1000>; + }; + }; + + power-state-idle-forced-right { + charge-state = "PWR_STATE_IDLE"; + charge-port = <0>; /* Right port */ + extra-flag = "LED_CHFLAG_FORCE_IDLE"; + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - Blue 3 sec, Off 1 sec */ + color-1 { + led-color = <&color_blue_right>; + period-ms = <3000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <1000>; + }; + }; + + power-state-idle-default-left { + charge-state = "PWR_STATE_IDLE"; + charge-port = <1>; /* Left port */ + extra-flag = "LED_CHFLAG_DEFAULT"; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to White */ + color-1 { + led-color = <&color_white_left>; + }; + }; + + power-state-idle-default-right { + charge-state = "PWR_STATE_IDLE"; + charge-port = <0>; /* Right port */ + extra-flag = "LED_CHFLAG_DEFAULT"; + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + }; +}; diff --git a/zephyr/test/drivers/led_driver/prj.conf b/zephyr/test/drivers/led_driver/prj.conf new file mode 100644 index 0000000000..abdb8cc6a1 --- /dev/null +++ b/zephyr/test/drivers/led_driver/prj.conf @@ -0,0 +1,6 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y diff --git a/zephyr/test/drivers/led_driver/src/led.c b/zephyr/test/drivers/led_driver/src/led.c new file mode 100644 index 0000000000..5c0c9d0c01 --- /dev/null +++ b/zephyr/test/drivers/led_driver/src/led.c @@ -0,0 +1,69 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <ztest.h> +#include "ec_commands.h" +#include "gpio.h" +#include "led.h" +#include "led_common.h" +#include "test/drivers/test_state.h" + +#define VERIFY_LED_COLOR(color, led_id) \ + { \ + const struct led_pins_node_t *pin_node = \ + led_get_node(color, led_id); \ + for (int j = 0; j < pin_node->pins_count; j++) { \ + int val = gpio_pin_get_dt(gpio_get_dt_spec( \ + pin_node->gpio_pins[j].signal)); \ + int expecting = pin_node->gpio_pins[j].val; \ + zassert_equal(expecting, val, "[%d]: %d != %d", j, \ + expecting, val); \ + } \ + } + +ZTEST_SUITE(led_driver, drivers_predicate_post_main, NULL, NULL, NULL, NULL); + +ZTEST(led_driver, test_led_control) +{ + /* Exercise valid led_id, set to RESET state */ + led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_RESET); + VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED); + + /* Exercise valid led_id, set to OFF state. + * Verify matches OFF color defined in device tree + */ + led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_OFF); + VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED); + + /* Exercise valid led_id, set to ON state. + * Verify matches ON color defined in device tree + */ + led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_ON); + VERIFY_LED_COLOR(LED_BLUE, EC_LED_ID_SYSRQ_DEBUG_LED); + + /* Exercise invalid led_id -- no change to led color */ + led_control(EC_LED_ID_LEFT_LED, LED_STATE_RESET); + VERIFY_LED_COLOR(LED_BLUE, EC_LED_ID_SYSRQ_DEBUG_LED); +} + +ZTEST(led_driver, test_led_brightness) +{ + uint8_t brightness[EC_LED_COLOR_COUNT] = { -1 }; + + /* Verify LED set to OFF */ + led_set_brightness(EC_LED_ID_SYSRQ_DEBUG_LED, brightness); + VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED); + + /* Verify LED colors defined in device tree are reflected in the + * brightness array. + */ + led_get_brightness_range(EC_LED_ID_SYSRQ_DEBUG_LED, brightness); + zassert_equal(brightness[EC_LED_COLOR_BLUE], 1, NULL); + zassert_equal(brightness[EC_LED_COLOR_WHITE], 1, NULL); + + /* Verify LED set to WHITE */ + led_set_brightness(EC_LED_ID_SYSRQ_DEBUG_LED, brightness); + VERIFY_LED_COLOR(LED_WHITE, EC_LED_ID_SYSRQ_DEBUG_LED); +} diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index df0888175f..d8c92a53ef 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -166,6 +166,22 @@ gpios = <&gpio0 29 (GPIO_ACTIVE_LOW | GPIO_INPUT)>; no-auto-init; }; + gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + #led-pin-cells = <1>; + gpios = <&gpio0 30 (GPIO_INPUT | GPIO_OUTPUT_LOW)>; + }; + gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 { + #led-pin-cells = <1>; + gpios = <&gpio0 31 (GPIO_INPUT | GPIO_OUTPUT_LOW)>; + }; + gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 { + #led-pin-cells = <1>; + gpios = <&gpio0 32 (GPIO_INPUT | GPIO_OUTPUT_LOW)>; + }; + gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 { + #led-pin-cells = <1>; + gpios = <&gpio0 33 (GPIO_INPUT | GPIO_OUTPUT_LOW)>; + }; }; gpio-interrupts { @@ -776,7 +792,7 @@ }; &gpio0 { - ngpios = <30>; + ngpios = <34>; }; &i2c0 { diff --git a/zephyr/test/drivers/src/espi.c b/zephyr/test/drivers/src/espi.c index 91746e7c45..67fc3c6f90 100644 --- a/zephyr/test/drivers/src/espi.c +++ b/zephyr/test/drivers/src/espi.c @@ -58,4 +58,25 @@ ZTEST_USER(espi, test_host_command_typec_status) zassert_equal(args.response_size, sizeof(response), NULL); } +ZTEST_USER(espi, test_host_command_usb_pd_get_amode) +{ + /* Only test we've enabled the command */ + struct ec_params_usb_pd_get_mode_request params = { + .port = PORT, + .svid_idx = 0, + }; + struct ec_params_usb_pd_get_mode_response response; + struct host_cmd_handler_args args = BUILD_HOST_COMMAND( + EC_CMD_USB_PD_GET_AMODE, 0, response, params); + + zassert_ok(host_command_process(&args), NULL); + zassert_ok(args.result, NULL); + /* Note: with no SVIDs the response size is the size of the svid field. + * See the usb alt mode test for verifying larger struct sizes + * + * TODO(b/219562077): Add the above described test. + */ + zassert_equal(args.response_size, sizeof(response.svid), NULL); +} + ZTEST_SUITE(espi, drivers_predicate_post_main, NULL, NULL, NULL, NULL); diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 472c57d978..fadb595e4b 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -20,6 +20,8 @@ #include "test/drivers/utils.h" #include "test/drivers/test_state.h" +#define TEST_PORT USBC_PORT_C0 + struct usbc_alt_mode_fixture { const struct emul *tcpci_emul; const struct emul *charger_emul; @@ -66,7 +68,7 @@ static void *usbc_alt_mode_setup(void) fixture.tcpci_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); /* The configured TCPCI rev must match the emulator's supported rev. */ - tcpc_config[0].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); @@ -127,7 +129,7 @@ ZTEST_F(usbc_alt_mode, verify_discovery) uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; struct ec_response_typec_discovery *discovery = (struct ec_response_typec_discovery *)response_buffer; - host_cmd_typec_discovery(USBC_PORT_C0, TYPEC_PARTNER_SOP, + host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, sizeof(response_buffer)); /* The host command does not count the VDM header in identity_count. */ diff --git a/zephyr/test/drivers/src/ppc_syv682c.c b/zephyr/test/drivers/src/ppc_syv682c.c deleted file mode 100644 index 9707f374ac..0000000000 --- a/zephyr/test/drivers/src/ppc_syv682c.c +++ /dev/null @@ -1,717 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <zephyr/device.h> -#include <zephyr/devicetree/gpio.h> -#include <zephyr/drivers/gpio/gpio_emul.h> -#include <fff.h> -#include <zephyr/zephyr.h> -#include <ztest.h> -#include <ztest_assert.h> - -#include "emul/emul_common_i2c.h" -#include "emul/emul_syv682x.h" -#include "test/drivers/stubs.h" -#include "syv682x.h" -#include "timer.h" -#include "test/drivers/test_state.h" -#include "usbc_ppc.h" - -#define SYV682X_ORD DT_DEP_ORD(DT_NODELABEL(syv682x_emul)) -#define GPIO_USB_C1_FRS_EN_PATH DT_PATH(named_gpios, usb_c1_frs_en) - -#define GPIO_USB_C1_FRS_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_FRS_EN_PATH, gpios) - -/* Configuration for a mock I2C access function that sometimes fails. */ -struct reg_to_fail_data { - int reg_access_to_fail; - int reg_access_fail_countdown; -}; - -static const int syv682x_port = 1; - -static void syv682x_test_after(void *data) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - ARG_UNUSED(data); - - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - - /* Clear the mock read/write functions */ - i2c_common_emul_set_read_func(emul, NULL, NULL); - i2c_common_emul_set_write_func(emul, NULL, NULL); - - /* Don't fail on any register access */ - i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); - i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); -} - -ZTEST(ppc_syv682c, test_syv682x_board_is_syv682c) -{ - zassert_true(syv682x_board_is_syv682c(syv682x_port), NULL); -} - -static void check_control_1_default_init(uint8_t control_1) -{ - /* - * During init, when not in dead battery mode, the driver should - * configure the high-voltage channel as sink but leave the power path - * disabled. The driver should set the current limits according to - * configuration. - */ - int ilim; - - zassert_true(control_1 & SYV682X_CONTROL_1_PWR_ENB, - "Default init, but power path enabled"); - ilim = (control_1 & SYV682X_HV_ILIM_MASK) >> SYV682X_HV_ILIM_BIT_SHIFT; - zassert_equal(ilim, CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM, - "Default init, but HV current limit set to %d", ilim); - zassert_false(control_1 & SYV682X_CONTROL_1_HV_DR, - "Default init, but source mode selected"); - zassert_true(control_1 & SYV682X_CONTROL_1_CH_SEL, - "Default init, but 5V power path selected"); -} - -ZTEST(ppc_syv682c, test_syv682x_init) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - const struct device *gpio_dev = - DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios)); - uint8_t reg; - int ilim; - - /* - * With a dead battery, the device powers up sinking VBUS, and the - * driver should keep that going.. - */ - zassert_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG, - SYV682X_CONTROL_1_CH_SEL), NULL); - syv682x_emul_set_condition(emul, SYV682X_STATUS_VSAFE_5V, - SYV682X_CONTROL_4_NONE); - zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - NULL); - zassert_true(reg & SYV682X_CONTROL_1_CH_SEL, - "Dead battery init, but CH_SEL set to 5V power path"); - zassert_false(reg & - (SYV682X_CONTROL_1_PWR_ENB | SYV682X_CONTROL_1_HV_DR), - "Dead battery init, but CONTROL_1 is 0x%x", reg); - zassert_false(ppc_is_sourcing_vbus(syv682x_port), - "Dead battery init, but VBUS source enabled"); - - /* With VBUS at vSafe0V, init should set the default configuration. */ - zassert_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG, - SYV682X_CONTROL_1_PWR_ENB), NULL); - syv682x_emul_set_condition(emul, SYV682X_STATUS_VSAFE_0V, - SYV682X_CONTROL_4_NONE); - zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - NULL); - check_control_1_default_init(reg); - - /* With sink disabled, init should do the same thing. */ - zassert_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG, - SYV682X_CONTROL_1_CH_SEL), NULL); - syv682x_emul_set_condition(emul, SYV682X_STATUS_VSAFE_0V, - SYV682X_CONTROL_4_NONE); - zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - NULL); - check_control_1_default_init(reg); - - /* - * Any init sequence should also disable the FRS GPIO, set the 5V - * current limit according to configuration, set over-current, over- - * voltage, and discharge parameters appropriately, and enable CC lines. - */ - zassert_equal(gpio_emul_output_get(gpio_dev, GPIO_USB_C1_FRS_EN_PORT), - 0, "FRS enabled, but FRS GPIO not asserted"); - ilim = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; - zassert_equal(ilim, CONFIG_PLATFORM_EC_USB_PD_PULLUP, - "Default init, but 5V current limit set to %d", ilim); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_2_REG, ®), - NULL); - zassert_equal(reg, (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) | - (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT) | - (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT), - "Default init, but CONTROL_2 is 0x%x", reg); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_3_REG, ®), - NULL); - zassert_equal(reg, (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) | - SYV682X_RVS_MASK, - "Default init, but CONTROL_3 is 0x%x", reg); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - NULL); - zassert_equal(reg & ~SYV682X_CONTROL_4_INT_MASK, - SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS, - "Default init, but CONTROL_4 is 0x%x", reg); - - /* Disable the power path again. */ - zassert_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG, - SYV682X_CONTROL_1_PWR_ENB), NULL); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - -} - -ZTEST(ppc_syv682c, test_syv682x_vbus_enable) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - uint8_t reg; - - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - zassert_not_equal(reg & SYV682X_CONTROL_1_PWR_ENB, - SYV682X_CONTROL_1_PWR_ENB, "VBUS sourcing disabled"); - zassert_false(ppc_is_sourcing_vbus(syv682x_port), - "PPC sourcing VBUS at beginning of test"); - - zassert_ok(ppc_vbus_source_enable(syv682x_port, true), - "VBUS enable failed"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, - "VBUS sourcing disabled"); - zassert_true(ppc_is_sourcing_vbus(syv682x_port), - "PPC is not sourcing VBUS after VBUS enabled"); -} - -ZTEST(ppc_syv682c, test_syv682x_interrupt) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - uint8_t reg; - - zassert_ok(ppc_vbus_source_enable(syv682x_port, true), - "VBUS enable failed"); - /* An OC event less than 100 ms should not cause VBUS to turn off. */ - syv682x_emul_set_condition(emul, SYV682X_STATUS_OC_5V, - SYV682X_CONTROL_4_NONE); - msleep(50); - zassert_true(ppc_is_sourcing_vbus(syv682x_port), - "PPC is not sourcing VBUS after 50 ms OC"); - /* But one greater than 100 ms should. */ - msleep(60); - zassert_false(ppc_is_sourcing_vbus(syv682x_port), - "PPC is sourcing VBUS after 100 ms OC"); - - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - /* - * TODO(b/190519131): Organize the tests to be more hermetic and avoid - * the following issue: The driver triggers overcurrent protection. If - * overcurrent protection is triggered 3 times, the TC won't turn the - * port back on without a detach. This could frustrate efforts to test - * the TC. - */ - - /* - * A TSD event should cause the driver to disable source and sink paths. - * (The device will have already physically disabled them.) The state of - * the sink path is not part of the driver's API. - */ - zassert_ok(ppc_vbus_source_enable(syv682x_port, true), - "Source enable failed"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_TSD, - SYV682X_CONTROL_4_NONE); - msleep(1); - zassert_false(ppc_is_sourcing_vbus(syv682x_port), - "PPC is sourcing power after TSD"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - - /* An OVP event should cause the driver to disable the source path. */ - zassert_ok(ppc_vbus_source_enable(syv682x_port, true), - "Source enable failed"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_OVP, - SYV682X_CONTROL_4_NONE); - msleep(1); - zassert_false(ppc_is_sourcing_vbus(syv682x_port), - "PPC is sourcing power after OVP"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - - /* - * A high-voltage OC while sinking should cause the driver to try to - * re-enable the sink path until the OC count limit is reached, at which - * point the driver should leave it disabled. - */ - zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), - "Sink enable failed"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_OC_HV, - SYV682X_CONTROL_4_NONE); - msleep(1); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, - "Power path disabled after HV_OC handled"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_OC_HV, - SYV682X_CONTROL_4_NONE); - /* Alert GPIO doesn't change so wait for delayed syv682x interrupt */ - msleep(15); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, - "Power path disabled after HV_OC handled"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_OC_HV, - SYV682X_CONTROL_4_NONE); - /* Alert GPIO doesn't change so wait for delayed syv682x interrupt */ - msleep(15); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, - SYV682X_CONTROL_1_PWR_ENB, - "Power path enabled after HV_OC handled 3 times"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - - /* - * A VCONN OC event less than 100 ms should not cause the driver to turn - * VCONN off. - */ - ppc_set_vconn(syv682x_port, true); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_VCONN_OCP); - msleep(1); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_true(reg & - (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), - "VCONN disabled after initial VCONN OC"); - msleep(50); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_true(reg & - (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), - "VCONN disabled after short VCONN OC"); - /* - * But if the event keeps going for over 100 ms continuously, the driver - * should turn VCONN off. - */ - msleep(60); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_false(reg & - (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), - "VCONN enabled after long VCONN OC"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - - /* - * A VCONN over-voltage (VBAT_OVP) event will cause the device to - * disconnect CC and VCONN. The driver should then reinitialize the - * device, which will enable both CC lines but leave VCONN disabled. The - * driver should then run generic CC over-voltage handling. - */ - ppc_set_vconn(syv682x_port, true); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_VBAT_OVP); - msleep(1); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_true(reg & SYV682X_CONTROL_4_CC1_BPS, - "CC1 disabled after handling VBAT_OVP"); - zassert_true(reg & SYV682X_CONTROL_4_CC2_BPS, - "CC2 disabled after handling VBAT_OVP"); - zassert_false(reg & - (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), - "VCONN enabled after handling VBAT_OVP"); - /* - * TODO(b/190519131): The PD stack should generate a Reset in response - * to a CC over-voltage event. There is currently no easy way to test - * that a Hard Reset occurred. - */ - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); -} - -ZTEST(ppc_syv682c, test_syv682x_frs) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - const struct device *gpio_dev = - DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios)); - uint8_t reg; - - /* - * Enabling FRS should enable only the appropriate CC line based on - * polarity. Disabling FRS should enable both CC lines. - */ - ppc_vbus_sink_enable(syv682x_port, true); - zassert_false(ppc_is_sourcing_vbus(syv682x_port), - "PPC is sourcing VBUS after sink enabled"); - ppc_set_polarity(syv682x_port, 0 /* CC1 */); - ppc_set_frs_enable(syv682x_port, true); - zassert_equal(gpio_emul_output_get(gpio_dev, GPIO_USB_C1_FRS_EN_PORT), - 1, "FRS enabled, but FRS GPIO not asserted"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_equal(reg & - (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), - SYV682X_CONTROL_4_CC1_BPS, - "FRS enabled with CC1 polarity, but CONTROL_4 is 0x%x", - reg); - ppc_set_frs_enable(syv682x_port, false); - zassert_equal(gpio_emul_output_get(gpio_dev, GPIO_USB_C1_FRS_EN_PORT), - 0, "FRS disabled, but FRS GPIO not deasserted"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_equal(reg & - (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), - SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS, - "FRS enabled with CC1 polarity, but CONTROL_4 is 0x%x", - reg); - - ppc_set_polarity(syv682x_port, 1 /* CC2 */); - ppc_set_frs_enable(syv682x_port, true); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_4_REG, ®), - "Reading CONTROL_4 failed"); - zassert_equal(reg & - (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), - SYV682X_CONTROL_4_CC2_BPS, - "FRS enabled with CC2 polarity, but CONTROL_4 is 0x%x", - reg); - - /* - * An FRS event when the PPC is Sink should cause the PPC to switch from - * Sink to Source. - */ - syv682x_emul_set_condition(emul, SYV682X_STATUS_FRS, - SYV682X_CONTROL_4_NONE); - msleep(1); - zassert_true(ppc_is_sourcing_vbus(syv682x_port), - "PPC is not sourcing VBUS after FRS signal handled"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); -} - -ZTEST(ppc_syv682c, test_syv682x_source_current_limit) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - uint8_t reg; - int ilim_val; - - zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, - TYPEC_RP_USB), - "Could not set source current limit"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; - zassert_equal(reg & SYV682X_5V_ILIM_MASK, SYV682X_5V_ILIM_1_25, - "Set USB Rp value, but 5V_ILIM is %d", ilim_val); - - zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, - TYPEC_RP_1A5), - "Could not set source current limit"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; - zassert_equal(ilim_val, SYV682X_5V_ILIM_1_75, - "Set 1.5A Rp value, but 5V_ILIM is %d", ilim_val); - - zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, - TYPEC_RP_3A0), - "Could not set source current limit"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - "Reading CONTROL_1 failed"); - ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; - zassert_equal(ilim_val, SYV682X_5V_ILIM_3_30, - "Set 3.0A Rp value, but 5V_ILIM is %d", ilim_val); -} - -ZTEST(ppc_syv682c, test_syv682x_write_busy) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - /* - * Writes should fail while the BUSY bit is set, except that writes to - * CONTROL_4 should succeed on the SYV682C. 1000 reads is intentionally - * many more than the driver is expected to make before reaching its - * timeout. It is not a goal of this test to verify the frequency of - * polling or the exact value of the timeout. - */ - syv682x_emul_set_busy_reads(emul, 1000); - zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port, - TYPEC_RP_USB), - EC_ERROR_TIMEOUT, "SYV682 busy, but write completed"); - zassert_ok(ppc_set_frs_enable(syv682x_port, false), - "Could not set CONTROL_4 while busy on SYV682C"); - - /* - * If the busy bit clears before the driver reaches its timeout, the - * write should succeed. - */ - syv682x_emul_set_busy_reads(emul, 1); - zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port, - TYPEC_RP_USB), 0, - "SYV682 not busy, but write failed"); - - syv682x_emul_set_busy_reads(emul, 0); -} - -ZTEST(ppc_syv682c, test_syv682x_dev_is_connected) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - uint8_t reg; - - zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SRC), - "Could not connect device as source"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_2_REG, ®), - "Reading CONTROL_2 failed"); - zassert_false(reg & SYV682X_CONTROL_2_FDSG, - "Connected as source, but force discharge enabled"); - - zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_DISCONNECTED), - "Could not disconnect device"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_2_REG, ®), - "Reading CONTROL_2 failed"); - zassert_true(reg & SYV682X_CONTROL_2_FDSG, - "Disconnected, but force discharge disabled"); - - zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SNK), - "Could not connect device as source"); -} - -ZTEST(ppc_syv682c, test_syv682x_vbus_sink_enable) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - uint8_t reg; - int ilim; - - /* - * If VBUS source is already enabled, disabling VBUS sink should - * trivially succeed. - */ - zassert_ok(ppc_vbus_source_enable(syv682x_port, true), - "VBUS enable failed"); - zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), - "Sink disable failed"); - - /* - * After enabling VBUS sink, the HV power path should be enabled in sink - * mode with the configured current limit. - */ - zassert_ok(ppc_vbus_source_enable(syv682x_port, false), - "VBUS enable failed"); - zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), - "Sink disable failed"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - NULL); - zassert_true(reg & SYV682X_CONTROL_1_CH_SEL, - "Sink enabled, but CH_SEL set to 5V power path"); - zassert_false(reg & SYV682X_CONTROL_1_PWR_ENB, - "Sink enabled, but power path disabled"); - zassert_false(reg & SYV682X_CONTROL_1_HV_DR, - "Sink enabled, but high-voltage path in source mode"); - ilim = (reg & SYV682X_HV_ILIM_MASK) >> SYV682X_HV_ILIM_BIT_SHIFT; - zassert_equal(ilim, CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM, - "Sink enabled, but HV current limit set to %d", ilim); - - zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), - "Sink disable failed"); - zassert_ok(syv682x_emul_get_reg(emul, SYV682X_CONTROL_1_REG, ®), - NULL); - zassert_true(reg & SYV682X_CONTROL_1_PWR_ENB, - "Sink disabled, but power path enabled"); -} - -ZTEST(ppc_syv682c, test_syv682x_vbus_sink_oc_limit) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), - "Sink enable failed"); - - /* Generate 4 consecutive sink over-current interrupts. After reaching - * this count, the driver should prevent sink enable until the count is - * cleared by sink disable. - */ - for (int i = 0; i < 4; ++i) { - syv682x_emul_set_condition(emul, SYV682X_STATUS_OC_HV, - SYV682X_CONTROL_4_NONE); - msleep(15); - } - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - - zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS, - "VBUS sink enable succeeded after 4 OC events"); - - zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), - "Sink disable failed"); - zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), - "Sink enable failed"); - zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), - "Sink disable failed"); -} - -ZTEST(ppc_syv682c, test_syv682x_set_vconn) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_VBAT_OVP); - zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, - "VBAT OVP, but ppc_set_vconn succeeded"); -} - -ZTEST(ppc_syv682c, test_syv682x_ppc_dump) -{ - /* - * The ppc_dump command should succeed for this port. Don't check the - * output, since there are no standard requirements for that. - */ - const struct ppc_drv *drv = ppc_chips[syv682x_port].drv; - - zassert_ok(drv->reg_dump(syv682x_port), "ppc_dump command failed"); -} - -/* Intercepts I2C reads as a mock. Fails to read for the register at offset - * reg_access_to_fail on read number N, where N is the initial value of - * reg_access_fail_countdown. - */ -static int mock_read_intercept_reg_fail(struct i2c_emul *emul, int reg, - uint8_t *val, int bytes, void *data) -{ - struct reg_to_fail_data *test_data = data; - - if (reg == test_data->reg_access_to_fail) { - test_data->reg_access_fail_countdown--; - if (test_data->reg_access_fail_countdown <= 0) - return -1; - } - return 1; -} - -ZTEST(ppc_syv682c, test_syv682x_i2c_error_status) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - /* Failed STATUS read should cause init to fail. */ - i2c_common_emul_set_read_fail_reg(emul, SYV682X_STATUS_REG); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "STATUS read error, but init succeeded"); - i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); -} - -ZTEST(ppc_syv682c, test_syv682x_i2c_error_control_1) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - const struct ppc_drv *drv = ppc_chips[syv682x_port].drv; - struct reg_to_fail_data reg_fail = { - .reg_access_to_fail = 0, - .reg_access_fail_countdown = 0, - }; - - /* Failed CONTROL_1 read */ - i2c_common_emul_set_read_fail_reg(emul, SYV682X_CONTROL_1_REG); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_1 read error, but init succeeded"); - zassert_not_equal(ppc_vbus_source_enable(syv682x_port, true), - EC_SUCCESS, - "CONTROL_1 read error, but VBUS source enable " - "succeeded"); - zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS, - "CONTROL_1 read error, but VBUS sink enable " - "succeeded"); - zassert_not_equal(ppc_set_vbus_source_current_limit(syv682x_port, - TYPEC_RP_USB), - EC_SUCCESS, - "CONTROL_1 read error, but set current limit " - "succeeded"); - zassert_ok(drv->reg_dump(syv682x_port), - "CONTROL_1 read error, and ppc_dump failed"); - i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); - - /* Init reads CONTROL_1 several times. The 3rd read happens while - * setting the source current limit. Check that init fails when that - * read fails. - */ - i2c_common_emul_set_read_func(emul, &mock_read_intercept_reg_fail, - ®_fail); - reg_fail.reg_access_to_fail = SYV682X_CONTROL_1_REG; - reg_fail.reg_access_fail_countdown = 3; - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_1 read error, but init succeeded"); - i2c_common_emul_set_read_func(emul, NULL, NULL); - - /* Failed CONTROL_1 write */ - i2c_common_emul_set_write_fail_reg(emul, SYV682X_CONTROL_1_REG); - - /* During init, the driver will write CONTROL_1 either to disable all - * power paths (normal case) or to enable the sink path (dead battery - * case). vSafe0V in STATUS is one indication of the normal case. - */ - syv682x_emul_set_condition(emul, SYV682X_STATUS_VSAFE_0V, - SYV682X_CONTROL_4_NONE); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_1 write error, but init succeeded"); - syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, - SYV682X_CONTROL_4_NONE); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_1 write error, but init succeeded"); - - zassert_not_equal(ppc_vbus_source_enable(syv682x_port, true), - EC_SUCCESS, - "CONTROL_1 write error, but VBUS source " - "enable succeeded"); - i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); -} - -ZTEST(ppc_syv682c, test_syv682x_i2c_error_control_2) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - /* Failed CONTROL_2 read */ - i2c_common_emul_set_read_fail_reg(emul, SYV682X_CONTROL_2_REG); - zassert_not_equal(ppc_discharge_vbus(syv682x_port, true), EC_SUCCESS, - "CONTROL_2 read error, but VBUS discharge succeeded"); - i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); - - /* Failed CONTROL_2 write */ - i2c_common_emul_set_write_fail_reg(emul, SYV682X_CONTROL_2_REG); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_2 write error, but init succeeded"); - i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); -} - -ZTEST(ppc_syv682c, test_syv682x_i2c_error_control_3) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - /* Failed CONTROL_3 read */ - i2c_common_emul_set_read_fail_reg(emul, SYV682X_CONTROL_3_REG); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_3 read error, but VBUS discharge succeeded"); - i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); - - /* Failed CONTROL_3 write */ - i2c_common_emul_set_write_fail_reg(emul, SYV682X_CONTROL_3_REG); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_3 write error, but init succeeded"); - i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); -} - -ZTEST(ppc_syv682c, test_syv682x_i2c_error_control_4) -{ - struct i2c_emul *emul = syv682x_emul_get(SYV682X_ORD); - - /* Failed CONTROL_4 read */ - i2c_common_emul_set_read_fail_reg(emul, SYV682X_CONTROL_4_REG); - zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, - "CONTROL_2 read error, but VCONN set succeeded"); - i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); - - /* Failed CONTROL_4 write */ - i2c_common_emul_set_write_fail_reg(emul, SYV682X_CONTROL_4_REG); - zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, - "CONTROL_4 write error, but init succeeded"); - zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, - "CONTROL_4 write error, but VCONN set succeeded"); - i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); -} - -ZTEST_SUITE(ppc_syv682c, drivers_predicate_post_main, NULL, NULL, - syv682x_test_after, NULL); diff --git a/zephyr/test/drivers/src/ppc_syv682x.c b/zephyr/test/drivers/src/ppc_syv682x.c new file mode 100644 index 0000000000..aa08c26745 --- /dev/null +++ b/zephyr/test/drivers/src/ppc_syv682x.c @@ -0,0 +1,804 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/device.h> +#include <zephyr/devicetree/gpio.h> +#include <zephyr/drivers/gpio/gpio_emul.h> +#include <zephyr/drivers/gpio.h> +#include <fff.h> +#include <zephyr/zephyr.h> +#include <ztest.h> +#include <ztest_assert.h> + +#include "emul/emul_common_i2c.h" +#include "emul/emul_syv682x.h" +#include "test/drivers/stubs.h" +#include "syv682x.h" +#include "timer.h" +#include "test/drivers/test_state.h" +#include "test/drivers/utils.h" +#include "usbc_ppc.h" + +#define SYV682X_ORD DT_DEP_ORD(DT_NODELABEL(syv682x_emul)) +#define GPIO_USB_C1_FRS_EN_PATH DT_PATH(named_gpios, usb_c1_frs_en) + +struct ppc_syv682x_fixture { + struct i2c_emul *ppc_emul; + const struct device *frs_en_gpio_port; + int frs_en_gpio_pin; +}; + +/* Configuration for a mock I2C access function that sometimes fails. */ +struct reg_to_fail_data { + int reg_access_to_fail; + int reg_access_fail_countdown; +}; + +static const int syv682x_port = 1; + +static void *syv682x_test_setup(void) +{ + static struct ppc_syv682x_fixture fixture; + + fixture.ppc_emul = syv682x_emul_get(SYV682X_ORD); + zassume_not_null(fixture.ppc_emul, NULL); + fixture.frs_en_gpio_port = + DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios)); + zassume_not_null(fixture.frs_en_gpio_port, NULL); + fixture.frs_en_gpio_pin = DT_GPIO_PIN(GPIO_USB_C1_FRS_EN_PATH, gpios); + + return &fixture; +} + +static void syv682x_test_after(void *data) +{ + struct ppc_syv682x_fixture *fixture = data; + struct i2c_emul *emul = fixture->ppc_emul; + + /* Disable the power path and clear interrupt conditions. */ + zassume_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG, + SYV682X_CONTROL_1_PWR_ENB), + NULL); + syv682x_emul_set_condition(emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_NONE); + + /* Clear the mock read/write functions */ + i2c_common_emul_set_read_func(emul, NULL, NULL); + i2c_common_emul_set_write_func(emul, NULL, NULL); + + /* Don't fail on any register access */ + i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); + i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); +} + +ZTEST_SUITE(ppc_syv682x, drivers_predicate_post_main, syv682x_test_setup, NULL, + syv682x_test_after, NULL); + +ZTEST_F(ppc_syv682x, test_syv682x_board_is_syv682c) +{ + /* + * The SYV682x driver should assume a version-C part in the absence of a + * board override. + */ + zassert_true(syv682x_board_is_syv682c(syv682x_port), NULL); +} + +static void check_control_1_default_init(uint8_t control_1) +{ + /* + * During init, when not in dead battery mode, the driver should + * configure the high-voltage channel as sink but leave the power path + * disabled. The driver should set the current limits according to + * configuration. + */ + int ilim; + + zassert_true(control_1 & SYV682X_CONTROL_1_PWR_ENB, + "Default init, but power path enabled"); + ilim = (control_1 & SYV682X_HV_ILIM_MASK) >> SYV682X_HV_ILIM_BIT_SHIFT; + zassert_equal(ilim, CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM, + "Default init, but HV current limit set to %d", ilim); + zassert_false(control_1 & SYV682X_CONTROL_1_HV_DR, + "Default init, but source mode selected"); + zassert_true(control_1 & SYV682X_CONTROL_1_CH_SEL, + "Default init, but 5V power path selected"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_init_dead_battery) +{ + uint8_t reg; + + /* + * With a dead battery, the device powers up sinking VBUS, and the + * driver should keep that going. + */ + zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + SYV682X_CONTROL_1_CH_SEL), + NULL); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_5V, + SYV682X_CONTROL_4_NONE); + zassert_ok(ppc_init(syv682x_port), "PPC init failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + NULL); + zassert_true(reg & SYV682X_CONTROL_1_CH_SEL, + "Dead battery init, but CH_SEL set to 5V power path"); + zassert_false(reg & (SYV682X_CONTROL_1_PWR_ENB | + SYV682X_CONTROL_1_HV_DR), + "Dead battery init, but CONTROL_1 is 0x%x", reg); + zassert_false(ppc_is_sourcing_vbus(syv682x_port), + "Dead battery init, but VBUS source enabled"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_init_vsafe0v) +{ + uint8_t reg; + + /* With VBUS at vSafe0V, init should set the default configuration. */ + zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + SYV682X_CONTROL_1_PWR_ENB), + NULL); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V, + SYV682X_CONTROL_4_NONE); + zassert_ok(ppc_init(syv682x_port), "PPC init failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + NULL); + check_control_1_default_init(reg); +} + +ZTEST_F(ppc_syv682x, test_syv682x_init_sink_disabled) +{ + uint8_t reg; + + /* With sink disabled, init should do the same thing. */ + zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + SYV682X_CONTROL_1_CH_SEL), + NULL); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V, + SYV682X_CONTROL_4_NONE); + zassert_ok(ppc_init(syv682x_port), "PPC init failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + NULL); + check_control_1_default_init(reg); +} + +ZTEST_F(ppc_syv682x, test_syv682x_init_common) +{ + uint8_t reg; + int ilim; + + zassert_ok(ppc_init(syv682x_port), "PPC init failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + NULL); + + /* + * Any init sequence should also disable the FRS GPIO, set the 5V + * current limit according to configuration, set over-current, over- + * voltage, and discharge parameters appropriately, and enable CC lines. + */ + zassert_equal(gpio_emul_output_get(this->frs_en_gpio_port, + this->frs_en_gpio_pin), + 0, "FRS enabled, but FRS GPIO not asserted"); + ilim = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; + zassert_equal(ilim, CONFIG_PLATFORM_EC_USB_PD_PULLUP, + "Default init, but 5V current limit set to %d", ilim); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG, + ®), + NULL); + zassert_equal(reg, + (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) | + (SYV682X_DSG_RON_200_OHM + << SYV682X_DSG_RON_SHIFT) | + (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT), + "Default init, but CONTROL_2 is 0x%x", reg); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_3_REG, + ®), + NULL); + zassert_equal(reg, + (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) | + SYV682X_RVS_MASK, + "Default init, but CONTROL_3 is 0x%x", reg); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + NULL); + zassert_equal(reg & ~SYV682X_CONTROL_4_INT_MASK, + SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS, + "Default init, but CONTROL_4 is 0x%x", reg); +} + +ZTEST_F(ppc_syv682x, test_syv682x_vbus_source_enable) +{ + uint8_t reg; + + zassert_ok(ppc_vbus_source_enable(syv682x_port, true), + "VBUS enable failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, + "VBUS sourcing enabled but power path disabled"); + zassert_true(ppc_is_sourcing_vbus(syv682x_port), + "PPC is not sourcing VBUS after VBUS enabled"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_vbus_source_disable) +{ + zassert_ok(ppc_vbus_source_enable(syv682x_port, false), + "VBUS disable failed"); + zassert_false(ppc_is_sourcing_vbus(syv682x_port), + "PPC sourcing VBUS after disable"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_interrupt_source_oc) +{ + zassume_ok(ppc_vbus_source_enable(syv682x_port, true), + "VBUS enable failed"); + /* An OC event less than 100 ms should not cause VBUS to turn off. */ + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_5V, + SYV682X_CONTROL_4_NONE); + msleep(50); + zassert_true(ppc_is_sourcing_vbus(syv682x_port), + "PPC is not sourcing VBUS after 50 ms OC"); + /* But one greater than 100 ms should. */ + msleep(60); + zassert_false(ppc_is_sourcing_vbus(syv682x_port), + "PPC is sourcing VBUS after 100 ms OC"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_interrupt_tsd) +{ + /* + * A TSD event should cause the driver to disable source and sink paths. + * (The device will have already physically disabled them.) The state of + * the sink path is not part of the driver's API. + */ + zassume_ok(ppc_vbus_source_enable(syv682x_port, true), + "Source enable failed"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_TSD, + SYV682X_CONTROL_4_NONE); + msleep(1); + zassert_false(ppc_is_sourcing_vbus(syv682x_port), + "PPC is sourcing power after TSD"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_ovp) +{ + /* An OVP event should cause the driver to disable the source path. */ + zassume_ok(ppc_vbus_source_enable(syv682x_port, true), + "Source enable failed"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OVP, + SYV682X_CONTROL_4_NONE); + msleep(1); + zassert_false(ppc_is_sourcing_vbus(syv682x_port), + "PPC is sourcing power after OVP"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_hv_oc) +{ + uint8_t reg; + + /* + * A high-voltage OC while sinking should cause the driver to try to + * re-enable the sink path until the OC count limit is reached, at which + * point the driver should leave it disabled. + */ + zassume_ok(ppc_vbus_sink_enable(syv682x_port, true), + "Sink enable failed"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + SYV682X_CONTROL_4_NONE); + msleep(1); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, + "Power path disabled after HV_OC handled"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + SYV682X_CONTROL_4_NONE); + /* Alert GPIO doesn't change so wait for delayed syv682x interrupt */ + msleep(15); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, + "Power path disabled after HV_OC handled"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + SYV682X_CONTROL_4_NONE); + /* Alert GPIO doesn't change so wait for delayed syv682x interrupt */ + msleep(15); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, + SYV682X_CONTROL_1_PWR_ENB, + "Power path enabled after HV_OC handled 3 times"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_oc) +{ + uint8_t reg; + + /* + * A VCONN OC event less than 100 ms should not cause the driver to turn + * VCONN off. + */ + ppc_set_vconn(syv682x_port, true); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_VCONN_OCP); + msleep(1); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + "Reading CONTROL_4 failed"); + zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 | + SYV682X_CONTROL_4_VCONN2), + "VCONN disabled after initial VCONN OC"); + msleep(50); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + "Reading CONTROL_4 failed"); + zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 | + SYV682X_CONTROL_4_VCONN2), + "VCONN disabled after short VCONN OC"); + /* + * But if the event keeps going for over 100 ms continuously, the driver + * should turn VCONN off. + */ + msleep(60); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + "Reading CONTROL_4 failed"); + zassert_false(reg & (SYV682X_CONTROL_4_VCONN1 | + SYV682X_CONTROL_4_VCONN2), + "VCONN enabled after long VCONN OC"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_ov) +{ + uint8_t reg; + + /* + * A VCONN over-voltage (VBAT_OVP) event will cause the device to + * disconnect CC and VCONN. The driver should then reinitialize the + * device, which will enable both CC lines but leave VCONN disabled. The + * driver should then run generic CC over-voltage handling. + */ + ppc_set_vconn(syv682x_port, true); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_VBAT_OVP); + msleep(1); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + "Reading CONTROL_4 failed"); + zassert_true(reg & SYV682X_CONTROL_4_CC1_BPS, + "CC1 disabled after handling VBAT_OVP"); + zassert_true(reg & SYV682X_CONTROL_4_CC2_BPS, + "CC2 disabled after handling VBAT_OVP"); + zassert_false(reg & (SYV682X_CONTROL_4_VCONN1 | + SYV682X_CONTROL_4_VCONN2), + "VCONN enabled after handling VBAT_OVP"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_frs_enable) +{ + const struct device *gpio_dev = + DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios)); + uint8_t reg; + + /* + * Enabling FRS should enable only the appropriate CC line based on + * polarity. Disabling FRS should enable both CC lines. + */ + ppc_vbus_sink_enable(syv682x_port, true); + zassume_false(ppc_is_sourcing_vbus(syv682x_port), + "PPC is sourcing VBUS after sink enabled"); + ppc_set_polarity(syv682x_port, 0 /* CC1 */); + ppc_set_frs_enable(syv682x_port, true); + zassert_equal(gpio_emul_output_get(gpio_dev, this->frs_en_gpio_pin), 1, + "FRS enabled, but FRS GPIO not asserted"); + zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + "Reading CONTROL_4 failed"); + zassert_equal( + reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), + SYV682X_CONTROL_4_CC1_BPS, + "FRS enabled with CC1 polarity, but CONTROL_4 is 0x%x", reg); +} + +ZTEST_F(ppc_syv682x, test_syv682x_frs_disable) +{ + const struct device *gpio_dev = + DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios)); + uint8_t reg; + + ppc_vbus_sink_enable(syv682x_port, true); + zassume_false(ppc_is_sourcing_vbus(syv682x_port), + "PPC is sourcing VBUS after sink enabled"); + ppc_set_polarity(syv682x_port, 0 /* CC1 */); + + ppc_set_frs_enable(syv682x_port, false); + zassert_equal(gpio_emul_output_get(gpio_dev, this->frs_en_gpio_pin), 0, + "FRS disabled, but FRS GPIO not deasserted"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, + ®), + "Reading CONTROL_4 failed"); + zassert_equal( + reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), + SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS, + "FRS disabled with CC1 polarity, but CONTROL_4 is 0x%x", reg); +} + +ZTEST_F(ppc_syv682x, test_syv682x_frs_trigger) +{ + /* + * An FRS event when the PPC is Sink should cause the PPC to switch from + * Sink to Source. + */ + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_FRS, + SYV682X_CONTROL_4_NONE); + msleep(1); + zassert_true(ppc_is_sourcing_vbus(syv682x_port), + "PPC is not sourcing VBUS after FRS signal handled"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_NONE); +} + +ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_usb_default) +{ + uint8_t reg; + int ilim_val; + + zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, + TYPEC_RP_USB), + "Could not set source current limit"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; + zassert_equal(reg & SYV682X_5V_ILIM_MASK, SYV682X_5V_ILIM_1_25, + "Set USB Rp value, but 5V_ILIM is %d", ilim_val); +} + +ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_1500ma) +{ + uint8_t reg; + int ilim_val; + + zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, + TYPEC_RP_1A5), + "Could not set source current limit"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; + zassert_equal(ilim_val, SYV682X_5V_ILIM_1_75, + "Set 1.5A Rp value, but 5V_ILIM is %d", ilim_val); +} + +ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_3000ma) +{ + uint8_t reg; + int ilim_val; + + zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, + TYPEC_RP_3A0), + "Could not set source current limit"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + "Reading CONTROL_1 failed"); + ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; + zassert_equal(ilim_val, SYV682X_5V_ILIM_3_30, + "Set 3.0A Rp value, but 5V_ILIM is %d", ilim_val); +} + +ZTEST_F(ppc_syv682x, test_syv682x_write_busy) +{ + /* + * Writes should fail while the BUSY bit is set, except that writes to + * CONTROL_4 should succeed on the SYV682C. 1000 reads is intentionally + * many more than the driver is expected to make before reaching its + * timeout. It is not a goal of this test to verify the frequency of + * polling or the exact value of the timeout. + */ + syv682x_emul_set_busy_reads(this->ppc_emul, 1000); + zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port, + TYPEC_RP_USB), + EC_ERROR_TIMEOUT, "SYV682 busy, but write completed"); + zassert_ok(ppc_set_frs_enable(syv682x_port, false), + "Could not set CONTROL_4 while busy on SYV682C"); + + /* + * If the busy bit clears before the driver reaches its timeout, the + * write should succeed. + */ + syv682x_emul_set_busy_reads(this->ppc_emul, 1); + zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port, + TYPEC_RP_USB), + 0, "SYV682 not busy, but write failed"); + + syv682x_emul_set_busy_reads(this->ppc_emul, 0); +} + +ZTEST_F(ppc_syv682x, test_syv682x_dev_is_connected) +{ + uint8_t reg; + + zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SRC), + "Could not connect device as source"); + zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG, + ®), + "Reading CONTROL_2 failed"); + zassert_false(reg & SYV682X_CONTROL_2_FDSG, + "Connected as source, but force discharge enabled"); + + zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_DISCONNECTED), + "Could not disconnect device"); + zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG, + ®), + "Reading CONTROL_2 failed"); + zassert_true(reg & SYV682X_CONTROL_2_FDSG, + "Disconnected, but force discharge disabled"); + + zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SNK), + "Could not connect device as source"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_enable_trivial) +{ + /* + * If VBUS source is already enabled, disabling VBUS sink should + * trivially succeed. + */ + zassume_ok(ppc_vbus_source_enable(syv682x_port, true), + "VBUS enable failed"); + zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), + "Sink disable failed"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_enable_power_path) +{ + uint8_t reg; + int ilim; + + /* + * After enabling VBUS sink, the HV power path should be enabled in sink + * mode with the configured current limit. + */ + zassume_ok(ppc_vbus_source_enable(syv682x_port, false), + "VBUS enable failed"); + zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), + "Sink disable failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + NULL); + zassert_true(reg & SYV682X_CONTROL_1_CH_SEL, + "Sink enabled, but CH_SEL set to 5V power path"); + zassert_false(reg & SYV682X_CONTROL_1_PWR_ENB, + "Sink enabled, but power path disabled"); + zassert_false(reg & SYV682X_CONTROL_1_HV_DR, + "Sink enabled, but high-voltage path in source mode"); + ilim = (reg & SYV682X_HV_ILIM_MASK) >> SYV682X_HV_ILIM_BIT_SHIFT; + zassert_equal(ilim, CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_HV_ILIM, + "Sink enabled, but HV current limit set to %d", ilim); +} + +ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_disable) +{ + uint8_t reg; + + zassume_ok(ppc_vbus_source_enable(syv682x_port, false), + "VBUS enable failed"); + zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), + "Sink disable failed"); + + zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), + "Sink disable failed"); + zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + ®), + NULL); + zassert_true(reg & SYV682X_CONTROL_1_PWR_ENB, + "Sink disabled, but power path enabled"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_oc_limit) +{ + zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), + "Sink enable failed"); + + /* Generate 4 consecutive sink over-current interrupts. After reaching + * this count, the driver should prevent sink enable until the count is + * cleared by sink disable. + */ + for (int i = 0; i < 4; ++i) { + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + SYV682X_CONTROL_4_NONE); + msleep(15); + } + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_NONE); + + zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS, + "VBUS sink enable succeeded after 4 OC events"); + + zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), + "Sink disable failed"); + zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), + "Sink enable failed"); + zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), + "Sink disable failed"); +} + +ZTEST_F(ppc_syv682x, test_syv682x_set_vconn) +{ + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_VBAT_OVP); + zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, + "VBAT OVP, but ppc_set_vconn succeeded"); +} + +ZTEST(ppc_syv682x, test_syv682x_ppc_dump) +{ + /* + * The ppc_dump command should succeed for this port. Don't check the + * output, since there are no standard requirements for that. + */ + const struct ppc_drv *drv = ppc_chips[syv682x_port].drv; + + zassert_ok(drv->reg_dump(syv682x_port), "ppc_dump command failed"); +} + +/* Intercepts I2C reads as a mock. Fails to read for the register at offset + * reg_access_to_fail on read number N, where N is the initial value of + * reg_access_fail_countdown. + */ +static int mock_read_intercept_reg_fail(struct i2c_emul *emul, int reg, + uint8_t *val, int bytes, void *data) +{ + struct reg_to_fail_data *test_data = data; + + if (reg == test_data->reg_access_to_fail) { + test_data->reg_access_fail_countdown--; + if (test_data->reg_access_fail_countdown <= 0) + return -1; + } + return 1; +} + +ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_status) +{ + /* Failed STATUS read should cause init to fail. */ + i2c_common_emul_set_read_fail_reg(this->ppc_emul, SYV682X_STATUS_REG); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "STATUS read error, but init succeeded"); + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); +} + +ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1) +{ + const struct ppc_drv *drv = ppc_chips[syv682x_port].drv; + struct reg_to_fail_data reg_fail = { + .reg_access_to_fail = 0, + .reg_access_fail_countdown = 0, + }; + + /* Failed CONTROL_1 read */ + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + SYV682X_CONTROL_1_REG); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_1 read error, but init succeeded"); + zassert_not_equal(ppc_vbus_source_enable(syv682x_port, true), + EC_SUCCESS, + "CONTROL_1 read error, but VBUS source enable " + "succeeded"); + zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS, + "CONTROL_1 read error, but VBUS sink enable " + "succeeded"); + zassert_not_equal(ppc_set_vbus_source_current_limit(syv682x_port, + TYPEC_RP_USB), + EC_SUCCESS, + "CONTROL_1 read error, but set current limit " + "succeeded"); + zassert_ok(drv->reg_dump(syv682x_port), + "CONTROL_1 read error, and ppc_dump failed"); + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); + + /* Init reads CONTROL_1 several times. The 3rd read happens while + * setting the source current limit. Check that init fails when that + * read fails. + */ + i2c_common_emul_set_read_func(this->ppc_emul, + &mock_read_intercept_reg_fail, ®_fail); + reg_fail.reg_access_to_fail = SYV682X_CONTROL_1_REG; + reg_fail.reg_access_fail_countdown = 3; + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_1 read error, but init succeeded"); + i2c_common_emul_set_read_func(this->ppc_emul, NULL, NULL); + + /* Failed CONTROL_1 write */ + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + SYV682X_CONTROL_1_REG); + + /* During init, the driver will write CONTROL_1 either to disable all + * power paths (normal case) or to enable the sink path (dead battery + * case). vSafe0V in STATUS is one indication of the normal case. + */ + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V, + SYV682X_CONTROL_4_NONE); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_1 write error, but init succeeded"); + syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + SYV682X_CONTROL_4_NONE); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_1 write error, but init succeeded"); + + zassert_not_equal(ppc_vbus_source_enable(syv682x_port, true), + EC_SUCCESS, + "CONTROL_1 write error, but VBUS source " + "enable succeeded"); + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); +} + +ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_2) +{ + /* Failed CONTROL_2 read */ + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + SYV682X_CONTROL_2_REG); + zassert_not_equal(ppc_discharge_vbus(syv682x_port, true), EC_SUCCESS, + "CONTROL_2 read error, but VBUS discharge succeeded"); + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); + + /* Failed CONTROL_2 write */ + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + SYV682X_CONTROL_2_REG); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_2 write error, but init succeeded"); + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); +} + +ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_3) +{ + /* Failed CONTROL_3 read */ + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + SYV682X_CONTROL_3_REG); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_3 read error, but VBUS discharge succeeded"); + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); + + /* Failed CONTROL_3 write */ + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + SYV682X_CONTROL_3_REG); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_3 write error, but init succeeded"); + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); +} + +ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_4) +{ + /* Failed CONTROL_4 read */ + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + SYV682X_CONTROL_4_REG); + zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, + "CONTROL_2 read error, but VCONN set succeeded"); + i2c_common_emul_set_read_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); + + /* Failed CONTROL_4 write */ + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + SYV682X_CONTROL_4_REG); + zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, + "CONTROL_4 write error, but init succeeded"); + zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, + "CONTROL_4 write error, but VCONN set succeeded"); + i2c_common_emul_set_write_fail_reg(this->ppc_emul, + I2C_COMMON_EMUL_NO_FAIL_REG); +} diff --git a/zephyr/test/drivers/src/watchdog.c b/zephyr/test/drivers/src/watchdog.c index d66ee77bd8..8b91247f12 100644 --- a/zephyr/test/drivers/src/watchdog.c +++ b/zephyr/test/drivers/src/watchdog.c @@ -23,6 +23,8 @@ #include "watchdog.h" #include "test/drivers/test_state.h" +#define wdt DEVICE_DT_GET(DT_CHOSEN(cros_ec_watchdog)) + /** * @brief Default watchdog timeout plus some time for it to expire. */ @@ -47,6 +49,12 @@ static void watchdog_before(void *state) ARG_UNUSED(state); set_test_runner_tid(); wdt_warning_triggered = false; + + /* When shuffling need watchdog initialized and running + * for other tests. + */ + (void) watchdog_init(); + (void) wdt_setup(wdt, 0); } /** @@ -72,12 +80,7 @@ ZTEST(watchdog, test_watchdog_init) { int retval = EC_SUCCESS; - /* Test successful initialization */ - retval = watchdog_init(); - zassert_equal(EC_SUCCESS, retval, "Expected EC_SUCCESS, returned %d.", - retval); - - /* Test already initialized */ + /* Test already initialized (initialized in watchdog_before) */ retval = watchdog_init(); zassert_equal(-ENOMEM, retval, "Expected -ENOMEM, returned %d.", retval); @@ -120,6 +123,9 @@ ZTEST(watchdog, test_watchdog_reload) */ ZTEST(watchdog, test_wdt_warning_handler) { + /* Feed the dog so timer is reset */ + watchdog_reload(); + zassert_false(wdt_warning_triggered, "Watchdog timer expired early."); k_timer_start(&ktimer, K_MSEC(DEFAULT_WDT_EXPIRY_MS), K_NO_WAIT); diff --git a/zephyr/zmake/tests/test_version.py b/zephyr/zmake/tests/test_version.py index e56e13a519..9e00473752 100644 --- a/zephyr/zmake/tests/test_version.py +++ b/zephyr/zmake/tests/test_version.py @@ -133,7 +133,6 @@ EXPECTED_HEADER = ( '#define CROS_EC_VERSION32 "trogdor_v2.6.1004-cmsis:0dead0,"\n' '#define BUILDER "toukmond@pokey"\n' '#define DATE "2021-06-28 03:18:53"\n' - '#define CROS_FWID_MISSING_STR "CROS_FWID_MISSING"\n' "#define CROS_FWID32 CROS_FWID_MISSING_STR\n" ) HEADER_VERSION_STR_STATIC = "trogdor_v2.6.0-STATIC" @@ -143,7 +142,6 @@ EXPECTED_HEADER_STATIC = ( '#define CROS_EC_VERSION32 "trogdor_v2.6.0-STATIC"\n' '#define BUILDER "reproducible@build"\n' '#define DATE "STATIC_VERSION_DATE"\n' - '#define CROS_FWID_MISSING_STR "CROS_FWID_MISSING"\n' "#define CROS_FWID32 CROS_FWID_MISSING_STR\n" ) diff --git a/zephyr/zmake/zmake/output_packers.py b/zephyr/zmake/zmake/output_packers.py index c09c6cc84c..78ee7649e6 100644 --- a/zephyr/zmake/zmake/output_packers.py +++ b/zephyr/zmake/zmake/output_packers.py @@ -237,7 +237,7 @@ class MchpPacker(BinmanPacker): """Packer for RO/RW image to generate a .bin build using FMAP. This expects that the build is setup to generate a - zephyr.npcx.bin for the RO image, which should be packed using + zephyr.mchp.bin for the RO image, which should be packed using Microchip's loader format. """ diff --git a/zephyr/zmake/zmake/version.py b/zephyr/zmake/zmake/version.py index 2333ad46df..5ac060f23b 100644 --- a/zephyr/zmake/zmake/version.py +++ b/zephyr/zmake/zmake/version.py @@ -162,7 +162,6 @@ def write_version_header(version_str, output_path, static=False): add_def("BUILDER", "{}@{}".format(getpass.getuser(), platform.node())) add_def("DATE", datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")) - add_def("CROS_FWID_MISSING_STR", "CROS_FWID_MISSING") # TODO(b/198475757): Add zmake support for getting CROS_FWID32 add_def_unquoted("CROS_FWID32", "CROS_FWID_MISSING_STR") |