5 files changed, 43 insertions, 12 deletions
diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h
index da0f215d0a..3d241a1984 100644
--- a/chip/npcx/registers-npcx5.h
+++ b/chip/npcx/registers-npcx5.h
@@ -125,6 +125,10 @@ enum {
 
 #define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
 
+/* pin-mux for JTAG */
+#define NPCX_DEVALT5_NJEN1_EN		1
+#define NPCX_DEVALT5_NJEN0_EN		2
+
 /* pin-mux for I2C */
 #define NPCX_DEVALT2_I2C0_0_SL		0
 #define NPCX_DEVALT2_I2C0_1_SL		1
diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h
index d7fd73aecc..cbd9be30dc 100644
--- a/chip/npcx/registers-npcx7.h
+++ b/chip/npcx/registers-npcx7.h
@@ -209,6 +209,10 @@ enum {
 #define NPCX_DEVALT6_I2C5_1_SL		6
 #define NPCX_DEVALT6_I2C4_1_SL		7
 
+/* pin-mux for JTAG */
+#define NPCX_DEVALT5_NJEN1_EN		1
+#define NPCX_DEVALT5_NJEN0_EN		2
+
 /* pin-mux for ADC */
 #define NPCX_DEVALTF_ADC5_SL		0
 #define NPCX_DEVALTF_ADC6_SL		1
diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h
index ef66bfcfc1..296f1af25c 100644
--- a/chip/npcx/registers-npcx9.h
+++ b/chip/npcx/registers-npcx9.h
@@ -256,6 +256,12 @@ enum {
 #define NPCX_SMBSEL_SMB5SEL		5
 #define NPCX_SMBSEL_SMB6SEL		6
 
+/* pin-mux for JTAG */
+#define NPCX_JEN_CTL1			REG8(NPCX_SCFG_BASE_ADDR + 0x120)
+#define NPCX_JEN_CTL1_JEN_EN_FIELD	FIELD(0, 4)
+#define NPCX_JEN_CTL1_JEN_EN_DIS	0x06
+#define NPCX_JEN_CTL1_JEN_EN_ENA	0x09
+
 /* SMB enumeration: I2C port definitions. */
 enum {
 	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index aaf7f0477e..bacfe31982 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -456,8 +456,6 @@ enum {
 
 /* pin-mux for JTAG */
 #define NPCX_DEVALT5_TRACE_EN            0
-#define NPCX_DEVALT5_NJEN1_EN            1
-#define NPCX_DEVALT5_NJEN0_EN            2
 
 /* pin-mux for ADC */
 #define NPCX_DEVALT6_ADC0_SL             0
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 3f6f5d9ccd..ce8851b18f 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -40,6 +40,9 @@
 #define CHIP_REV_STR_SIZE    6
 #endif
 
+/*  Legacy SuperI/O Configuration D register offset */
+#define SIOCFD_REG_OFFSET    0x2D
+
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
@@ -781,6 +784,22 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 #endif
 }
 
+#ifndef CONFIG_ENABLE_JTAG_SELECTION
+static void system_disable_host_sel_jtag(void)
+{
+	int data;
+
+	/* Enable Core-to-Host Modules Access */
+	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+	/* Clear SIOCFD.JEN0_HSL to disable JTAG0 */
+	data = sib_read_reg(SIO_OFFSET, SIOCFD_REG_OFFSET);
+	data &= ~0x80;
+	sib_write_reg(SIO_OFFSET, SIOCFD_REG_OFFSET, data);
+	/* Disable Core-to-Host Modules Access */
+	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+}
+#endif
+
 void chip_pre_init(void)
 {
 	/* Setting for fixing JTAG issue */
@@ -807,21 +826,21 @@ void chip_pre_init(void)
 	 * This is the workaround to disable the JTAG0 which is enabled
 	 * accidentally by a special key combination.
 	 */
+#if NPCX_FAMILY_VERSION < NPCX_FAMILY_NPCX9
 	if (!IS_BIT_SET(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN)) {
-		int data;
 		/* Set DEVALT5.nJEN0_EN to disable JTAG0 */
 		SET_BIT(NPCX_DEVALT(5), NPCX_DEVALT5_NJEN0_EN);
-		/* Enable Core-to-Host Modules Access */
-		SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-		/* Clear SIOCFD.JEN0_HSL to disable JTAG0 */
-		data = sib_read_reg(SIO_OFFSET, 0x2D);
-		data &= ~0x80;
-		sib_write_reg(SIO_OFFSET, 0x2D, data);
-		/* Disable Core-to-Host Modules Access */
-		CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
+		system_disable_host_sel_jtag();
+	}
+#else
+	if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) ==
+		      NPCX_JEN_CTL1_JEN_EN_ENA) {
+		SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD,
+			  NPCX_JEN_CTL1_JEN_EN_DIS);
+		system_disable_host_sel_jtag();
 	}
 #endif
-
+#endif
 }
 
 void system_pre_init(void)