diff options
| -rw-r--r-- | chip/stm32/config_chip.h | 3 | ||||
| -rw-r--r-- | chip/stm32/memory_regions.inc | 16 | ||||
| -rw-r--r-- | chip/stm32/usb.c | 3 | ||||
| -rw-r--r-- | chip/stm32/usb_hw.h | 4 | ||||
| -rw-r--r-- | core/cortex-m/ec.lds.S | 13 | ||||
| -rw-r--r-- | core/cortex-m0/ec.lds.S | 13 |
6 files changed, 22 insertions, 30 deletions
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 1d7f95115d..4a2f686e6b 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -79,6 +79,9 @@ #include "config_std_internal_flash.h" #endif +/* Additional special purpose regions (USB RAM and other special SRAMs) */ +#define CONFIG_CHIP_MEMORY_REGIONS + /* System stack size */ #if defined(CHIP_VARIANT_STM32F05X) #define CONFIG_STACK_SIZE 768 diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc new file mode 100644 index 0000000000..eaa9fc71f3 --- /dev/null +++ b/chip/stm32/memory_regions.inc @@ -0,0 +1,16 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifdef CONFIG_USB_RAM_SIZE +REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \ + CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2) +#endif /* CONFIG_USB_RAM_SIZE */ +#ifdef CHIP_VARIANT_STM32H7X3 +REGION(itcm, wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */ +REGION(dtcm, rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */ +REGION(ahb, rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */ +REGION(ahb4, rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */ +REGION(backup, rw, 0x38000000, 0x01000) /* Backup RAM: 4kB */ +#endif /* CHIP_VARIANT_STM32H7X3 */ diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index 560ca3da2d..c8768823d7 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -90,8 +90,7 @@ const uint8_t usb_string_desc[] = { }; /* Endpoint table in USB controller RAM */ -struct stm32_endpoint btable_ep[USB_EP_COUNT] - __attribute__((section(".usb_ram.btable"))); +struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable; /* Control endpoint (EP0) buffers */ static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h index 0ba7fb369d..fb7b5d546b 100644 --- a/chip/stm32/usb_hw.h +++ b/chip/stm32/usb_hw.h @@ -29,7 +29,7 @@ typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint; extern usb_uint __usb_ram_start[]; /* Attribute to define a buffer variable in USB RAM */ -#define __usb_ram __attribute__((section(".usb_ram.data"))) +#define __usb_ram __attribute__((section(".usb_ram.99_data"))) struct stm32_endpoint { volatile usb_uint tx_addr; @@ -41,7 +41,7 @@ struct stm32_endpoint { extern struct stm32_endpoint btable_ep[]; /* Attribute to put the endpoint table in USB RAM */ -#define __usb_btable __attribute__((section(".usb_ram.btable"))) +#define __usb_btable __attribute__((section(".usb_ram.00_btable"))) /* Read from USB RAM into a usb_setup_packet struct */ struct usb_setup_packet; diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index c3ed3c9c80..25ce2ef221 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -52,11 +52,6 @@ MEMORY ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(SECTION), \ LENGTH = FW_SIZE(SECTION) #endif /* CONFIG_EXTERNAL_STORAGE */ -#ifdef CONFIG_USB_RAM_SIZE - USB_RAM (rw) : \ - ORIGIN = CONFIG_USB_RAM_BASE, \ - LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2 -#endif #ifdef CONFIG_CHIP_MEMORY_REGIONS #define REGION(name, attr, start, size) \ name(attr) : ORIGIN = (start), LENGTH = (size) @@ -376,14 +371,6 @@ SECTIONS __image_size = __hey_flash_used; #endif -#ifdef CONFIG_USB_RAM_SIZE - .usb_ram (NOLOAD) : { - __usb_ram_start = .; - . = ALIGN(8); - *(.usb_ram.btable) - *(.usb_ram.data) - } > USB_RAM -#endif #ifdef CONFIG_CHIP_MEMORY_REGIONS #define REGION(name, attr, start, size) \ .name(NOLOAD) : { \ diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S index ce1bcdbc70..86f5494797 100644 --- a/core/cortex-m0/ec.lds.S +++ b/core/cortex-m0/ec.lds.S @@ -25,11 +25,6 @@ MEMORY #endif FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE -#ifdef CONFIG_USB_RAM_SIZE - USB_RAM (rw) : \ - ORIGIN = CONFIG_USB_RAM_BASE, \ - LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2 -#endif #ifdef CONFIG_CHIP_MEMORY_REGIONS #define REGION(name, attr, start, size) \ name(attr) : ORIGIN = (start), LENGTH = (size) @@ -246,14 +241,6 @@ SECTIONS __image_size = __hey_flash_used; -#ifdef CONFIG_USB_RAM_SIZE - .usb_ram (NOLOAD) : { - __usb_ram_start = .; - . = ALIGN(8); - *(.usb_ram.btable) - *(.usb_ram.data) - } > USB_RAM -#endif #ifdef CONFIG_CHIP_MEMORY_REGIONS #define REGION(name, attr, start, size) \ .name(NOLOAD) : { \ |