diff options
| -rw-r--r-- | chip/stm32/system.c | 9 | ||||
| -rw-r--r-- | core/cortex-m/cpu.c | 6 | ||||
| -rw-r--r-- | core/cortex-m/cpu.h | 2 |
3 files changed, 14 insertions, 3 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 1a9da8c3a4..1f5f9c9108 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -373,6 +373,15 @@ void system_reset(int flags) chip_save_reset_flags(save_flags); +#ifdef CONFIG_ARMV7M_CACHE + /* + * Disable caches (D-cache is also flushed and invalidated) + * so changes that lives in cache are saved in memory now. + * Any subsequent writes will be done immediately. + */ + cpu_disable_caches(); +#endif + if (flags & SYSTEM_RESET_HARD) { #ifdef CONFIG_SOFTWARE_PANIC uint32_t reason, info; diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c index 96ac96a016..7c31892c18 100644 --- a/core/cortex-m/cpu.c +++ b/core/cortex-m/cpu.c @@ -50,16 +50,16 @@ void cpu_enable_caches(void) } } -static void cpu_sysjump_cache(void) +void cpu_disable_caches(void) { /* * Disable the I-cache and the D-cache - * The I-cache will be invalidated after the sysjump if needed + * The I-cache will be invalidated after the reboot/sysjump if needed * (e.g after a flash update). */ cpu_clean_invalidate_dcache(); CPU_NVIC_CCR &= ~(CPU_NVIC_CCR_ICACHE | CPU_NVIC_CCR_DCACHE); asm volatile("dsb; isb"); } -DECLARE_HOOK(HOOK_SYSJUMP, cpu_sysjump_cache, HOOK_PRIO_LAST); +DECLARE_HOOK(HOOK_SYSJUMP, cpu_disable_caches, HOOK_PRIO_LAST); #endif /* CONFIG_ARMV7M_CACHE */ diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index 5f7dd02801..0b03302bfc 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -74,6 +74,8 @@ enum { void cpu_init(void); /* Enable the CPU I-cache and D-cache if they are not already enabled */ void cpu_enable_caches(void); +/* Disable the CPU I-cache and D-cache */ +void cpu_disable_caches(void); /* Invalidate the D-cache */ void cpu_invalidate_dcache(void); /* Clean and Invalidate the D-cache to the Point of Coherency */ |