diff options
| -rw-r--r-- | zephyr/include/cros/nuvoton/npcx9.dtsi | 15 | ||||
| -rw-r--r-- | zephyr/projects/brya/boards/arm/brya/Kconfig.board | 15 | ||||
| -rw-r--r-- | zephyr/projects/brya/boards/arm/brya/Kconfig.defconfig | 10 | ||||
| -rw-r--r-- | zephyr/projects/brya/boards/arm/brya/board.cmake | 6 | ||||
| -rw-r--r-- | zephyr/projects/brya/boards/arm/brya/brya.dts | 43 | ||||
| -rw-r--r-- | zephyr/projects/brya/boards/arm/brya/brya_defconfig | 54 | ||||
| -rw-r--r-- | zephyr/projects/brya/brya/CMakeLists.txt | 12 | ||||
| -rw-r--r-- | zephyr/projects/brya/brya/gpio.dts | 40 | ||||
| -rw-r--r-- | zephyr/projects/brya/brya/include/gpio_map.h | 36 | ||||
| -rw-r--r-- | zephyr/projects/brya/brya/prj.conf | 26 | ||||
| -rw-r--r-- | zephyr/projects/brya/brya/zmake.yaml | 11 |
11 files changed, 268 insertions, 0 deletions
diff --git a/zephyr/include/cros/nuvoton/npcx9.dtsi b/zephyr/include/cros/nuvoton/npcx9.dtsi new file mode 100644 index 0000000000..de492d3306 --- /dev/null +++ b/zephyr/include/cros/nuvoton/npcx9.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021 The Chromium OS Authors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include <cros/nuvoton/npcx.dtsi> + +/ { + soc { + + }; +}; diff --git a/zephyr/projects/brya/boards/arm/brya/Kconfig.board b/zephyr/projects/brya/boards/arm/brya/Kconfig.board new file mode 100644 index 0000000000..8add483941 --- /dev/null +++ b/zephyr/projects/brya/boards/arm/brya/Kconfig.board @@ -0,0 +1,15 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# "BOARD" below refers to a Zephyr board, which does not have a 1:1 +# mapping with the Chrome OS concept of a board. By Zephyr's +# conventions, we'll still call it "BOARD_*" to make this more +# applicable to be upstreamed, even though this code is shared by all +# projects using Brya baseboard. +config BOARD_BRYA + bool "Google Brya Baseboard" + depends on SOC_NPCX9M3F + # NPCX doesn't actually have enough ram for coverage, but this will + # allow generating initial 0 line coverage. + select HAS_COVERAGE_SUPPORT diff --git a/zephyr/projects/brya/boards/arm/brya/Kconfig.defconfig b/zephyr/projects/brya/boards/arm/brya/Kconfig.defconfig new file mode 100644 index 0000000000..e4de179311 --- /dev/null +++ b/zephyr/projects/brya/boards/arm/brya/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +if BOARD_BRYA + +config BOARD + default "brya" + +endif # BOARD_BRYA diff --git a/zephyr/projects/brya/boards/arm/brya/board.cmake b/zephyr/projects/brya/boards/arm/brya/board.cmake new file mode 100644 index 0000000000..19469c1ca4 --- /dev/null +++ b/zephyr/projects/brya/boards/arm/brya/board.cmake @@ -0,0 +1,6 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.packed.bin) + diff --git a/zephyr/projects/brya/boards/arm/brya/brya.dts b/zephyr/projects/brya/boards/arm/brya/brya.dts new file mode 100644 index 0000000000..219484aaa0 --- /dev/null +++ b/zephyr/projects/brya/boards/arm/brya/brya.dts @@ -0,0 +1,43 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/dts-v1/; + +#include <cros/nuvoton/npcx9.dtsi> +#include <dt-bindings/gpio_defines.h> +#include <nuvoton/npcx9m3f.dtsi> + +/ { + model = "Google Brya Baseboard"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,flash = &flash0; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + }; + + named-pwms { + compatible = "named-pwms"; + }; + + named-adc-channels { + compatible = "named-adc-channels"; + }; + + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; +}; diff --git a/zephyr/projects/brya/boards/arm/brya/brya_defconfig b/zephyr/projects/brya/boards/arm/brya/brya_defconfig new file mode 100644 index 0000000000..b206544d1c --- /dev/null +++ b/zephyr/projects/brya/boards/arm/brya/brya_defconfig @@ -0,0 +1,54 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Kernel Configuration +CONFIG_SOC_SERIES_NPCX9=y + +# Platform Configuration +CONFIG_SOC_NPCX9M3F=y +CONFIG_BOARD_BRYA=y + +# Enable NPCX firmware header generator +CONFIG_NPCX_HEADER=y +CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y +CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y +CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Pinmux Driver +CONFIG_PINMUX=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# PLL configuration +CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000 +CONFIG_CLOCK_NPCX_APB1_PRESCALER=6 +CONFIG_CLOCK_NPCX_APB2_PRESCALER=6 +CONFIG_CLOCK_NPCX_APB3_PRESCALER=6 +CONFIG_CLOCK_NPCX_APB4_PRESCALER=6 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000 + +# Code RAM base for NPCX9M3F +CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10080000 +CONFIG_CROS_EC_RAM_BASE=0x200c0000 +CONFIG_CROS_EC_DATA_RAM_SIZE=0x0000f800 +CONFIG_CROS_EC_RAM_SIZE=0x0000f800 + +CONFIG_FLASH_SIZE=512 +CONFIG_CROS_EC_RO_MEM_OFF=0x0 +CONFIG_CROS_EC_RO_SIZE=0x40000 +CONFIG_CROS_EC_RW_MEM_OFF=0x40000 +CONFIG_CROS_EC_RW_SIZE=0x40000 diff --git a/zephyr/projects/brya/brya/CMakeLists.txt b/zephyr/projects/brya/brya/CMakeLists.txt new file mode 100644 index 0000000000..f60730951b --- /dev/null +++ b/zephyr/projects/brya/brya/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +set(BOARD_ROOT "${CMAKE_CURRENT_LIST_DIR}/..") + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(brya) + +zephyr_include_directories(include) diff --git a/zephyr/projects/brya/brya/gpio.dts b/zephyr/projects/brya/brya/gpio.dts new file mode 100644 index 0000000000..df56757d20 --- /dev/null +++ b/zephyr/projects/brya/brya/gpio.dts @@ -0,0 +1,40 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-gpios { + compatible = "named-gpios"; + + lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + label = "GPIO_LID_OPEN"; + }; + + power_btn: power_btn { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + label = "GPIO_POWER_BUTTON"; + }; + + wp_l { + gpios = <&gpioa 1 GPIO_INPUT>; + enum-name = "GPIO_WP_L"; + label = "EC_WP_ODL"; + }; + + ec_chg_led_y_c1 { + gpios = <&gpioc 3 GPIO_OUT_LOW>; + enum-name = "GPIO_EC_CHG_LED_Y_C1"; + label = "EC_CHG_LED_Y_C1"; + }; + + ec_chg_led_b_c1 { + gpios = <&gpioc 4 GPIO_OUT_LOW>; + enum-name = "GPIO_EC_CHG_LED_B_C1"; + label = "EC_CHG_LED_B_C1"; + }; + }; +}; diff --git a/zephyr/projects/brya/brya/include/gpio_map.h b/zephyr/projects/brya/brya/include/gpio_map.h new file mode 100644 index 0000000000..5c2f4ea23e --- /dev/null +++ b/zephyr/projects/brya/brya/include/gpio_map.h @@ -0,0 +1,36 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_GPIO_MAP_H +#define __ZEPHYR_GPIO_MAP_H + +#include <devicetree.h> +#include <gpio_signal.h> + +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_WP_L GPIO_UNIMPLEMENTED + +/* + * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items. + * + * Each GPIO_INT requires three parameters: + * gpio_signal - The enum gpio_signal for the interrupt gpio + * interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH) + * handler - The platform/ec interrupt handler. + * + * Ensure that this files includes all necessary headers to declare all + * referenced handler functions. + * + * For example, one could use the follow definition: + * #define EC_CROS_GPIO_INTERRUPTS \ + * GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print) + */ +#define EC_CROS_GPIO_INTERRUPTS \ + GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt) \ + GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH, \ + power_button_interrupt) \ + GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt) + +#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/brya/brya/prj.conf b/zephyr/projects/brya/brya/prj.conf new file mode 100644 index 0000000000..bb1384b46f --- /dev/null +++ b/zephyr/projects/brya/brya/prj.conf @@ -0,0 +1,26 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_SHIMMED_TASKS=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_LTO=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y + +# TODO(b/188605676): bring these features up +CONFIG_CROS_KB_RAW_NPCX=n +CONFIG_PLATFORM_EC_ADC=n +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_BOARD_VERSION=n +CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=n +CONFIG_PLATFORM_EC_HOSTCMD=y +CONFIG_PLATFORM_EC_I2C=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_VBOOT=n +CONFIG_PLATFORM_EC_VBOOT_HASH=n diff --git a/zephyr/projects/brya/brya/zmake.yaml b/zephyr/projects/brya/brya/zmake.yaml new file mode 100644 index 0000000000..686f175267 --- /dev/null +++ b/zephyr/projects/brya/brya/zmake.yaml @@ -0,0 +1,11 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +board: brya +dts-overlays: + - gpio.dts +supported-zephyr-versions: + - v2.5 +toolchain: coreboot-sdk +output-type: npcx |