diff options
l--------- | board/ryu_p4p5/Makefile | 1 | ||||
-rw-r--r-- | board/ryu_p4p5/board.c | 677 | ||||
-rw-r--r-- | board/ryu_p4p5/board.h | 201 | ||||
-rw-r--r-- | board/ryu_p4p5/build.mk | 13 | ||||
-rw-r--r-- | board/ryu_p4p5/ec.tasklist | 28 | ||||
-rw-r--r-- | board/ryu_p4p5/gpio.inc | 144 | ||||
-rw-r--r-- | board/ryu_p4p5/usb_pd_config.h | 227 | ||||
-rw-r--r-- | board/ryu_p4p5/usb_pd_policy.c | 139 | ||||
-rw-r--r-- | common/lb_common.c | 4 | ||||
-rw-r--r-- | test/build.mk | 1 | ||||
-rwxr-xr-x | util/flash_ec | 1 |
11 files changed, 1434 insertions, 2 deletions
diff --git a/board/ryu_p4p5/Makefile b/board/ryu_p4p5/Makefile new file mode 120000 index 0000000000..94aaae2c4d --- /dev/null +++ b/board/ryu_p4p5/Makefile @@ -0,0 +1 @@ +../../Makefile
\ No newline at end of file diff --git a/board/ryu_p4p5/board.c b/board/ryu_p4p5/board.c new file mode 100644 index 0000000000..976c546de2 --- /dev/null +++ b/board/ryu_p4p5/board.c @@ -0,0 +1,677 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* ryu board configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "battery.h" +#include "case_closed_debug.h" +#include "charge_manager.h" +#include "charge_ramp.h" +#include "charge_state.h" +#include "charger.h" +#include "common.h" +#include "console.h" +#include "ec_version.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "i2c.h" +#include "inductive_charging.h" +#include "lid_switch.h" +#include "power.h" +#include "power_button.h" +#include "registers.h" +#include "spi.h" +#include "task.h" +#include "usb.h" +#include "usb_pd.h" +#include "usb_pd_config.h" +#include "usb_spi.h" +#include "usb-stm32f3.h" +#include "usb-stream.h" +#include "usart-stm32f3.h" +#include "util.h" +#include "pi3usb9281.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) + +/* Default input current limit when VBUS is present */ +#define DEFAULT_CURR_LIMIT 500 /* mA */ + +/* VBUS too low threshold */ +#define VBUS_LOW_THRESHOLD_MV 4600 + +/* Input current error margin */ +#define IADP_ERROR_MARGIN_MA 100 + +static int charge_current_limit; + +static void vbus_log(void) +{ + CPRINTS("VBUS %d", gpio_get_level(GPIO_CHGR_ACOK)); +} +DECLARE_DEFERRED(vbus_log); + +void vbus_evt(enum gpio_signal signal) +{ + struct charge_port_info charge; + int vbus_level = gpio_get_level(signal); + + /* + * If VBUS is low, or VBUS is high and we are not outputting VBUS + * ourselves, then update the VBUS supplier. + */ + if (!vbus_level || !gpio_get_level(GPIO_USBC_5V_EN)) { + charge.voltage = USB_BC12_CHARGE_VOLTAGE; + charge.current = vbus_level ? DEFAULT_CURR_LIMIT : 0; + charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0, &charge); + } + + hook_call_deferred(vbus_log, 0); + if (task_start_called()) + task_wake(TASK_ID_PD); +} + +/* Wait 200ms after a charger is detected to debounce pin contact order */ +#define USB_CHG_DEBOUNCE_DELAY_MS 200 +/* + * Wait 100ms after reset, before re-enabling attach interrupt, so that the + * spurious attach interrupt from certain ports is ignored. + */ +#define USB_CHG_RESET_DELAY_MS 100 + +void usb_charger_task(void) +{ + int device_type, charger_status; + struct charge_port_info charge; + int type; + charge.voltage = USB_BC12_CHARGE_VOLTAGE; + + while (1) { + /* Read interrupt register to clear */ + pi3usb9281_get_interrupts(0); + + /* Set device type */ + device_type = pi3usb9281_get_device_type(0); + charger_status = pi3usb9281_get_charger_status(0); + + /* Debounce pin plug order if we detect a charger */ + if (device_type || PI3USB9281_CHG_STATUS_ANY(charger_status)) { + msleep(USB_CHG_DEBOUNCE_DELAY_MS); + + /* Trigger chip reset to refresh detection registers */ + pi3usb9281_reset(0); + /* Clear possible disconnect interrupt */ + pi3usb9281_get_interrupts(0); + /* Mask attach interrupt */ + pi3usb9281_set_interrupt_mask(0, + 0xff & + ~PI3USB9281_INT_ATTACH); + /* Re-enable interrupts */ + pi3usb9281_enable_interrupts(0); + msleep(USB_CHG_RESET_DELAY_MS); + + /* Clear possible attach interrupt */ + pi3usb9281_get_interrupts(0); + /* Re-enable attach interrupt */ + pi3usb9281_set_interrupt_mask(0, 0xff); + + /* Re-read ID registers */ + device_type = pi3usb9281_get_device_type(0); + charger_status = pi3usb9281_get_charger_status(0); + } + + if (PI3USB9281_CHG_STATUS_ANY(charger_status)) + type = CHARGE_SUPPLIER_PROPRIETARY; + else if (device_type & PI3USB9281_TYPE_CDP) + type = CHARGE_SUPPLIER_BC12_CDP; + else if (device_type & PI3USB9281_TYPE_DCP) + type = CHARGE_SUPPLIER_BC12_DCP; + else if (device_type & PI3USB9281_TYPE_SDP) + type = CHARGE_SUPPLIER_BC12_SDP; + else + type = CHARGE_SUPPLIER_OTHER; + + /* Attachment: decode + update available charge */ + if (device_type || PI3USB9281_CHG_STATUS_ANY(charger_status)) { + charge.current = pi3usb9281_get_ilim(device_type, + charger_status); + charge_manager_update_charge(type, 0, &charge); + } else { /* Detachment: update available charge to 0 */ + charge.current = 0; + charge_manager_update_charge( + CHARGE_SUPPLIER_PROPRIETARY, + 0, + &charge); + charge_manager_update_charge( + CHARGE_SUPPLIER_BC12_CDP, + 0, + &charge); + charge_manager_update_charge( + CHARGE_SUPPLIER_BC12_DCP, + 0, + &charge); + charge_manager_update_charge( + CHARGE_SUPPLIER_BC12_SDP, + 0, + &charge); + charge_manager_update_charge( + CHARGE_SUPPLIER_OTHER, + 0, + &charge); + } + + /* notify host of power info change */ + /* pd_send_host_event(PD_EVENT_POWER_CHANGE); */ + + /* Wait for interrupt */ + task_wait_event(-1); + } +} + +void usb_evt(enum gpio_signal signal) +{ + task_wake(TASK_ID_USB_CHG); +} + +#include "gpio_list.h" + +const void *const usb_strings[] = { + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Ryu debug"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("EC_PD"), + [USB_STR_AP_STREAM_NAME] = USB_STRING_DESC("AP"), + [USB_STR_SH_STREAM_NAME] = USB_STRING_DESC("SH"), +}; + +BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); + +/* + * Define AP and SH console forwarding queues and associated USART and USB + * stream endpoints. + */ + +QUEUE_CONFIG(ap_usart_to_usb, 64, uint8_t); +QUEUE_CONFIG(usb_to_ap_usart, 64, uint8_t); +QUEUE_CONFIG(sh_usart_to_usb, 64, uint8_t); +QUEUE_CONFIG(usb_to_sh_usart, 64, uint8_t); + +struct usb_stream_config const usb_ap_stream; +struct usb_stream_config const usb_sh_stream; + +USART_CONFIG(usart1, + usart1_hw, + 115200, + ap_usart_to_usb, + usb_to_ap_usart, + usb_ap_stream.consumer, + usb_ap_stream.producer) + +USART_CONFIG(usart3, + usart3_hw, + 115200, + sh_usart_to_usb, + usb_to_sh_usart, + usb_sh_stream.consumer, + usb_sh_stream.producer) + +#define AP_USB_STREAM_RX_SIZE 16 +#define AP_USB_STREAM_TX_SIZE 16 + +USB_STREAM_CONFIG(usb_ap_stream, + USB_IFACE_AP_STREAM, + USB_STR_AP_STREAM_NAME, + USB_EP_AP_STREAM, + AP_USB_STREAM_RX_SIZE, + AP_USB_STREAM_TX_SIZE, + usb_to_ap_usart, + ap_usart_to_usb, + usart1.consumer, + usart1.producer) + +#define SH_USB_STREAM_RX_SIZE 16 +#define SH_USB_STREAM_TX_SIZE 16 + +USB_STREAM_CONFIG(usb_sh_stream, + USB_IFACE_SH_STREAM, + USB_STR_SH_STREAM_NAME, + USB_EP_SH_STREAM, + SH_USB_STREAM_RX_SIZE, + SH_USB_STREAM_TX_SIZE, + usb_to_sh_usart, + sh_usart_to_usb, + usart3.consumer, + usart3.producer) + +/* Initialize board. */ +static void board_init(void) +{ + struct charge_port_info charge_none, charge_vbus; + + /* Initialize all pericom charge suppliers to 0 */ + charge_none.voltage = USB_BC12_CHARGE_VOLTAGE; + charge_none.current = 0; + charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY, + 0, + &charge_none); + charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, 0, &charge_none); + charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, 0, &charge_none); + charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, 0, &charge_none); + charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, 0, &charge_none); + + /* Initialize VBUS supplier based on whether or not VBUS is present */ + charge_vbus.voltage = USB_BC12_CHARGE_VOLTAGE; + charge_vbus.current = DEFAULT_CURR_LIMIT; + if (gpio_get_level(GPIO_CHGR_ACOK)) + charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0, + &charge_vbus); + else + charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0, + &charge_none); + + /* Enable pericom BC1.2 interrupts. */ + gpio_enable_interrupt(GPIO_USBC_BC12_INT_L); + pi3usb9281_set_interrupt_mask(0, 0xff); + pi3usb9281_enable_interrupts(0); + + /* + * Determine recovery mode is requested by the power, volup, and + * voldown buttons being pressed. + */ + if (power_button_signal_asserted() && + !gpio_get_level(GPIO_BTN_VOLD_L) && + !gpio_get_level(GPIO_BTN_VOLU_L)) + host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY); + + /* + * Initialize AP and SH console forwarding USARTs and queues. + */ + queue_init(&ap_usart_to_usb); + queue_init(&usb_to_ap_usart); + queue_init(&sh_usart_to_usb); + queue_init(&usb_to_sh_usart); + usart_init(&usart1); + usart_init(&usart3); + + /* + * Enable CC lines after all GPIO have been initialized. Note, it is + * important that this is enabled after the CC_DEVICE_ODL lines are + * set low to specify device mode. + */ + gpio_set_level(GPIO_USBC_CC_EN, 1); + + /* Enable interrupts on VBUS transitions. */ + gpio_enable_interrupt(GPIO_CHGR_ACOK); + + /* + * TODO(crosbug.com/p/38689) Workaround for PMIC issue on P5. + * remove when P5 are de-commissioned. + * We are re-using EXTINT1 for the new power sequencing workaround + * this is killing the base closing detection on P5 + * we won't charge it. + */ + if (board_get_version() == 5) + gpio_enable_interrupt(GPIO_HPD_IN); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +/* power signal list. Must match order of enum power_signal. */ +const struct power_signal_info power_signal_list[] = { + {GPIO_AP_HOLD, 1, "AP_HOLD"}, + {GPIO_AP_IN_SUSPEND, 1, "SUSPEND_ASSERTED"}, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +/* + * TODO(crosbug.com/p/38689) Workaround for MAX77620 PMIC EN_PP3300 issue. + * remove when P5 are de-commissioned. + */ +void pp1800_on_off_evt(enum gpio_signal signal) +{ + int level = gpio_get_level(signal); + gpio_set_level(GPIO_EN_PP3300_RSVD, level); +} + +/* ADC channels */ +const struct adc_t adc_channels[] = { + /* Vbus sensing. Converted to mV, /10 voltage divider. */ + [ADC_VBUS] = {"VBUS", 30000, 4096, 0, STM32_AIN(0)}, + /* USB PD CC lines sensing. Converted to mV (3000mV/4096). */ + [ADC_CC1_PD] = {"CC1_PD", 3000, 4096, 0, STM32_AIN(1)}, + [ADC_CC2_PD] = {"CC2_PD", 3000, 4096, 0, STM32_AIN(3)}, + /* Charger current sensing. Converted to mA. */ + [ADC_IADP] = {"IADP", 7500, 4096, 0, STM32_AIN(8)}, + [ADC_IBAT] = {"IBAT", 37500, 4096, 0, STM32_AIN(13)}, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* Charge supplier priority: lower number indicates higher priority. */ +const int supplier_priority[] = { + [CHARGE_SUPPLIER_PD] = 0, + [CHARGE_SUPPLIER_TYPEC] = 1, + [CHARGE_SUPPLIER_PROPRIETARY] = 1, + [CHARGE_SUPPLIER_BC12_DCP] = 1, + [CHARGE_SUPPLIER_BC12_CDP] = 2, + [CHARGE_SUPPLIER_BC12_SDP] = 3, + [CHARGE_SUPPLIER_OTHER] = 3, + [CHARGE_SUPPLIER_VBUS] = 4 +}; +BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT); + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + {"master", I2C_PORT_MASTER, 100, + GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA}, + {"slave", I2C_PORT_SLAVE, 100, + GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA}, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* TODO(crosbug.com/p/38333) remove me */ +#define GPIO_USBC_SS1_USB_MODE_L GPIO_USBC_MUX_CONF0 +#define GPIO_USBC_SS2_USB_MODE_L GPIO_USBC_MUX_CONF1 +#define GPIO_USBC_SS_EN_L GPIO_USBC_MUX_CONF2 + +void p4_board_set_usb_mux(int port, enum typec_mux mux, int polarity) +{ + /* reset everything */ + gpio_set_level(GPIO_USBC_SS_EN_L, 1); + gpio_set_level(GPIO_USBC_DP_MODE_L, 1); + gpio_set_level(GPIO_USBC_DP_POLARITY, 1); + gpio_set_level(GPIO_USBC_SS1_USB_MODE_L, 1); + gpio_set_level(GPIO_USBC_SS2_USB_MODE_L, 1); + + if (mux == TYPEC_MUX_NONE) + /* everything is already disabled, we can return */ + return; + + if (mux == TYPEC_MUX_USB || mux == TYPEC_MUX_DOCK) { + /* USB 3.0 uses 2 superspeed lanes */ + gpio_set_level(polarity ? GPIO_USBC_SS2_USB_MODE_L : + GPIO_USBC_SS1_USB_MODE_L, 0); + } + + if (mux == TYPEC_MUX_DP || mux == TYPEC_MUX_DOCK) { + /* DP uses available superspeed lanes (x2 or x4) */ + gpio_set_level(GPIO_USBC_DP_POLARITY, polarity); + gpio_set_level(GPIO_USBC_DP_MODE_L, 0); + } + /* switch on superspeed lanes */ + gpio_set_level(GPIO_USBC_SS_EN_L, 0); +} + +void board_set_usb_mux(int port, enum typec_mux mux, int polarity) +{ + if (board_get_version() < 5) { + /* P4/EVT or older boards */ + /* TODO(crosbug.com/p/38333) remove this */ + p4_board_set_usb_mux(port, mux, polarity); + return; + } + + /* reset everything */ + gpio_set_level(GPIO_USBC_MUX_CONF0, 0); + gpio_set_level(GPIO_USBC_MUX_CONF1, 0); + gpio_set_level(GPIO_USBC_MUX_CONF2, 0); + + if (mux == TYPEC_MUX_NONE) + /* everything is already disabled, we can return */ + return; + + gpio_set_level(GPIO_USBC_MUX_CONF0, polarity); + + if (mux == TYPEC_MUX_USB || mux == TYPEC_MUX_DOCK) + /* USB 3.0 uses 2 superspeed lanes */ + gpio_set_level(GPIO_USBC_MUX_CONF2, 1); + + if (mux == TYPEC_MUX_DP || mux == TYPEC_MUX_DOCK) + /* DP uses available superspeed lanes (x2 or x4) */ + gpio_set_level(GPIO_USBC_MUX_CONF1, 1); +} + +int p4_board_get_usb_mux(int port, const char **dp_str, const char **usb_str) +{ + int has_ss = !gpio_get_level(GPIO_USBC_SS_EN_L); + int has_usb = !gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) || + !gpio_get_level(GPIO_USBC_SS2_USB_MODE_L); + int has_dp = !gpio_get_level(GPIO_USBC_DP_MODE_L); + + if (has_dp) + *dp_str = gpio_get_level(GPIO_USBC_DP_POLARITY) ? "DP2" : "DP1"; + else + *dp_str = NULL; + + if (has_usb) + *usb_str = gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) ? + "USB2" : "USB1"; + else + *usb_str = NULL; + + return has_ss; +} + +int board_get_usb_mux(int port, const char **dp_str, const char **usb_str) +{ + int has_usb, has_dp, polarity; + + if (board_get_version() < 5) { + /* P4/EVT or older boards */ + /* TODO(crosbug.com/p/38333) remove this */ + return p4_board_get_usb_mux(port, dp_str, usb_str); + } + + has_usb = gpio_get_level(GPIO_USBC_MUX_CONF2); + has_dp = gpio_get_level(GPIO_USBC_MUX_CONF1); + polarity = gpio_get_level(GPIO_USBC_MUX_CONF0); + + if (has_dp) + *dp_str = polarity ? "DP2" : "DP1"; + else + *dp_str = NULL; + + if (has_usb) + *usb_str = polarity ? "USB2" : "USB1"; + else + *usb_str = NULL; + + return has_dp || has_usb; +} + +/** + * Discharge battery when on AC power for factory test. + */ +int board_discharge_on_ac(int enable) +{ + return charger_discharge_on_ac(enable); +} + +int extpower_is_present(void) +{ + return gpio_get_level(GPIO_CHGR_ACOK); +} + +void usb_board_connect(void) +{ + gpio_set_level(GPIO_USB_PU_EN_L, 0); +} + +void usb_board_disconnect(void) +{ + gpio_set_level(GPIO_USB_PU_EN_L, 1); +} + +/* Charge manager callback function, called on delayed override timeout */ +void board_charge_manager_override_timeout(void) +{ + /* TODO: Implement me! */ +} +DECLARE_DEFERRED(board_charge_manager_override_timeout); + +/** + * Set active charge port -- only one port can be active at a time. + * + * @param charge_port Charge port to enable. + * + * Returns EC_SUCCESS if charge port is accepted and made active, + * EC_ERROR_* otherwise. + */ +int board_set_active_charge_port(int charge_port) +{ + int ret = EC_SUCCESS; + /* check if we are source vbus on that port */ + int source = gpio_get_level(GPIO_USBC_5V_EN); + + if (charge_port >= 0 && charge_port < PD_PORT_COUNT && source) { + CPRINTS("Port %d is not a sink, skipping enable", charge_port); + charge_port = CHARGE_PORT_NONE; + ret = EC_ERROR_INVAL; + } + if (charge_port == CHARGE_PORT_NONE) { + /* Disable charging */ + charge_set_input_current_limit(0); + } + + return ret; +} + +/** + * Set the charge limit based upon desired maximum. + * + * @param charge_ma Desired charge limit (mA). + */ +void board_set_charge_limit(int charge_ma) +{ + int rv; + + charge_current_limit = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); + rv = charge_set_input_current_limit(charge_current_limit); + if (rv < 0) + CPRINTS("Failed to set input current limit for PD"); +} + +/** + * Return whether ramping is allowed for given supplier + */ +int board_is_ramp_allowed(int supplier) +{ + return supplier == CHARGE_SUPPLIER_BC12_DCP || + supplier == CHARGE_SUPPLIER_BC12_SDP || + supplier == CHARGE_SUPPLIER_BC12_CDP || + supplier == CHARGE_SUPPLIER_PROPRIETARY; +} + +/** + * Return the maximum allowed input current + */ +int board_get_ramp_current_limit(int supplier, int sup_curr) +{ + switch (supplier) { + case CHARGE_SUPPLIER_BC12_DCP: + return 2000; + case CHARGE_SUPPLIER_BC12_SDP: + return 1000; + case CHARGE_SUPPLIER_BC12_CDP: + case CHARGE_SUPPLIER_PROPRIETARY: + return sup_curr; + default: + return 500; + } +} + +/** + * Return if board is consuming full amount of input current + */ +int board_is_consuming_full_charge(void) +{ + return adc_read_channel(ADC_IADP) >= charge_current_limit - + IADP_ERROR_MARGIN_MA; +} + +/** + * Return if VBUS is sagging low enough that we should stop ramping + */ +int board_is_vbus_too_low(enum chg_ramp_vbus_state ramp_state) +{ + return adc_read_channel(ADC_VBUS) < VBUS_LOW_THRESHOLD_MV; +} + +/* + * Enable and disable SPI for case closed debugging. This forces the AP into + * reset while SPI is enabled, thus preventing contention on the SPI interface. + */ +void usb_spi_board_enable(struct usb_spi_config const *config) +{ + /* Place AP into reset */ + gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0); + + /* Configure SPI GPIOs */ + gpio_config_module(MODULE_SPI_MASTER, 1); + gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_OUT_HIGH); + + /* Set all four SPI pins to high speed */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0xf03c0000; + + /* Enable clocks to SPI2 module */ + STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; + + /* Reset SPI2 */ + STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2; + STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2; + + /* Enable SPI LDO to power the flash chip */ + gpio_set_level(GPIO_VDDSPI_EN, 1); + + spi_enable(1); +} + +void usb_spi_board_disable(struct usb_spi_config const *config) +{ + spi_enable(0); + + /* Disable SPI LDO */ + gpio_set_level(GPIO_VDDSPI_EN, 0); + + /* Disable clocks to SPI2 module */ + STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; + + /* Release SPI GPIOs */ + gpio_config_module(MODULE_SPI_MASTER, 0); + gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_INPUT); + + /* Release AP from reset */ + gpio_set_level(GPIO_PMIC_WARM_RESET_L, 1); +} + +int board_get_version(void) +{ + static int ver; + + if (!ver) { + /* + * read the board EC ID on the tristate strappings + * using ternary encoding: 0 = 0, 1 = 1, Hi-Z = 2 + */ + uint8_t id0 = 0, id1 = 0; + gpio_set_flags(GPIO_BOARD_ID0, GPIO_PULL_DOWN | GPIO_INPUT); + gpio_set_flags(GPIO_BOARD_ID1, GPIO_PULL_DOWN | GPIO_INPUT); + usleep(100); + id0 = gpio_get_level(GPIO_BOARD_ID0); + id1 = gpio_get_level(GPIO_BOARD_ID1); + gpio_set_flags(GPIO_BOARD_ID0, GPIO_PULL_UP | GPIO_INPUT); + gpio_set_flags(GPIO_BOARD_ID1, GPIO_PULL_UP | GPIO_INPUT); + usleep(100); + id0 = gpio_get_level(GPIO_BOARD_ID0) && !id0 ? 2 : id0; + id1 = gpio_get_level(GPIO_BOARD_ID1) && !id1 ? 2 : id1; + gpio_set_flags(GPIO_BOARD_ID0, GPIO_INPUT); + gpio_set_flags(GPIO_BOARD_ID1, GPIO_INPUT); + ver = id1 * 3 + id0; + CPRINTS("Board ID = %d\n", ver); + } + + return ver; +} diff --git a/board/ryu_p4p5/board.h b/board/ryu_p4p5/board.h new file mode 100644 index 0000000000..6ded87e243 --- /dev/null +++ b/board/ryu_p4p5/board.h @@ -0,0 +1,201 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* ryu board configuration */ + +#ifndef __BOARD_H +#define __BOARD_H + +/* 48 MHz SYSCLK clock frequency */ +#define CPU_CLOCK 48000000 + +/* the UART console is on USART2 (PD4/PD5) */ +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 2 + +/* By default, enable all console messages excepted USB */ +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_USB) | CC_MASK(CC_LIGHTBAR))) + +/* Optional features */ +#undef CONFIG_CMD_HASH +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGE_RAMP +#define CONFIG_CMD_CHGRAMP +#define CONFIG_FORCE_CONSOLE_RESUME +#define CONFIG_STM_HWTIMER32 +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_FLASH_ERASE_CHECK +#define CONFIG_USB_PD_INTERNAL_COMP +#define CONFIG_USB_SWITCH_PI3USB9281 +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_VCONN +#define CONFIG_ADC +#define CONFIG_ADC_SAMPLE_TIME 3 +#define CONFIG_HW_CRC +#define CONFIG_I2C +#define CONFIG_LID_SWITCH +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_VBOOT_HASH +#define CONFIG_WATCHDOG_HELP +#undef CONFIG_TASK_PROFILING +#define CONFIG_INDUCTIVE_CHARGING +#undef CONFIG_HIBERNATE +#undef CONFIG_UART_TX_DMA /* DMAC_CH7 is used by USB PD */ +#define CONFIG_UART_RX_DMA +#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART2_RX + +/* Charging/Power configuration */ +#define CONFIG_BATTERY_RYU +#define CONFIG_BATTERY_BQ27541 +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_CHARGER +#define CONFIG_CHARGER_V2 +#define CONFIG_CHARGER_BQ24773 +#define CONFIG_CHARGER_ILIM_PIN_DISABLED +#define CONFIG_CHARGER_PROFILE_OVERRIDE +#define CONFIG_CHARGER_SENSE_RESISTOR 5 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHIPSET_TEGRA +#define CONFIG_PMIC_FW_LONG_PRESS_TIMER +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1 + +/* I2C ports configuration */ +#define I2C_PORT_MASTER 0 +#define I2C_PORT_SLAVE 1 +#define I2C_PORT_EC I2C_PORT_SLAVE +#define I2C_PORT_CHARGER I2C_PORT_MASTER +#define I2C_PORT_BATTERY I2C_PORT_MASTER +#define I2C_PORT_LIGHTBAR I2C_PORT_MASTER + +/* slave address for host commands */ +#ifdef HAS_TASK_HOSTCMD +#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3c +#endif + +/* USART and USB stream drivers */ +#define CONFIG_STREAM_USART +#define CONFIG_STREAM_USART1 +#define CONFIG_STREAM_USART3 +#define CONFIG_STREAM_USB + +/* USB Configuration */ +#define CONFIG_USB +#define CONFIG_USB_PID 0x500f + +/* Prevent the USB driver from initializing at boot */ +#define CONFIG_USB_INHIBIT_INIT + +/* USB interface indexes (use define rather than enum to expand them) */ +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_AP_STREAM 1 +#define USB_IFACE_SH_STREAM 2 +#define USB_IFACE_SPI 3 +#define USB_IFACE_COUNT 4 + +/* USB endpoint indexes (use define rather than enum to expand them) */ +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_AP_STREAM 2 +#define USB_EP_SH_STREAM 3 +#define USB_EP_SPI 4 +#define USB_EP_COUNT 5 + +/* Enable console over USB */ +#define CONFIG_USB_CONSOLE + +/* Enable control of SPI over USB */ +#define CONFIG_SPI_MASTER_PORT 2 +#define CONFIG_SPI_CS_GPIO GPIO_SPI_FLASH_NSS + +#define CONFIG_USB_SPI + +/* Enable Case Closed Debugging */ +#define CONFIG_CASE_CLOSED_DEBUG + +/* Maximum number of deferrable functions */ +#undef DEFERRABLE_MAX_COUNT +#define DEFERRABLE_MAX_COUNT 14 + +#ifndef __ASSEMBLER__ + +int board_get_version(void); + +/* Timer selection */ +#define TIM_CLOCK32 5 +#define TIM_WATCHDOG 19 + +#include "gpio_signal.h" + +/* PMIC_THERM_L selection at runtime depending on board version */ +#define GPIO_PMIC_THERM_L (board_get_version() >= 5 ? GPIO_P5_PMIC_THERM_L : \ + GPIO_P4_PMIC_THERM_L) + +enum power_signal { + TEGRA_XPSHOLD = 0, + TEGRA_SUSPEND_ASSERTED, + + /* Number of power signals */ + POWER_SIGNAL_COUNT +}; + +/* ADC signal */ +enum adc_channel { + ADC_VBUS = 0, + ADC_CC1_PD, + ADC_CC2_PD, + ADC_IADP, + ADC_IBAT, + /* Number of ADC channels */ + ADC_CH_COUNT +}; + +/* Charge suppliers */ +enum charge_supplier { + CHARGE_SUPPLIER_PD, + CHARGE_SUPPLIER_TYPEC, + CHARGE_SUPPLIER_BC12_DCP, + CHARGE_SUPPLIER_BC12_CDP, + CHARGE_SUPPLIER_BC12_SDP, + CHARGE_SUPPLIER_PROPRIETARY, + CHARGE_SUPPLIER_OTHER, + CHARGE_SUPPLIER_VBUS, + CHARGE_SUPPLIER_COUNT +}; + +/* supplier_priority table defined in board.c */ +extern const int supplier_priority[]; + +/* USB string indexes */ +enum usb_strings { + USB_STR_DESC = 0, + USB_STR_VENDOR, + USB_STR_PRODUCT, + USB_STR_VERSION, + USB_STR_CONSOLE_NAME, + USB_STR_AP_STREAM_NAME, + USB_STR_SH_STREAM_NAME, + + USB_STR_COUNT +}; + +/* Discharge battery when on AC power for factory test. */ +int board_discharge_on_ac(int enable); + +/* Set the charge current limit. */ +void board_set_charge_limit(int charge_ma); + +/* PP1800 transition GPIO interrupt handler */ +void pp1800_on_off_evt(enum gpio_signal signal); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __BOARD_H */ diff --git a/board/ryu_p4p5/build.mk b/board/ryu_p4p5/build.mk new file mode 100644 index 0000000000..4671ea0c7c --- /dev/null +++ b/board/ryu_p4p5/build.mk @@ -0,0 +1,13 @@ +# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +# the IC is STmicro STM32F373VB +CHIP:=stm32 +CHIP_FAMILY:=stm32f3 +CHIP_VARIANT:=stm32f373 + +board-y=board.o +board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/board/ryu_p4p5/ec.tasklist b/board/ryu_p4p5/ec.tasklist new file mode 100644 index 0000000000..cb9fb5adf2 --- /dev/null +++ b/board/ryu_p4p5/ec.tasklist @@ -0,0 +1,28 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, SMALLER_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, SMALLER_TASK_STACK_SIZE) \ + TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/ryu_p4p5/gpio.inc b/board/ryu_p4p5/gpio.inc new file mode 100644 index 0000000000..890c64390d --- /dev/null +++ b/board/ryu_p4p5/gpio.inc @@ -0,0 +1,144 @@ +/* -*- mode:c -*- + * + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupts */ +GPIO_INT(CHGR_ACOK, D, 4, GPIO_INT_BOTH | GPIO_PULL_UP, vbus_evt) +GPIO_INT(POWER_BUTTON_L, C, 13, GPIO_INT_BOTH, power_button_interrupt) /* active high, the name is for compatibility with existing code */ +GPIO_INT(USBC_BC12_INT_L, D, 11, GPIO_INT_FALLING | GPIO_PULL_UP, usb_evt) +GPIO_INT(LID_OPEN, E, 1, GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt) +GPIO_INT(CHARGE_DONE, E, 6, GPIO_INT_BOTH, inductive_charging_interrupt) +GPIO_INT(AP_IN_SUSPEND, F, 9, GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(AP_HOLD, E, 3, GPIO_INT_BOTH, power_signal_interrupt) +/* + * TODO(crosbug.com/p/38689) Workaround for MAX77620 PMIC PP3300 issue + * Put back as GPIO_ODR_HIGH for P6+ + */ +GPIO_INT(HPD_IN, C, 1, GPIO_INT_BOTH, pp1800_on_off_evt) + +/* Interrupt lines not used yet */ +GPIO(BC_TEMP_ALERT_L, C, 5, GPIO_INT_FALLING) +GPIO(LB_INT_L, E, 7, GPIO_INT_FALLING | GPIO_PULL_UP) +GPIO(LIGHTBAR_EN_L, E, 8, GPIO_INT_FALLING | GPIO_PULL_UP) +GPIO(BASE_PRES_L, E, 10, GPIO_INT_BOTH | GPIO_PULL_UP) + +/* Buttons */ +GPIO(BTN_VOLD_L, C, 0, GPIO_INPUT | GPIO_PULL_UP) +GPIO(BTN_VOLU_L, A, 2, GPIO_INPUT | GPIO_PULL_UP) + +/* PD RX/TX */ +GPIO(USBC_CC1_PD, A, 1, GPIO_ANALOG) +GPIO(USBC_CC2_PD, A, 3, GPIO_ANALOG) +GPIO(USBC_CC_EN, A, 4, GPIO_OUT_LOW) +GPIO(USBC_CC_TX_DATA, A, 6, GPIO_OUT_LOW) +GPIO(USBC_CC_TX_EN, D, 7, GPIO_OUT_LOW) + +#if 0 +/* Alternate functions */ +GPIO(USBC_TX_CLKOUT, B, 1, GPIO_OUT_LOW) +GPIO(USBC_TX_CLKIN, B, 3, GPIO_OUT_LOW) +#endif + +/* System power */ +GPIO(PMIC_PWRON_L, D, 14, GPIO_ODR_HIGH) +GPIO(PMIC_WARM_RESET_L, E, 4, GPIO_ODR_HIGH) +GPIO(EN_PP5000, A, 14, GPIO_OUT_LOW) /* Proto 5+ */ +/* + * We are missing an external pull-up for EN_PP3300. + * This GPIO is used to pull it up through an external 100kOhm. + * EN_PP3300 is still controlled by PMIC though. + */ +GPIO(EN_PP3300_RSVD, E, 13, GPIO_OUT_LOW) +/* sensor temp output and PMIC reset input */ +GPIO(P5_PMIC_THERM_L, B, 8, GPIO_ODR_HIGH) +/* TODO(crosbug.com/p/38333) remove P4_PMIC_THERM_L */ +GPIO(P4_PMIC_THERM_L, D, 12, GPIO_ODR_HIGH) + +GPIO(VBUS_SENSE, A, 0, GPIO_ANALOG) +GPIO(CHGR_IADP, B, 0, GPIO_ANALOG) +GPIO(CHGR_IBAT, C, 3, GPIO_ANALOG) + +/* Inductive charging */ +GPIO(CHARGE_EN, D, 13, GPIO_OUT_LOW) +GPIO(BASE_CHG_VDD_EN, E, 5, GPIO_OUT_LOW) + +/* USB-C Power and muxes control */ +GPIO(USBC_CHARGE_EN_L, A, 7, GPIO_OUT_LOW) +GPIO(USBC_5V_EN, D, 8, GPIO_OUT_LOW) +GPIO(USBC_VCONN1_EN_L, F, 10, GPIO_OUT_HIGH) +GPIO(USBC_VCONN2_EN_L, D, 10, GPIO_OUT_HIGH) + +GPIO(USBC_CC1_DEVICE_ODL, A, 5, GPIO_ODR_LOW) +GPIO(USBC_CC2_DEVICE_ODL, E, 14, GPIO_ODR_LOW) + +/* Pericom PI3USB30592 mux controls on Proto 5+ */ +GPIO(USBC_MUX_CONF0, D, 3, GPIO_OUT_LOW) +GPIO(USBC_MUX_CONF1, D, 9, GPIO_OUT_LOW) +GPIO(USBC_MUX_CONF2, E, 0, GPIO_OUT_LOW) +/* TODO(crosbug.com/p/38333) remove USBC_DP_xxx GPIOs */ +GPIO(USBC_DP_MODE_L, D, 1, GPIO_OUT_HIGH) +GPIO(USBC_DP_POLARITY, D, 2, GPIO_OUT_HIGH) + +/* Inputs */ +GPIO(BOARD_ID0, E, 11, GPIO_INPUT) +GPIO(BOARD_ID1, E, 12, GPIO_INPUT) +GPIO(SH_SIGNAL, E, 2, GPIO_INPUT) + +/* Lightbar reset */ +GPIO(LB_RST_L, D, 15, GPIO_ODR_HIGH | GPIO_PULL_UP) + +#if 0 +/* Alternate functions */ +GPIO(USB_DM, A, 11, GPIO_ANALOG) +GPIO(USB_DP, A, 12, GPIO_ANALOG) +GPIO(UART_TX, D, 5, GPIO_OUT_LOW) +GPIO(UART_RX, D, 6, GPIO_OUT_LOW) +#endif + +/* + * I2C pins should be configured as inputs until I2C module is + * initialized. This will avoid driving the lines unintentionally. + */ +GPIO(MASTER_I2C_SCL, A, 15, GPIO_INPUT) +GPIO(MASTER_I2C_SDA, A, 14, GPIO_INPUT) +GPIO(SLAVE_I2C_SCL, A, 9, GPIO_INPUT) +GPIO(SLAVE_I2C_SDA, A, 10, GPIO_INPUT) + +/* SCL gating for PI3USB9281 */ +GPIO(PERICOM_CLK_EN, C, 15, GPIO_OUT_HIGH) + +/* Case closed debugging. */ +GPIO(USB_PU_EN_L, C, 2, GPIO_OUT_HIGH) +GPIO(PD_DISABLE_DEBUG, C, 6, GPIO_OUT_LOW) +GPIO(SPI_FLASH_NSS, B, 9, GPIO_INPUT) +GPIO(VDDSPI_EN, C, 12, GPIO_OUT_LOW) +GPIO(SH_RESET, C, 4, GPIO_ODR_HIGH) +GPIO(SH_BOOT, C, 9, GPIO_ODR_HIGH) +GPIO(EC_INT_L, F, 2, GPIO_ODR_HIGH) +GPIO(ENTERING_RW, E, 15, GPIO_OUT_LOW) +GPIO(WP_L, F, 6, GPIO_INPUT) +GPIO(FW_DEBUG_MODE_L, C, 7, GPIO_ODR_HIGH) /* Proto 5+ */ + +#if 0 +/* Alternate functions */ +GPIO(SH_UART_TX, C, 11, GPIO_OUT_LOW) +GPIO(SH_UART_RX, C, 10, GPIO_INPUT) +GPIO(AP_UART_TX, B, 6, GPIO_OUT_LOW) +GPIO(AP_UART_RX, B, 7, GPIO_INPUT) +#endif + +UNIMPLEMENTED(AP_RESET_L) + +#define GPIO_ODR_UP GPIO_OPEN_DRAIN | GPIO_PULL_UP + +ALTERNATE(B, 0xC400, 5, MODULE_SPI_MASTER, 0) /* SPI2: PB10/14/15 */ +ALTERNATE(B, 0x0008, 5, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ +ALTERNATE(B, 0x0002, 2, MODULE_USB_PD, 0) /* TIM3_CH4: PB1 */ +ALTERNATE(B, 0x00C0, 7, MODULE_USART, 0) /* USART1: PB6/PB7 */ +ALTERNATE(D, 0x0060, 7, MODULE_UART, GPIO_PULL_UP) /* USART2: PD4/PD5 */ +ALTERNATE(C, 0x0C00, 7, MODULE_USART, GPIO_ODR_UP) /* USART3: PC10/PC11 */ +ALTERNATE(A, 0xC600, 4, MODULE_I2C, 0) /* I2C SLAVE:PA9/10 MASTER:PA14/15 */ +ALTERNATE(A, 0x1800,14, MODULE_USB, 0) /* USB: PA11/12 */ diff --git a/board/ryu_p4p5/usb_pd_config.h b/board/ryu_p4p5/usb_pd_config.h new file mode 100644 index 0000000000..8ab1017e3f --- /dev/null +++ b/board/ryu_p4p5/usb_pd_config.h @@ -0,0 +1,227 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* USB Power delivery board configuration */ + +#ifndef __USB_PD_CONFIG_H +#define __USB_PD_CONFIG_H + +#include "adc.h" +#include "charge_state.h" +#include "clock.h" +#include "gpio.h" +#include "registers.h" + +/* Port and task configuration */ +#define PD_PORT_COUNT 1 +#define PORT_TO_TASK_ID(port) TASK_ID_PD +#define TASK_ID_TO_PORT(id) 0 + +/* Timer selection for baseband PD communication */ +#define TIM_CLOCK_PD_TX_C0 3 +#define TIM_CLOCK_PD_RX_C0 2 + +#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0 +#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0 + +/* Timer channel */ +#define TIM_RX_CCR_C0 4 +#define TIM_TX_CCR_C0 4 + +/* RX timer capture/compare register */ +#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) +#define TIM_RX_CCR_REG(p) TIM_CCR_C0 + +/* TX and RX timer register */ +#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) +#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) +#define TIM_REG_TX(p) TIM_REG_TX_C0 +#define TIM_REG_RX(p) TIM_REG_RX_C0 + +/* use the hardware accelerator for CRC */ +#define CONFIG_HW_CRC + +/* TX is using SPI1 on PA6, PB3, and PB5 */ +#define SPI_REGS(p) STM32_SPI1_REGS + +static inline void spi_enable_clock(int port) +{ + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; + /* Delay 1 APB clock cycle after the clock is enabled */ + clock_wait_bus_cycles(BUS_APB, 1); +} + +#define DMAC_SPI_TX(p) STM32_DMAC_CH3 + +/* RX is using COMP1 triggering TIM2 CH4 */ +#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM2_IC4 +#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM2_IC4 + +#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 +#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 +#define TIM_CCR_CS 1 +#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22)) +#define IRQ_COMP STM32_IRQ_COMP +/* triggers packet detection on comparator falling edge */ +#define EXTI_XTSR STM32_EXTI_FTSR + +#define DMAC_TIM_RX(p) STM32_DMAC_CH7 + +/* the pins used for communication need to be hi-speed */ +static inline void pd_set_pins_speed(int port) +{ + /* 40 MHz pin speed on SPI MISO PA6 */ + STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003000; + /* 40 MHz pin speed on TIM3_CH4 (PB1) */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x0000000C; +} + +/* Reset SPI peripheral used for TX */ +static inline void pd_tx_spi_reset(int port) +{ + /* Reset SPI1 */ + STM32_RCC_APB2RSTR |= (1 << 12); + STM32_RCC_APB2RSTR &= ~(1 << 12); +} + +/* Drive the CC line from the TX block */ +static inline void pd_tx_enable(int port, int polarity) +{ + /* put SPI function on TX pin : PA6 is SPI MISO */ + gpio_set_alternate_function(GPIO_A, 0x0040, 5); + + /* set the low level reference */ + gpio_set_level(GPIO_USBC_CC_TX_EN, 1); +} + +/* Put the TX driver in Hi-Z state */ +static inline void pd_tx_disable(int port, int polarity) +{ + /* output low on SPI TX (PA6 is SPI1 MISO) to disable the FET */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*6))) + | (1 << (2*6)); + + /* put the low level reference in Hi-Z */ + gpio_set_level(GPIO_USBC_CC_TX_EN, 0); +} + +/* we know the plug polarity, do the right configuration */ +static inline void pd_select_polarity(int port, int polarity) +{ + /* + * use the right comparator : CC1 -> PA1 (COMP1 INP) + * CC2 -> PA3 (COMP2 INP) + * use VrefInt / 2 as INM (about 600mV) + */ + STM32_COMP_CSR = (STM32_COMP_CSR + & ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK + | STM32_COMP_CMP1EN | STM32_COMP_CMP2EN)) + | STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP2INSEL_VREF12 + | (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN); +} + +/* Initialize pins used for TX and put them in Hi-Z */ +static inline void pd_tx_init(void) +{ + gpio_config_module(MODULE_USB_PD, 1); +} + +static inline void pd_set_host_mode(int port, int enable) +{ + if (enable) { + /* Turn the 5V regulator providing VBUS */ + gpio_set_level(GPIO_EN_PP5000, 1); + /* We never charging in power source mode */ + gpio_set_level(GPIO_USBC_CHARGE_EN_L, 1); + charge_set_input_current_limit(0); + /* High-Z is used for host mode. */ + gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 1); + gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 1); + } else { + /* Kill VBUS power supply */ + gpio_set_level(GPIO_USBC_5V_EN, 0); + /* Turn off the 5V regulator */ + gpio_set_level(GPIO_EN_PP5000, 0); + /* Pull low for device mode. */ + gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 0); + gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 0); + gpio_set_level(GPIO_USBC_CHARGE_EN_L, 0); + } + +} + +/** + * Initialize various GPIOs and interfaces to safe state at start of pd_task. + * + * These include: + * VBUS, charge path based on power role. + * Physical layer CC transmit. + * VCONNs disabled. + * + * @param port USB-C port number + * @param power_role Power role of device + */ +static inline void pd_config_init(int port, uint8_t power_role) +{ + /* + * Set CC pull resistors, and charge_en and vbus_en GPIOs to match + * the initial role. + */ + pd_set_host_mode(port, power_role); + + /* Initialize TX pins and put them in Hi-Z */ + pd_tx_init(); + + /* Reset mux ... for NONE polarity doesn't matter */ + board_set_usb_mux(port, TYPEC_MUX_NONE, 0); + + gpio_set_level(GPIO_USBC_VCONN1_EN_L, 1); + gpio_set_level(GPIO_USBC_VCONN2_EN_L, 1); +} + +static inline int pd_adc_read(int port, int cc) +{ + if (cc == 0) + return adc_read_channel(ADC_CC1_PD); + else + return adc_read_channel(ADC_CC2_PD); +} + +static inline void pd_set_vconn(int port, int polarity, int enable) +{ + /* Set VCONN on the opposite CC line from the polarity */ + gpio_set_level(polarity ? GPIO_USBC_VCONN1_EN_L : + GPIO_USBC_VCONN2_EN_L, !enable); +} + +static inline int pd_snk_is_vbus_provided(int port) +{ + return gpio_get_level(GPIO_CHGR_ACOK); +} + +/* Standard-current DFP : no-connect voltage is 1.55V */ +#define PD_SRC_VNC 1550 /* mV */ + +/* UFP-side : threshold for DFP connection detection */ +#define PD_SNK_VA 200 /* mV */ + +/* start as a sink in case we have no other power supply/battery */ +#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED + +/* delay for the voltage transition on the power supply, chip max is 16us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 20000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 20000 /* us */ + +/* Define typical operating power and max power */ +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW 24000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + +/* The lower the input voltage, the higher the power efficiency. */ +#define PD_PREFER_LOW_VOLTAGE + +#endif /* __USB_PD_CONFIG_H */ diff --git a/board/ryu_p4p5/usb_pd_policy.c b/board/ryu_p4p5/usb_pd_policy.c new file mode 100644 index 0000000000..b7550b1480 --- /dev/null +++ b/board/ryu_p4p5/usb_pd_policy.c @@ -0,0 +1,139 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "charge_manager.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "registers.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "usb_pd.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP) + +const uint32_t pd_src_pdo[] = { + PDO_FIXED(5000, 900, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); + +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 10000), + PDO_VAR(4750, 21000, 3000), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +void pd_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ + struct charge_port_info charge; + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge); +} + +void typec_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ + struct charge_port_info charge; + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge); +} + +int pd_is_valid_input_voltage(int mv) +{ + /* Any voltage less than the max is allowed */ + return 1; +} + +int pd_check_requested_voltage(uint32_t rdo) +{ + int max_ma = rdo & 0x3FF; + int op_ma = (rdo >> 10) & 0x3FF; + int idx = rdo >> 28; + uint32_t pdo; + uint32_t pdo_ma; + + if (!idx || idx > pd_src_pdo_cnt) + return EC_ERROR_INVAL; /* Invalid index */ + + /* check current ... */ + pdo = pd_src_pdo[idx - 1]; + pdo_ma = (pdo & 0x3ff); + if (op_ma > pdo_ma) + return EC_ERROR_INVAL; /* too much op current */ + if (max_ma > pdo_ma) + return EC_ERROR_INVAL; /* too much max current */ + + CPRINTF("Requested %d V %d mA (for %d/%d mA)\n", + ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, + ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10); + + return EC_SUCCESS; +} + +void pd_transition_voltage(int idx) +{ + /* No-operation: we are always 5V */ +} + +int pd_set_power_supply_ready(int port) +{ + /* provide VBUS */ + gpio_set_level(GPIO_USBC_5V_EN, 1); + + return EC_SUCCESS; /* we are ready */ +} + +void pd_power_supply_reset(int port) +{ + /* Kill VBUS */ + gpio_set_level(GPIO_USBC_5V_EN, 0); +} + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + +int pd_check_power_swap(int port) +{ + /* TODO: use battery level to decide to accept/reject power swap */ + /* Always allow power swap */ + return 1; +} + +int pd_check_data_swap(int port, int data_role) +{ + /* Always allow data swap */ + return 1; +} + +void pd_check_pr_role(int port, int pr_role, int flags) +{ +} + +void pd_check_dr_role(int port, int dr_role, int flags) +{ +} + +void pd_execute_data_swap(int port, int data_role) +{ + /* TODO: what do we need to do to change host controller data role? */ +} + +int pd_custom_vdm(int port, int cnt, uint32_t *payload, + uint32_t **rpayload) +{ + return 0; +} diff --git a/common/lb_common.c b/common/lb_common.c index 6bd3ac5ec3..edd033d870 100644 --- a/common/lb_common.c +++ b/common/lb_common.c @@ -62,7 +62,7 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg) #define MAX_GREEN 0x30 #define MAX_BLUE 0x67 #endif -#if defined(BOARD_SAMUS) || defined(BOARD_RYU) +#if defined(BOARD_SAMUS) || defined(BOARD_RYU) || defined(BOARD_RYU_P4P5) /* Samus uses completely different LEDs, so the numbers are different. The * Samus LEDs can handle much higher currents, but these constants were * calibrated to provide uniform intensity at the level used by Link. @@ -123,7 +123,7 @@ static const uint8_t led_to_isc[] = { 0x18, 0x15, 0x18, 0x15 }; #ifdef BOARD_SAMUS static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 }; #endif -#ifdef BOARD_RYU +#if defined(BOARD_RYU) || defined(BOARD_RYU_P4P5) static const uint8_t led_to_isc[] = { 0x18, 0x15, 0x18, 0x15 }; #endif #ifdef BOARD_HOST diff --git a/test/build.mk b/test/build.mk index 9d897f14b6..b138a94683 100644 --- a/test/build.mk +++ b/test/build.mk @@ -20,6 +20,7 @@ test-list-$(BOARD_SAMUS)= # Ryu has issues when building tests test-list-$(BOARD_RYU)= +test-list-$(BOARD_RYU_P4P5)= # llama has issues when building tests test-list-$(BOARD_LLAMA)= diff --git a/util/flash_ec b/util/flash_ec index db83d69d7c..9ee1da44d5 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -75,6 +75,7 @@ BOARDS_STM32=( pit plankton ryu + ryu_p4p5 ryu_sh samus_pd snow |