diff options
-rw-r--r-- | board/host/gpio.inc | 2 | ||||
-rw-r--r-- | common/cbi_eeprom.c | 9 | ||||
-rw-r--r-- | common/main.c | 9 | ||||
-rw-r--r-- | common/system.c | 2 | ||||
-rw-r--r-- | include/config.h | 25 | ||||
-rw-r--r-- | include/cros_board_info.h | 9 | ||||
-rw-r--r-- | test/build.mk | 2 | ||||
-rw-r--r-- | test/cbi_wp.c | 56 | ||||
-rw-r--r-- | test/cbi_wp.tasklist | 9 | ||||
-rw-r--r-- | test/test_config.h | 4 | ||||
-rw-r--r-- | zephyr/Kconfig | 8 |
11 files changed, 132 insertions, 3 deletions
diff --git a/board/host/gpio.inc b/board/host/gpio.inc index c567aa0277..ce69385259 100644 --- a/board/host/gpio.inc +++ b/board/host/gpio.inc @@ -34,3 +34,5 @@ GPIO(USB_C0_DISCHARGE, PIN(0, 15), 0) GPIO(I2C_SCL, PIN(0, 16), GPIO_INPUT) GPIO(I2C_SDA, PIN(0, 17), GPIO_INPUT) + +GPIO(EC_CBI_WP, PIN(0, 18), GPIO_OUT_LOW) diff --git a/common/cbi_eeprom.c b/common/cbi_eeprom.c index fe52bcd9f3..2761f0b977 100644 --- a/common/cbi_eeprom.c +++ b/common/cbi_eeprom.c @@ -9,6 +9,7 @@ #include "cros_board_info.h" #include "gpio.h" #include "i2c.h" +#include "system.h" #include "timer.h" #include "util.h" @@ -63,6 +64,14 @@ static int eeprom_write(uint8_t *cbi) return EC_SUCCESS; } +#ifdef CONFIG_EEPROM_CBI_WP +void cbi_latch_eeprom_wp(void) +{ + CPRINTS("WP latched"); + gpio_set_level(GPIO_EC_CBI_WP, 1); +} +#endif /* CONFIG_EEPROM_CBI_WP */ + const struct cbi_storage_driver eeprom_drv = { .store = eeprom_write, .load = eeprom_read, diff --git a/common/main.c b/common/main.c index 5564100b31..d9fbe94a1e 100644 --- a/common/main.c +++ b/common/main.c @@ -12,6 +12,7 @@ #include "common.h" #include "console.h" #include "cpu.h" +#include "cros_board_info.h" #include "dma.h" #include "eeprom.h" #include "flash.h" @@ -170,6 +171,14 @@ test_mockable __keep int main(void) #endif /* + * If the EC has exclusive control over the CBI EEPROM WP signal, have + * the EC set the WP if appropriate. Note that once the WP is set, the + * EC must be reset via EC_RST_ODL in order for the WP to become unset. + */ + if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) && system_is_locked()) + cbi_latch_eeprom_wp(); + + /* * Keyboard scan init/Button init can set recovery events to * indicate to host entry into recovery mode. Before this is * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be initialized diff --git a/common/system.c b/common/system.c index adc510fefa..f88fb69072 100644 --- a/common/system.c +++ b/common/system.c @@ -175,7 +175,7 @@ static uint32_t __attribute__((unused)) get_size(enum ec_image copy) } } -int system_is_locked(void) +test_mockable int system_is_locked(void) { static int is_locked = -1; diff --git a/include/config.h b/include/config.h index 11733d38df..2f8cf39076 100644 --- a/include/config.h +++ b/include/config.h @@ -5176,6 +5176,14 @@ */ #undef CONFIG_CBI_EEPROM +/* + * Define this if the EC has exclusive control over the CBI EEPROM WP signal. + * The accompanying hardware must ensure that the CBI WP gets latched and is + * only reset when EC_RST_ODL is asserted. GPIO_EC_CBI_WP must be set up for + * the board. + */ +#undef CONFIG_EEPROM_CBI_WP + /* Define this to support Cros Board Info from GPIO. */ #undef CONFIG_CBI_GPIO @@ -6366,10 +6374,23 @@ #define ALS_COUNT 0 #endif /* CONFIG_ALS */ + +/* + * If the EC has exclusive control over CBI EEPROM WP, don't consult the main + * flash WP. + */ +#ifdef CONFIG_EEPROM_CBI_WP +#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK +#endif + +#if defined(CONFIG_EEPROM_CBI_WP) && !defined(CONFIG_CBI_EEPROM) +#error "CONFIG_EEPROM_CBI_WP requires CONFIG_CBI_EEPROM to be defined!" +#endif + #if defined(CONFIG_BYPASS_CBI_EEPROM_WP_CHECK) && \ - !defined(CONFIG_SYSTEM_UNLOCKED) + !defined(CONFIG_SYSTEM_UNLOCKED) && !defined(CONFIG_EEPROM_CBI_WP) #error "CONFIG_BYPASS_CBI_EEPROM_WP_CHECK is only permitted " \ - "when CONFIG_SYSTEM_UNLOCK is also enabled." + "when CONFIG_SYSTEM_UNLOCK or CONFIG_EEPROM_CBI_WP is also enabled." #endif /* CONFIG_BYPASS_CBI_EEPROM_WP_CHECK && !CONFIG_SYSTEM_UNLOCK */ #if defined(CONFIG_BOARD_VERSION_CBI) && defined(CONFIG_BOARD_VERSION_GPIO) diff --git a/include/cros_board_info.h b/include/cros_board_info.h index ee5a717ee5..7a79cfee2a 100644 --- a/include/cros_board_info.h +++ b/include/cros_board_info.h @@ -217,6 +217,15 @@ void cbi_invalidate_cache(void); */ int cbi_get_cache_status(void); +/** + * Latch the CBI EEPROM WP + * + * This function assumes that the EC has a pin to set the CBI EEPROM WP signal + * (GPIO_EC_CBI_WP). Note that once the WP is set, the EC must be reset via + * EC_RST_ODL in order for the WP to become unset since the signal is latched. + */ +void cbi_latch_eeprom_wp(void); + #ifdef TEST_BUILD /** * Write the locally cached CBI to EEPROM. diff --git a/test/build.mk b/test/build.mk index 6b156ccaf0..ec9e66ead3 100644 --- a/test/build.mk +++ b/test/build.mk @@ -20,6 +20,7 @@ test-list-host += bklight_passthru test-list-host += body_detection test-list-host += button test-list-host += cbi +test-list-host += cbi_wp test-list-host += cec test-list-host += charge_manager test-list-host += charge_manager_drp_charging @@ -132,6 +133,7 @@ bklight_passthru-y=bklight_passthru.o body_detection-y=body_detection.o body_detection_data_literals.o motion_common.o button-y=button.o cbi-y=cbi.o +cbi_wp-y=cbi_wp.o cec-y=cec.o charge_manager-y=charge_manager.o charge_manager_drp_charging-y=charge_manager.o diff --git a/test/cbi_wp.c b/test/cbi_wp.c new file mode 100644 index 0000000000..7bdfa4b0c8 --- /dev/null +++ b/test/cbi_wp.c @@ -0,0 +1,56 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Test CBI EEPROM WP + */ + +#include "common.h" +#include "console.h" +#include "cros_board_info.h" +#include "gpio.h" +#include "system.h" +#include "test_util.h" +#include "util.h" + +static int system_locked; + +static void test_setup(void) +{ + /* Make sure that write protect is disabled */ + gpio_set_level(GPIO_WP, 0); + gpio_set_level(GPIO_EC_CBI_WP, 0); + system_locked = 0; +} + +static void test_teardown(void) +{ +} + +int system_is_locked(void) +{ + return system_locked; +} + +DECLARE_EC_TEST(test_wp) +{ + int cbi_wp; + + cbi_wp = gpio_get_level(GPIO_EC_CBI_WP); + zassert_equal(cbi_wp, 0, NULL); + + cbi_latch_eeprom_wp(); + cbi_wp = gpio_get_level(GPIO_EC_CBI_WP); + zassert_equal(cbi_wp, 1, NULL); + + return EC_SUCCESS; +} + +TEST_SUITE(test_suite_cbi_wp) +{ + ztest_test_suite(test_cbi_wp, + ztest_unit_test_setup_teardown(test_wp, + test_setup, + test_teardown)); + ztest_run_test_suite(test_cbi_wp); +} diff --git a/test/cbi_wp.tasklist b/test/cbi_wp.tasklist new file mode 100644 index 0000000000..e54ea001bd --- /dev/null +++ b/test/cbi_wp.tasklist @@ -0,0 +1,9 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TEST_TASK_LIST /* No test task */ diff --git a/test/test_config.h b/test/test_config.h index 8b98dc1087..5afc5d1282 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -40,6 +40,10 @@ #define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN #endif +#ifdef TEST_CBI_WP +#define CONFIG_EEPROM_CBI_WP +#endif + #ifdef TEST_FLASH_LOG #define CONFIG_CRC8 #define CONFIG_FLASH_ERASED_VALUE32 (-1U) diff --git a/zephyr/Kconfig b/zephyr/Kconfig index 2440fd3773..a24996e2f6 100644 --- a/zephyr/Kconfig +++ b/zephyr/Kconfig @@ -141,6 +141,14 @@ config PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK When defined, ectool can be used to reprogram all CBI fields, regardless of the state of the hardware write protect. +config PLATFORM_EC_EEPROM_CBI_WP + bool "EC can independently set the CBI EEPROM WP signal" + help + Define this if the EC can independently set the CBI EEPROM WP + signal. The accompanying hardware must ensure that the CBI WP gets + latched and is only reset when EC_RST_ODL is asserted. + select PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK + choice PLATFORM_EC_CBI_STORAGE_TYPE prompt "Select CBI storage Type" optional |