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-rw-r--r--chip/nrf51/build.mk6
-rw-r--r--chip/stm32/build.mk6
2 files changed, 10 insertions, 2 deletions
diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk
index e5d8ed1b29..e1cf967168 100644
--- a/chip/nrf51/build.mk
+++ b/chip/nrf51/build.mk
@@ -8,7 +8,11 @@
CORE:=cortex-m0
# Force ARMv6-M ISA used by the Cortex-M0
-CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0
+# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
+# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
+# with "svc". GCC kept that naming scheme even though the distinction is long
+# gone.
+CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
chip-y+=gpio.o system.o uart.o
chip-y+=watchdog.o ppi.o
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 6e0c190667..9a6a280d81 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -10,7 +10,11 @@ ifeq ($(CHIP_FAMILY),stm32f0)
# STM32F0xx sub-family has a Cortex-M0 ARM core
CORE:=cortex-m0
# Force ARMv6-M ISA used by the Cortex-M0
-CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0
+# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
+# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
+# with "svc". GCC kept that naming scheme even though the distinction is long
+# gone.
+CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4))
# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
CORE:=cortex-m