diff options
-rw-r--r-- | baseboard/octopus/baseboard.h | 2 | ||||
-rw-r--r-- | baseboard/octopus/variant_ec_npcx796fb.c | 6 | ||||
-rw-r--r-- | baseboard/octopus/variant_usbc_standalone_tcpcs.c | 56 | ||||
-rw-r--r-- | board/casta/battery.c | 39 | ||||
-rw-r--r-- | board/casta/board.c | 90 | ||||
-rw-r--r-- | board/casta/board.h | 65 | ||||
-rw-r--r-- | board/casta/build.mk | 15 | ||||
-rw-r--r-- | board/casta/ec.tasklist | 38 | ||||
-rw-r--r-- | board/casta/gpio.inc | 166 |
9 files changed, 464 insertions, 13 deletions
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index dace7bdbcf..07e77b7013 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -162,8 +162,10 @@ #if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS) #define CONFIG_USB_PD_TCPC_LOW_POWER #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751) #define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ #define CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND +#endif #define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ #define CONFIG_USB_PD_VBUS_DETECT_TCPC #define CONFIG_USBC_PPC_NX20P3483 diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c index 8d798fc5a7..9089e0fb19 100644 --- a/baseboard/octopus/variant_ec_npcx796fb.c +++ b/baseboard/octopus/variant_ec_npcx796fb.c @@ -9,7 +9,9 @@ #include "gpio.h" #include "i2c.h" #include "power.h" +#ifdef CONFIG_PWM #include "pwm_chip.h" +#endif #include "timer.h" #include "usbc_ppc.h" #include "util.h" @@ -33,13 +35,17 @@ const struct i2c_port_t i2c_ports[] = { {"tcpc1", I2C_PORT_TCPC1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, {"eeprom", I2C_PORT_EEPROM, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, {"charger", I2C_PORT_CHARGER, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, +#ifndef VARIANT_OCTOPUS_NO_SENSORS {"sensor", I2C_PORT_SENSOR, 100, GPIO_I2C7_SCL, GPIO_I2C7_SDA}, +#endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); +#ifdef CONFIG_PWM /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); +#endif diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c index ffa26336bb..ec2c65bd23 100644 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c @@ -24,19 +24,25 @@ #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_1 1 /******************************************************************************/ /* USB-C TPCP Configuration */ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = { - [USB_PD_PORT_ANX7447] = { + [USB_PD_PORT_TCPC_0] = { .i2c_host_port = I2C_PORT_TCPC0, +#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) + .i2c_slave_addr = PS8751_I2C_ADDR1, + .drv = &ps8xxx_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW +#else .i2c_slave_addr = AN7447_TCPC0_I2C_ADDR, .drv = &anx7447_tcpm_drv, .pol = TCPC_ALERT_ACTIVE_LOW, +#endif }, - [USB_PD_PORT_PS8751] = { + [USB_PD_PORT_TCPC_1] = { .i2c_host_port = I2C_PORT_TCPC1, .i2c_slave_addr = PS8751_I2C_ADDR1, .drv = &ps8xxx_tcpm_drv, @@ -48,11 +54,16 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = { /* USB-C MUX Configuration */ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = { - [USB_PD_PORT_ANX7447] = { + [USB_PD_PORT_TCPC_0] = { +#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, +#else .driver = &anx7447_usb_mux_driver, .hpd_update = &anx7447_tcpc_update_hpd_status, +#endif }, - [USB_PD_PORT_PS8751] = { + [USB_PD_PORT_TCPC_1] = { .driver = &tcpci_tcpm_usb_mux_driver, .hpd_update = &ps8xxx_tcpc_update_hpd_status, } @@ -61,12 +72,12 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = { /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_COUNT] = { - [USB_PD_PORT_ANX7447] = { + [USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_TCPC0, .i2c_addr = NX20P3483_ADDR2, .drv = &nx20p348x_drv, }, - [USB_PD_PORT_PS8751] = { + [USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_TCPC1, .i2c_addr = NX20P3483_ADDR2, .drv = &nx20p348x_drv, @@ -113,8 +124,12 @@ uint16_t tcpc_get_alert_status(void) uint16_t status = 0; if (!gpio_get_level(GPIO_USB_C0_MUX_INT_ODL)) { +#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) + if (gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) +#else if (!gpio_is_implemented(GPIO_USB_C0_PD_RST) || !gpio_get_level(GPIO_USB_C0_PD_RST)) +#endif status |= PD_STATUS_TCPC_ALERT_0; } @@ -134,6 +149,21 @@ uint16_t tcpc_get_alert_status(void) */ void board_reset_pd_mcu(void) { +#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) + /* + * C0: Assert reset to TCPC0 (PS8751) for required delay if we have a + * battery + */ + if (battery_is_present() == BP_YES) { + /* + * TODO(crbug:846412): After refactor, ensure that battery has + * enough charge to last the reboot as well + */ + gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); + msleep(PS8XXX_RESET_DELAY_MS); + gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); + } +#else /* * C0: Assert reset to TCPC0 (ANX7447) for required delay (1ms) only if * we have a battery @@ -151,7 +181,7 @@ void board_reset_pd_mcu(void) gpio_set_level(GPIO_USB_C0_PD_RST, 0); msleep(ANX74XX_RESET_FINISH_MS); } - +#endif /* * C1: Assert reset to TCPC1 (PS8751) for required delay (1ms) only if * we have a battery, otherwise we may brown out the system. @@ -182,10 +212,10 @@ static void set_ps8751_gpio3(int enable) * Ensure that we don't put the TCPC back to sleep while we are * accessing debug registers. */ - pd_prevent_low_power_mode(USB_PD_PORT_PS8751, 1); + pd_prevent_low_power_mode(USB_PD_PORT_TCPC_1, 1); /* Enable debug page access */ - rv = tcpc_write(USB_PD_PORT_PS8751, PS8XXX_REG_I2C_DEBUGGING_ENABLE, + rv = tcpc_write(USB_PD_PORT_TCPC_1, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x30); if (rv) goto error; @@ -225,8 +255,8 @@ error: CPRINTS("C1: Could not set re-driver power to %d", enable); /* Disable debug page access and allow LPM again*/ - tcpc_write(USB_PD_PORT_PS8751, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31); - pd_prevent_low_power_mode(USB_PD_PORT_PS8751, 0); + tcpc_write(USB_PD_PORT_TCPC_1, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31); + pd_prevent_low_power_mode(USB_PD_PORT_TCPC_1, 0); } /* diff --git a/board/casta/battery.c b/board/casta/battery.c new file mode 100644 index 0000000000..6cb4fc5743 --- /dev/null +++ b/board/casta/battery.c @@ -0,0 +1,39 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery_fuel_gauge.h" +#include "common.h" +#include "util.h" + +/* + * Battery info for all casta battery types. Note that the fields + * start_charging_min/max and charging_min/max are not used for the charger. + * The effective temperature limits are given by discharging_min/max_c. + * + * Fuel Gauge (FG) parameters which are used for determining if the battery + * is connected, the appropriate ship mode (battery cutoff) command, and the + * charge/discharge FETs status. + * + * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery + * register. For some batteries, the charge/discharge FET bits are set when + * charging/discharging is active, in other types, these bits set mean that + * charging/discharging is disabled. Therefore, in addition to the mask for + * these bits, a disconnect value must be specified. Note that for TI fuel + * gauge, the charge/discharge FET status is found in Operation Status (0x54), + * but a read of Manufacturer Access (0x00) will return the lower 16 bits of + * Operation status which contains the FET status bits. + * + * The assumption for battery types supported is that the charge/discharge FET + * status can be read with a sb_read() command and therefore, only the register + * address, mask, and disconnect value need to be provided. + */ +const struct board_batt_params board_battery_info[] = { + /* TODO(b/119871861): Casta: battery datasheets and specs */ +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_TYPE_COUNT; diff --git a/board/casta/board.c b/board/casta/board.c new file mode 100644 index 0000000000..d5dc8833bf --- /dev/null +++ b/board/casta/board.c @@ -0,0 +1,90 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Casta board-specific configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "battery.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "common.h" +#include "cros_board_info.h" +#include "driver/charger/bd9995x.h" +#include "driver/ppc/nx20p348x.h" +#include "driver/tcpm/anx7447.h" +#include "driver/tcpm/ps8xxx.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/tcpm.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "i2c.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "power.h" +#include "power_button.h" +#include "switch.h" +#include "system.h" +#include "tcpci.h" +#include "temp_sensor.h" +#include "thermistor.h" +#include "usb_mux.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) + +static void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_PD_C0_INT_ODL: + nx20p348x_interrupt(0); + break; + + case GPIO_USB_PD_C1_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} + +/* Must come after other header files and GPIO interrupts*/ +#include "gpio_list.h" + +/* ADC channels */ +const struct adc_t adc_channels[] = { + [ADC_TEMP_SENSOR_AMB] = { + "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_CHARGER] = { + "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* TODO(b/119872005): Casta: confirm thermistor parts */ +const struct temp_sensor_t temp_sensors[] = { + [TEMP_SENSOR_BATTERY] = {.name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0, + .action_delay_sec = 1}, + [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB, + .action_delay_sec = 5}, + [TEMP_SENSOR_CHARGER] = {.name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER, + .action_delay_sec = 1}, +}; +BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); + diff --git a/board/casta/board.h b/board/casta/board.h new file mode 100644 index 0000000000..8d83af75af --- /dev/null +++ b/board/casta/board.h @@ -0,0 +1,65 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Casta board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Select Baseboard features */ +#define VARIANT_OCTOPUS_EC_NPCX796FB +#define VARIANT_OCTOPUS_CHARGER_ISL9238 +#define VARIANT_OCTOPUS_TCPC_0_PS8751 +#define VARIANT_OCTOPUS_NO_SENSORS +#include "baseboard.h" + +/* USB PD */ +#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT +#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT + +#define CONFIG_TEMP_SENSOR +#define CONFIG_THERMISTOR + +/* Keyboard Backlight is unconnected in casta proto */ +#undef CONFIG_PWM +#undef CONFIG_PWM_KBLIGHT + +/* All casta systems are clamshells */ +#undef CONFIG_TABLET_MODE +#undef CONFIG_TABLET_SWITCH + +/* TODO(b/119872005): Casta: confirm thermistor parts */ +#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B +#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_HOST_EVENT + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +enum adc_channel { + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_CH_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_BATTERY, + TEMP_SENSOR_AMBIENT, + TEMP_SENSOR_CHARGER, + TEMP_SENSOR_COUNT +}; + +/* List of possible batteries */ +/* TODO(b/119871861): Casta: battery datasheets and specs */ +enum battery_type { + BATTERY_TYPE_COUNT, +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/casta/build.mk b/board/casta/build.mk new file mode 100644 index 0000000000..94c194fa01 --- /dev/null +++ b/board/casta/build.mk @@ -0,0 +1,15 @@ +# -*- makefile -*- +# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=npcx +CHIP_FAMILY:=npcx7 +CHIP_VARIANT:=npcx7m6fb +BASEBOARD:=octopus + +board-y=board.o +board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/board/casta/ec.tasklist b/board/casta/ec.tasklist new file mode 100644 index 0000000000..addd7efed2 --- /dev/null +++ b/board/casta/ec.tasklist @@ -0,0 +1,38 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + * + * For USB PD tasks, IDs must be in consecutive order and correspond to + * the port which they are for. See TASK_ID_TO_PD_PORT() macro. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) diff --git a/board/casta/gpio.inc b/board/casta/gpio.inc new file mode 100644 index 0000000000..00597e5270 --- /dev/null +++ b/board/casta/gpio.inc @@ -0,0 +1,166 @@ +/* -*- mode:c -*- + * + * Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +/* Wake Source interrupts */ +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH, lid_interrupt) +/* + * High-to-low transition on POWER_BUTTON_L is treated as a wake event from + * hibernate. Absence of GPIO_HIB_WAKE_HIGH flag is treated as wake on + * high-to-low edge. + */ +GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* MECH_PWR_BTN_ODL */ +GPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* ACOK_OD */ + +/* USB-C interrupts */ +GPIO_INT(USB_C0_MUX_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C1_MUX_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_PD_C0_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt) +GPIO_INT(USB_PD_C1_INT_ODL, PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt) + +/* Power State interrupts */ +#ifdef CONFIG_POWER_S0IX +GPIO_INT(PCH_SLP_S0_L, PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ +#endif +GPIO_INT(PCH_SLP_S4_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */ +GPIO_INT(PCH_SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */ +GPIO_INT(SUSPWRDNACK, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRDNACK */ +GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */ +GPIO_INT(ALL_SYS_PGOOD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */ + +/* Other interrupts */ +GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */ + +/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */ +#ifndef CONFIG_POWER_S0IX +GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */ +#endif + +/* + * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here + * only for debugging purposes. + */ +GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */ +GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */ + +GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */ +GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ +GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ + +GPIO(EN_PP5000, PIN(7, 3), GPIO_OUT_LOW) /* EN_PP5000_A */ +GPIO(PP5000_PG, PIN(C, 0), GPIO_INPUT) /* PP5000_PG_OD */ +GPIO(EN_PP3300, PIN(D, 4), GPIO_OUT_LOW) /* EN_PP3300_A */ +GPIO(PP3300_PG, PIN(6, 0), GPIO_INPUT) /* PP3300_PG_OD */ +GPIO(PMIC_EN, PIN(7, 2), GPIO_OUT_LOW) /* Enable A Rails via PMIC */ +GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */ +GPIO(PCH_SYS_PWROK, PIN(B, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */ + +/* Peripheral rails */ +GPIO(ENABLE_BACKLIGHT, PIN(D, 3), GPIO_ODR_HIGH | + GPIO_SEL_1P8V) /* EC_BL_EN_OD */ +GPIO(EN_P3300_TRACKPAD_ODL, PIN(3, 3), GPIO_ODR_HIGH) + +GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT) + +/* + * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does + * not need to be an interrupt for normal EC operations. Thus, configure it as + * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL + * common code can configure PSL_IN correctly. + * + * Reason for choosing low-to-high edge for waking from hibernate is to avoid + * the double reset - one because of PSL_IN wake and other because of VCC1_RST + * being asserted. Also, it should be fine to have the EC in hibernate when H1 + * or servo wants to hold the EC in reset since VCC1 will be down and so entire + * EC logic (except PSL) as well as AP will be in reset. + */ +GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) + +/* + * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is + * normally driven by the PMIC. The EC can also drive this signal in the event + * that the ambient or charger temperature sensors exceeds their thresholds. + */ +GPIO(CPU_PROCHOT, PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */ + +GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */ + +/* I2C pins - Alternate function below configures I2C module on these pins */ +GPIO(I2C0_SCL, PIN(B, 5), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SCL */ +GPIO(I2C0_SDA, PIN(B, 4), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SDA */ +GPIO(I2C1_SCL, PIN(9, 0), GPIO_INPUT) /* EC_I2C_USB_C0_MUX_SCL */ +GPIO(I2C1_SDA, PIN(8, 7), GPIO_INPUT) /* EC_I2C_USB_C0_MUX_SDA */ +GPIO(I2C2_SCL, PIN(9, 2), GPIO_INPUT) /* EC_I2C_USB_C1_MUX_SCL */ +GPIO(I2C2_SDA, PIN(9, 1), GPIO_INPUT) /* EC_I2C_USB_C1_MUX_SDA */ +GPIO(I2C3_SCL, PIN(D, 1), GPIO_INPUT) /* EC_I2C_EEPROM_SCL */ +GPIO(I2C3_SDA, PIN(D, 0), GPIO_INPUT) /* EC_I2C_EEPROM_SDA */ +GPIO(I2C4_SCL, PIN(F, 3), GPIO_INPUT) /* EC_I2C_CHARGER_3V3_SCL */ +GPIO(I2C4_SDA, PIN(F, 2), GPIO_INPUT) /* EC_I2C_CHARGER_3V3_SDA */ + +/* USB pins */ +GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ +GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_INPUT | GPIO_PULL_DOWN) /* NC */ +GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ +GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN) /* NC */ + +GPIO(USB_C0_PD_RST_ODL, PIN(8, 3), GPIO_ODR_HIGH) /* C0 PD Reset */ +GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ +GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ +GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ + GPIO_SEL_1P8V) +GPIO(USB_C1_PD_RST_ODL, PIN(7, 0), GPIO_ODR_HIGH) /* C1 PD Reset */ +GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ +GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ +GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ + GPIO_SEL_1P8V) + +/* LED */ +GPIO(LED_1_L, PIN(C, 3), GPIO_OUT_HIGH) +GPIO(LED_2_L, PIN(C, 4), GPIO_OUT_HIGH) +GPIO(LED_3_L, PIN(D, 7), GPIO_OUT_HIGH) + +/* Not implemented in hardware */ +UNIMPLEMENTED(KB_BL_PWR_EN) + +/* Overcurrent event to host */ +GPIO(USB_C_OC, PIN(3, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) + +/* Strap pins */ +GPIO(GPO66_NC, PIN(6, 6), GPIO_INPUT | GPIO_PULL_UP) +GPIO(GPOB6_NC, PIN(B, 6), GPIO_INPUT | GPIO_PULL_UP) + +/* Misc. */ +GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) + +/* Keyboard pins */ +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */ +ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_02-07 */ +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */ +ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */ +ALTERNATE(PIN_MASK(0, 0xF0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-13 */ +ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_14 */ +GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */ + +/* Alternate functions GPIO definitions */ +/* Cr50 requires no pull-ups on UART pins. */ +ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* UART from EC to Servo */ +ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0) /* I2C0 */ +ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* I2C1 SCL / I2C2 */ +ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* I2C1 SDA */ +ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0) /* I2C3 */ +ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */ +ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */ + +/* Power Switch Logic (PSL) inputs */ +ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 = LID_OPEN */ +ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0) /* GPIO00 = ACOK_OD, + GPIO01 = MECH_PWR_BTN_ODL + GPIO02 = EC_RST_ODL */ |