diff options
| -rw-r--r-- | board/bds/board.c | 48 | ||||
| -rw-r--r-- | board/link/board.c | 10 | ||||
| -rw-r--r-- | chip/lm4/adc.c | 4 | ||||
| -rw-r--r-- | chip/lm4/gpio.c | 10 | ||||
| -rw-r--r-- | chip/lm4/i2c.c | 9 | ||||
| -rw-r--r-- | chip/lm4/keyboard_scan.c | 99 | ||||
| -rw-r--r-- | chip/lm4/lpc.c | 14 | ||||
| -rw-r--r-- | chip/lm4/pwm.c | 14 | ||||
| -rw-r--r-- | chip/lm4/registers.h | 89 | ||||
| -rw-r--r-- | chip/lm4/timer.c | 28 | ||||
| -rw-r--r-- | chip/lm4/uart.c | 14 | ||||
| -rw-r--r-- | chip/lm4/x86_power.c | 18 | ||||
| -rw-r--r-- | test/powerdemo.c | 46 |
13 files changed, 218 insertions, 185 deletions
diff --git a/board/bds/board.c b/board/bds/board.c index 88d528bf51..d9c79b675a 100644 --- a/board/bds/board.c +++ b/board/bds/board.c @@ -1,3 +1,7 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ /* Stellaris EKB-LM4F-EAC pins multiplexing */ #include "board.h" @@ -15,24 +19,24 @@ void configure_board(void) * pin 6 : GPIO = function 0 (SD card CS -- open drain) * pin 7 : GPIO = function 0 (user LED) */ - LM4_GPIO_PCTL(A) = 0x00222211; - LM4_GPIO_AFSEL(A) = 0x3f; - LM4_GPIO_DEN(A) = 0xff; - LM4_GPIO_PDR(A) = 0x00; - LM4_GPIO_PUR(A) = 0x3c; - LM4_GPIO_DIR(A) = 0xc0; - LM4_GPIO_ODR(A) = 0x40; - LM4_GPIO_DR2R(A) = 0xc3; - LM4_GPIO_DR8R(A) = 0x3c; - LM4_GPIO_DATA_BITS(A, 0x100) = 0x40; - LM4_GPIO_DATA_BITS(A, 0x200) = 0; + LM4_GPIO_PCTL(LM4_GPIO_A) = 0x00222211; + LM4_GPIO_AFSEL(LM4_GPIO_A) = 0x3f; + LM4_GPIO_DEN(LM4_GPIO_A) = 0xff; + LM4_GPIO_PDR(LM4_GPIO_A) = 0x00; + LM4_GPIO_PUR(LM4_GPIO_A) = 0x3c; + LM4_GPIO_DIR(LM4_GPIO_A) = 0xc0; + LM4_GPIO_ODR(LM4_GPIO_A) = 0x40; + LM4_GPIO_DR2R(LM4_GPIO_A) = 0xc3; + LM4_GPIO_DR8R(LM4_GPIO_A) = 0x3c; + LM4_GPIO_DATA(LM4_GPIO_A, 0x40) = 0x40; + LM4_GPIO_DATA(LM4_GPIO_A, 0x80) = 0; /* GPIOB muxing * pin 0 : GPIO = function 0 (USB ID) * pin 1 : USB digital (VBus sense) */ - LM4_GPIO_DEN(B) |= 0x01; - LM4_GPIO_AFSEL(B)|= 0x01; + LM4_GPIO_DEN(LM4_GPIO_B) |= 0x01; + LM4_GPIO_AFSEL(LM4_GPIO_B) |= 0x01; /* GPIOC muxing * pins 0/1/2/3 : JTAG (default config) @@ -40,24 +44,24 @@ void configure_board(void) * pin 6 : USB digital (USB power enable) * pin 7 : USB digital (USB current overflow) */ - LM4_GPIO_PCTL(C) = 0x88001111; - LM4_GPIO_AFSEL(C) = 0xcf; - LM4_GPIO_DEN(C) = 0xdf; - LM4_GPIO_DIR(C) = 0x10; - LM4_GPIO_DATA_BITS(C, 0x40) = 0; + LM4_GPIO_PCTL(LM4_GPIO_C) = 0x88001111; + LM4_GPIO_AFSEL(LM4_GPIO_C) = 0xcf; + LM4_GPIO_DEN(LM4_GPIO_C) = 0xdf; + LM4_GPIO_DIR(LM4_GPIO_C) = 0x10; + LM4_GPIO_DATA(LM4_GPIO_C, 0x10) = 0; /* GPIOD muxing * pins 0/1/2/3/4 : GPIO = function 0 (buttons up,down,left,right,select) * pin 5 : GPIO = function 0 (OLED d/Cn) * pin 6 : GPIO = function 0 (OLED reset) */ - LM4_GPIO_DEN(D) = 0x7f; - LM4_GPIO_DIR(D) = 0x60; - LM4_GPIO_PUR(D) = 0x1f; + LM4_GPIO_DEN(LM4_GPIO_D) = 0x7f; + LM4_GPIO_DIR(LM4_GPIO_D) = 0x60; + LM4_GPIO_PUR(LM4_GPIO_D) = 0x1f; /* GPIOE muxing * pin 3 : Analog function : AIN0 ADC (potentiometer) * pin 6/7: USB analog */ - LM4_GPIO_AMSEL(E) = 0x8; + LM4_GPIO_AMSEL(LM4_GPIO_E) = 0x8; } diff --git a/board/link/board.c b/board/link/board.c index 7b1ceb77e7..fd6ac6bf75 100644 --- a/board/link/board.c +++ b/board/link/board.c @@ -1,3 +1,7 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ /* EC for Link mainboard pins multiplexing */ #include "board.h" @@ -12,7 +16,7 @@ void configure_board(void) /* GPIOA muxing : * pins 0/1 : UART0 = function 1 */ - LM4_GPIO_PCTL(A) = 0x00000011; - LM4_GPIO_AFSEL(A) = 0x03; - LM4_GPIO_DEN(A) = 0x03; + LM4_GPIO_PCTL(LM4_GPIO_A) = 0x00000011; + LM4_GPIO_AFSEL(LM4_GPIO_A) = 0x03; + LM4_GPIO_DEN(LM4_GPIO_A) = 0x03; } diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c index fab5c43cef..97b20ed175 100644 --- a/chip/lm4/adc.c +++ b/chip/lm4/adc.c @@ -23,8 +23,8 @@ static void configure_gpio(void) scratch = LM4_SYSTEM_RCGCGPIO; /* Use analog function for PE3 (AIN0) */ - LM4_GPIO_DEN(E) &= ~0x08; - LM4_GPIO_AMSEL(E) |= 0x08; + LM4_GPIO_DEN(LM4_GPIO_E) &= ~0x08; + LM4_GPIO_AMSEL(LM4_GPIO_E) |= 0x08; } diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c index 2ec64ce8af..a00d771c53 100644 --- a/chip/lm4/gpio.c +++ b/chip/lm4/gpio.c @@ -18,11 +18,11 @@ int gpio_pre_init(void) gpio_set(EC_GPIO_DEBUG_LED, 0); /* Clear GPIOAFSEL bits for block A pin 7 */ - LM4_GPIO_AFSEL(A) &= ~(0x80); + LM4_GPIO_AFSEL(LM4_GPIO_A) &= ~(0x80); /* Set GPIO to digital enable, output */ - LM4_GPIO_DEN(A) |= 0x80; - LM4_GPIO_DIR(A) |= 0x80; + LM4_GPIO_DEN(LM4_GPIO_A) |= 0x80; + LM4_GPIO_DIR(LM4_GPIO_A) |= 0x80; return EC_SUCCESS; } @@ -38,7 +38,7 @@ int gpio_get(enum gpio_signal signal, int *value_ptr) { switch (signal) { case EC_GPIO_DEBUG_LED: - *value_ptr = (LM4_GPIO_DATA_BITS(A, 0x200) & 0x80 ? 1 : 0); + *value_ptr = (LM4_GPIO_DATA(LM4_GPIO_A, 0x80) & 0x80 ? 1 : 0); return EC_SUCCESS; default: return EC_ERROR_UNKNOWN; @@ -50,7 +50,7 @@ int gpio_set(enum gpio_signal signal, int value) { switch (signal) { case EC_GPIO_DEBUG_LED: - LM4_GPIO_DATA_BITS(A, 0x200) = (value ? 0x80 : 0); + LM4_GPIO_DATA(LM4_GPIO_A, 0x80) = (value ? 0x80 : 0); return EC_SUCCESS; default: return EC_ERROR_UNKNOWN; diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c index 386f24380f..d1cd3ebdb6 100644 --- a/chip/lm4/i2c.c +++ b/chip/lm4/i2c.c @@ -175,12 +175,13 @@ static void configure_gpio(void) scratch = LM4_SYSTEM_RCGCGPIO; /* Use alternate function 3 for PG6:7 */ - LM4_GPIO_AFSEL(G) |= 0xc0; - LM4_GPIO_PCTL(G) = (LM4_GPIO_PCTL(N) & 0x00ffffff) | 0x33000000; - LM4_GPIO_DEN(G) |= 0xc0; + LM4_GPIO_AFSEL(LM4_GPIO_G) |= 0xc0; + LM4_GPIO_PCTL(LM4_GPIO_G) = (LM4_GPIO_PCTL(LM4_GPIO_G) & 0x00ffffff) | + 0x33000000; + LM4_GPIO_DEN(LM4_GPIO_G) |= 0xc0; /* Configure SDA as open-drain. SCL should not be open-drain, * since it has an internal pull-up. */ - LM4_GPIO_ODR(G) |= 0x80; + LM4_GPIO_ODR(LM4_GPIO_G) |= 0x80; } diff --git a/chip/lm4/keyboard_scan.c b/chip/lm4/keyboard_scan.c index e78e8a5241..dd7b9bdb52 100644 --- a/chip/lm4/keyboard_scan.c +++ b/chip/lm4/keyboard_scan.c @@ -48,18 +48,18 @@ static void select_column(int col) { #if defined(EVT) if (col < 0) { - LM4_GPIO_DIR(P) &= ~0xff; - LM4_GPIO_DIR(Q) &= ~0x1f; + LM4_GPIO_DIR(LM4_GPIO_P) &= ~0xff; + LM4_GPIO_DIR(LM4_GPIO_Q) &= ~0x1f; } else if (col < 8) { - LM4_GPIO_DIR(P) &= ~0xff; - LM4_GPIO_DIR(Q) &= ~0x1f; - LM4_GPIO_DATA_BITS(P, 0xff << 2) = ~(1 << col); - LM4_GPIO_DIR(P) = (1 << col) & 0xff; + LM4_GPIO_DIR(LM4_GPIO_P) &= ~0xff; + LM4_GPIO_DIR(LM4_GPIO_Q) &= ~0x1f; + LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = ~(1 << col); + LM4_GPIO_DIR(LM4_GPIO_P) = (1 << col) & 0xff; } else { - LM4_GPIO_DIR(P) &= ~0xff; - LM4_GPIO_DIR(Q) &= ~0x1f; - LM4_GPIO_DATA_BITS(Q, 0xff << 2) = ~(1 << (col - 8)); - LM4_GPIO_DIR(Q) |= 1 << (col - 8); + LM4_GPIO_DIR(LM4_GPIO_P) &= ~0xff; + LM4_GPIO_DIR(LM4_GPIO_Q) &= ~0x1f; + LM4_GPIO_DATA(LM4_GPIO_Q, 0xff) = ~(1 << (col - 8)); + LM4_GPIO_DIR(LM4_GPIO_Q) |= 1 << (col - 8); } #else /* BDS definition */ /* Somehow the col 10 and 11 are swapped on bds. */ @@ -71,24 +71,25 @@ static void select_column(int col) if (col < 0) { /* All tri-stated */ - LM4_GPIO_DIR(Q) = 0; - LM4_GPIO_DIR(K) &= ~0x0f; - LM4_GPIO_DIR(N) &= ~0x04; + LM4_GPIO_DIR(LM4_GPIO_Q) = 0; + LM4_GPIO_DIR(LM4_GPIO_K) &= ~0x0f; + LM4_GPIO_DIR(LM4_GPIO_N) &= ~0x04; } else if (col < 8) { - LM4_GPIO_DIR(Q) = 1 << col; - LM4_GPIO_DIR(K) &= ~0x0f; - LM4_GPIO_DIR(N) &= ~0x04; - LM4_GPIO_DATA_BITS(Q, 0xff << 2) = ~(1 << col); + LM4_GPIO_DIR(LM4_GPIO_Q) = 1 << col; + LM4_GPIO_DIR(LM4_GPIO_K) &= ~0x0f; + LM4_GPIO_DIR(LM4_GPIO_N) &= ~0x04; + LM4_GPIO_DATA(LM4_GPIO_Q, 0xff) = ~(1 << col); } else if (col < 12) { - LM4_GPIO_DIR(Q) = 0; - LM4_GPIO_DIR(K) = (LM4_GPIO_DIR(K) & ~0x0f) | (1 << (col - 8)); - LM4_GPIO_DIR(N) &= ~0x04; - LM4_GPIO_DATA_BITS(K, 0x0f << 2) = ~(1 << (col - 8)); + LM4_GPIO_DIR(LM4_GPIO_Q) = 0; + LM4_GPIO_DIR(LM4_GPIO_K) = (LM4_GPIO_DIR(LM4_GPIO_K) & ~0x0f) | + (1 << (col - 8)); + LM4_GPIO_DIR(LM4_GPIO_N) &= ~0x04; + LM4_GPIO_DATA(LM4_GPIO_K, 0x0f) = ~(1 << (col - 8)); } else { /* col == 12 */ - LM4_GPIO_DIR(Q) = 0; - LM4_GPIO_DIR(K) &= ~0x0f; - LM4_GPIO_DIR(N) |= 0x04; - LM4_GPIO_DATA_BITS(N, 0x04 << 2) = ~0x04; + LM4_GPIO_DIR(LM4_GPIO_Q) = 0; + LM4_GPIO_DIR(LM4_GPIO_K) &= ~0x0f; + LM4_GPIO_DIR(LM4_GPIO_N) |= 0x04; + LM4_GPIO_DATA(LM4_GPIO_N, 0x04) = ~0x04; } #endif } @@ -110,41 +111,41 @@ int keyboard_scan_init(void) /* Clear GPIOAFSEL and enable digital function for PC5, PH0:7, * PK0:3, PN2, PQ0:7. */ - LM4_GPIO_AFSEL(C) &= ~0x20; - LM4_GPIO_DEN(C) |= 0x20; + LM4_GPIO_AFSEL(LM4_GPIO_C) &= ~0x20; + LM4_GPIO_DEN(LM4_GPIO_C) |= 0x20; #if defined(EVT) - LM4_GPIO_AFSEL(N) &= 0xff; /* KSI[7:0] */ - LM4_GPIO_DEN(N) |= 0xff; - LM4_GPIO_AFSEL(P) &= 0xff; /* KSO[7:0] */ - LM4_GPIO_DEN(P) |= 0xff; - LM4_GPIO_AFSEL(Q) &= 0x1f; /* KSO[12:8] */ - LM4_GPIO_DEN(Q) |= 0x1f; + LM4_GPIO_AFSEL(LM4_GPIO_N) &= 0xff; /* KSI[7:0] */ + LM4_GPIO_DEN(LM4_GPIO_N) |= 0xff; + LM4_GPIO_AFSEL(LM4_GPIO_P) &= 0xff; /* KSO[7:0] */ + LM4_GPIO_DEN(LM4_GPIO_P) |= 0xff; + LM4_GPIO_AFSEL(LM4_GPIO_Q) &= 0x1f; /* KSO[12:8] */ + LM4_GPIO_DEN(LM4_GPIO_Q) |= 0x1f; #else - LM4_GPIO_AFSEL(H) = 0; - LM4_GPIO_DEN(H) = 0xff; - LM4_GPIO_AFSEL(K) &= ~0x0f; - LM4_GPIO_DEN(K) |= 0x0f; - LM4_GPIO_AFSEL(N) &= ~0x04; - LM4_GPIO_DEN(N) |= 0x04; - LM4_GPIO_AFSEL(Q) = 0; - LM4_GPIO_DEN(Q) = 0xff; + LM4_GPIO_AFSEL(LM4_GPIO_H) = 0; + LM4_GPIO_DEN(LM4_GPIO_H) = 0xff; + LM4_GPIO_AFSEL(LM4_GPIO_K) &= ~0x0f; + LM4_GPIO_DEN(LM4_GPIO_K) |= 0x0f; + LM4_GPIO_AFSEL(LM4_GPIO_N) &= ~0x04; + LM4_GPIO_DEN(LM4_GPIO_N) |= 0x04; + LM4_GPIO_AFSEL(LM4_GPIO_Q) = 0; + LM4_GPIO_DEN(LM4_GPIO_Q) = 0xff; #endif #if defined(EVT) /* Set PN0:7 as inputs with pull-up */ - LM4_GPIO_DIR(N) = 0; - LM4_GPIO_PUR(N) = 0xff; + LM4_GPIO_DIR(LM4_GPIO_N) = 0; + LM4_GPIO_PUR(LM4_GPIO_N) = 0xff; #else /* Set PH0:7 as inputs with pull-up */ - LM4_GPIO_DIR(H) = 0; - LM4_GPIO_PUR(H) = 0xff; + LM4_GPIO_DIR(LM4_GPIO_H) = 0; + LM4_GPIO_PUR(LM4_GPIO_H) = 0xff; #endif /* Set PC5 as input with pull-up. */ /* TODO: no need for pull-up on real circuit, since it'll be * externally pulled up. */ - LM4_GPIO_DIR(C) &= ~0x04; - LM4_GPIO_PUR(C) |= 0x04; + LM4_GPIO_DIR(LM4_GPIO_C) &= ~0x04; + LM4_GPIO_PUR(LM4_GPIO_C) |= 0x04; /* Tri-state the columns */ select_column(-1); @@ -173,9 +174,9 @@ void check_keys_down(void) usleep(20); /* Read the row state */ #if defined(EVT) - r = LM4_GPIO_DATA_BITS(N, 0xff << 2); + r = LM4_GPIO_DATA(LM4_GPIO_N, 0xff); #else - r = LM4_GPIO_DATA_BITS(H, 0xff << 2); + r = LM4_GPIO_DATA(LM4_GPIO_H, 0xff); #endif /* Invert it so 0=not pressed, 1=pressed */ r ^= 0xff; diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index 962b4f07ba..68f12c230d 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -29,18 +29,18 @@ static void configure_gpio(void) /* I/O: PL0:3 = command/address/data * inp: PL4 (frame), PL5 (reset), PM0 (powerdown), PM5 (clock) * out: PM1 (sci), PM2 (clkrun), PM4 (serirq) */ - LM4_GPIO_AFSEL(L) |= 0x3f; - LM4_GPIO_AFSEL(M) |= 0x37; - LM4_GPIO_PCTL(L) |= 0x00ffffff; - LM4_GPIO_PCTL(M) |= 0x00ff0fff; - LM4_GPIO_DEN(L) |= 0x3f; - LM4_GPIO_DEN(M) |= 0x37; + LM4_GPIO_AFSEL(LM4_GPIO_L) |= 0x3f; + LM4_GPIO_AFSEL(LM4_GPIO_M) |= 0x37; + LM4_GPIO_PCTL(LM4_GPIO_L) |= 0x00ffffff; + LM4_GPIO_PCTL(LM4_GPIO_M) |= 0x00ff0fff; + LM4_GPIO_DEN(LM4_GPIO_L) |= 0x3f; + LM4_GPIO_DEN(LM4_GPIO_M) |= 0x37; /* Set the drive strength to 8mA for serirq only */ /* TODO: Only necessary on BDS because the cabling to the x86 * is long and flaky; remove this for Link. Setting this for all * I/O lines seems to hang the x86 during boot. */ - LM4_GPIO_DR8R(M) |= 0x00000010; + LM4_GPIO_DR8R(LM4_GPIO_M) |= 0x00000010; } diff --git a/chip/lm4/pwm.c b/chip/lm4/pwm.c index da9acb5e89..1ce97887a2 100644 --- a/chip/lm4/pwm.c +++ b/chip/lm4/pwm.c @@ -32,15 +32,17 @@ static void configure_gpios(void) /* Use alternate function 1 for PN4 (channel 3 PWM) and PN6:7 (channel 4 PWM/tach) */ // TODO: depends on which PWMs we're using - LM4_GPIO_AFSEL(N) |= 0xd0; - LM4_GPIO_PCTL(N) = (LM4_GPIO_PCTL(N) & 0x00f0ffff) | 0x11010000; - LM4_GPIO_DEN(N) |= 0xd0; + LM4_GPIO_AFSEL(LM4_GPIO_N) |= 0xd0; + LM4_GPIO_PCTL(LM4_GPIO_N) = (LM4_GPIO_PCTL(LM4_GPIO_N) & 0x00f0ffff) | + 0x11010000; + LM4_GPIO_DEN(LM4_GPIO_N) |= 0xd0; /* Use alternate function 1 for PK6 (channel 1 PWM) */ // TODO: GPIO module depends on fan channel - LM4_GPIO_AFSEL(K) |= 0x40; - LM4_GPIO_PCTL(K) = (LM4_GPIO_PCTL(K) & 0xf0ffffff) | 0x01000000; - LM4_GPIO_DEN(K) |= 0x40; + LM4_GPIO_AFSEL(LM4_GPIO_K) |= 0x40; + LM4_GPIO_PCTL(LM4_GPIO_K) = (LM4_GPIO_PCTL(LM4_GPIO_K) & 0xf0ffffff) | + 0x01000000; + LM4_GPIO_DEN(LM4_GPIO_K) |= 0x40; } diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index 8038ac9b4b..df701efd53 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -1,7 +1,6 @@ /* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. - * Copyright 2011 Google Inc. * * Register map for LM4x processor */ @@ -49,7 +48,12 @@ static inline int lm4_uart_addr(int ch, int offset) #define LM4_ADC_SS1_BASE 0x40038060 #define LM4_ADC_SS2_BASE 0x40038080 #define LM4_ADC_SS3_BASE 0x400380a0 -#define LM4ADCREG(ss, offset) LM4REG(LM4_ADC_SS##ss##_BASE + (offset)) +#define LM4_ADC_SS_SEP 0x00000020 +static inline int lm4_adc_addr(int ss, int offset) +{ + return offset + LM4_ADC_SS0_BASE + LM4_ADC_SS_SEP * ss; +} +#define LM4ADCREG(ss, offset) LM4REG(lm4_adc_addr(ss, offset)) #define LM4_ADC_SSMUX(ss) LM4ADCREG(ss, 0x000) #define LM4_ADC_SSCTL(ss) LM4ADCREG(ss, 0x004) #define LM4_ADC_SSFIFO(ss) LM4ADCREG(ss, 0x008) @@ -95,7 +99,12 @@ static inline int lm4_lpc_addr(int ch, int offset) #define LM4_FAN_CH3_BASE 0x40084040 #define LM4_FAN_CH4_BASE 0x40084050 #define LM4_FAN_CH5_BASE 0x40084060 -#define LM4FANREG(ch, offset) LM4REG(LM4_FAN_CH##ch##_BASE + (offset)) +#define LM4_FAN_CH_SEP 0x00000010 +static inline int lm4_fan_addr(int ch, int offset) +{ + return offset + LM4_FAN_CH0_BASE + LM4_FAN_CH_SEP * ch; +} +#define LM4FANREG(ch, offset) LM4REG(lm4_fan_addr(ch, offset)) #define LM4_FAN_FANCH(ch) LM4FANREG(ch, 0x000) #define LM4_FAN_FANCMD(ch) LM4FANREG(ch, 0x004) #define LM4_FAN_FANCST(ch) LM4FANREG(ch, 0x008) @@ -218,10 +227,24 @@ static inline int lm4_lpc_addr(int ch, int offset) #define LM4_GPIO_PORTG_AHB_BASE 0x4005E000 #define LM4_GPIO_PORTH_AHB_BASE 0x4005F000 #define LM4_GPIO_PORTJ_AHB_BASE 0x40060000 - -#define LM4GPIOREG(port, offset) LM4REG(LM4_GPIO_PORT##port##_BASE + (offset)) - -#define LM4_GPIO_DATA_BITS(port, off) LM4GPIOREG(port, 0x000 + (off)) +/* Ports for passing to LM4GPIOREG(); abstracted from base addresses above so + * that we can switch to/from AHB. */ +#define LM4_GPIO_A LM4_GPIO_PORTA_BASE +#define LM4_GPIO_B LM4_GPIO_PORTB_BASE +#define LM4_GPIO_C LM4_GPIO_PORTC_BASE +#define LM4_GPIO_D LM4_GPIO_PORTD_BASE +#define LM4_GPIO_E LM4_GPIO_PORTE_BASE +#define LM4_GPIO_F LM4_GPIO_PORTF_BASE +#define LM4_GPIO_G LM4_GPIO_PORTG_BASE +#define LM4_GPIO_H LM4_GPIO_PORTH_BASE +#define LM4_GPIO_K LM4_GPIO_PORTK_BASE +#define LM4_GPIO_L LM4_GPIO_PORTL_BASE +#define LM4_GPIO_M LM4_GPIO_PORTM_BASE +#define LM4_GPIO_N LM4_GPIO_PORTN_BASE +#define LM4_GPIO_P LM4_GPIO_PORTP_BASE +#define LM4_GPIO_Q LM4_GPIO_PORTQ_BASE +#define LM4GPIOREG(port, offset) LM4REG((port) + (offset)) +#define LM4_GPIO_DATA(port, mask) LM4GPIOREG(port, ((mask) << 2)) #define LM4_GPIO_DIR(port) LM4GPIOREG(port, 0x400) #define LM4_GPIO_IS(port) LM4GPIOREG(port, 0x404) #define LM4_GPIO_IBE(port) LM4GPIOREG(port, 0x408) @@ -275,64 +298,74 @@ static inline int lm4_i2c_addr(int port, int offset) /* Timers */ -#define LM4TIMERREG(tmr, offset) LM4REG(LM4_TIMER##tmr##_BASE + (offset)) - +/* Timers 0-5 are 16/32 bit */ #define LM4_TIMER0_BASE 0x40030000 #define LM4_TIMER1_BASE 0x40031000 #define LM4_TIMER2_BASE 0x40032000 #define LM4_TIMER3_BASE 0x40033000 #define LM4_TIMER4_BASE 0x40034000 #define LM4_TIMER5_BASE 0x40035000 +/* Timers 6-11 are 32/64 bit */ #define LM4_TIMERW0_BASE 0x40036000 #define LM4_TIMERW1_BASE 0x40037000 -#define LM4_TIMERW2_BASE 0x4004C000 -#define LM4_TIMERW3_BASE 0x4004D000 -#define LM4_TIMERW4_BASE 0x4004E000 -#define LM4_TIMERW5_BASE 0x4004F000 - +#define LM4_TIMERW2_BASE 0x4004c000 +#define LM4_TIMERW3_BASE 0x4004d000 +#define LM4_TIMERW4_BASE 0x4004e000 +#define LM4_TIMERW5_BASE 0x4004f000 +#define LM4_TIMER_SEP 0x00001000 +static inline int lm4_timer_addr(int timer, int offset) +{ + if (timer < 8) + return offset + LM4_TIMER0_BASE + LM4_TIMER_SEP * timer; + else + return offset + LM4_TIMERW2_BASE + LM4_TIMER_SEP * (timer - 8); +} +#define LM4TIMERREG(timer, offset) LM4REG(lm4_timer_addr(timer, offset)) #define LM4_TIMER_CFG(tmr) LM4TIMERREG(tmr, 0x00) #define LM4_TIMER_TAMR(tmr) LM4TIMERREG(tmr, 0x04) #define LM4_TIMER_TBMR(tmr) LM4TIMERREG(tmr, 0x08) -#define LM4_TIMER_CTL(tmr) LM4TIMERREG(tmr, 0x0C) +#define LM4_TIMER_CTL(tmr) LM4TIMERREG(tmr, 0x0c) #define LM4_TIMER_SYNC(tmr) LM4TIMERREG(tmr, 0x10) #define LM4_TIMER_IMR(tmr) LM4TIMERREG(tmr, 0x18) -#define LM4_TIMER_RIS(tmr) LM4TIMERREG(tmr, 0x1C) +#define LM4_TIMER_RIS(tmr) LM4TIMERREG(tmr, 0x1c) #define LM4_TIMER_MIS(tmr) LM4TIMERREG(tmr, 0x20) #define LM4_TIMER_ICR(tmr) LM4TIMERREG(tmr, 0x24) #define LM4_TIMER_TAILR(tmr) LM4TIMERREG(tmr, 0x28) -#define LM4_TIMER_TBILR(tmr) LM4TIMERREG(tmr, 0x2C) +#define LM4_TIMER_TBILR(tmr) LM4TIMERREG(tmr, 0x2c) #define LM4_TIMER_TAMATCHR(tmr) LM4TIMERREG(tmr, 0x30) #define LM4_TIMER_TBMATCHR(tmr) LM4TIMERREG(tmr, 0x34) #define LM4_TIMER_TAPR(tmr) LM4TIMERREG(tmr, 0x38) -#define LM4_TIMER_TBPR(tmr) LM4TIMERREG(tmr, 0x3C) +#define LM4_TIMER_TBPR(tmr) LM4TIMERREG(tmr, 0x3c) #define LM4_TIMER_TAPMR(tmr) LM4TIMERREG(tmr, 0x40) #define LM4_TIMER_TBPMR(tmr) LM4TIMERREG(tmr, 0x44) #define LM4_TIMER_TAR(tmr) LM4TIMERREG(tmr, 0x48) -#define LM4_TIMER_TBR(tmr) LM4TIMERREG(tmr, 0x4C) +#define LM4_TIMER_TBR(tmr) LM4TIMERREG(tmr, 0x4c) #define LM4_TIMER_TAV(tmr) LM4TIMERREG(tmr, 0x50) #define LM4_TIMER_TBV(tmr) LM4TIMERREG(tmr, 0x54) #define LM4_TIMER_RTCPD(tmr) LM4TIMERREG(tmr, 0x58) -#define LM4_TIMER_TAPS(tmr) LM4TIMERREG(tmr, 0x5C) +#define LM4_TIMER_TAPS(tmr) LM4TIMERREG(tmr, 0x5c) #define LM4_TIMER_TBPS(tmr) LM4TIMERREG(tmr, 0x60) #define LM4_TIMER_TAPV(tmr) LM4TIMERREG(tmr, 0x64) #define LM4_TIMER_TBPV(tmr) LM4TIMERREG(tmr, 0x68) -#define LM4_SYSTICK_CTRL LM4REG(0xE000E010) -#define LM4_SYSTICK_RELOAD LM4REG(0xE000E014) -#define LM4_SYSTICK_CURRENT LM4REG(0xE000E018) +#define LM4_SYSTICK_CTRL LM4REG(0xe000e010) +#define LM4_SYSTICK_RELOAD LM4REG(0xe000e014) +#define LM4_SYSTICK_CURRENT LM4REG(0xe000e018) /* Watchdogs */ -#define LM4WDTREG(num, offset) LM4REG(LM4_WATCHDOG##num##_BASE + (offset)) - #define LM4_WATCHDOG0_BASE 0x40000000 #define LM4_WATCHDOG1_BASE 0x40001000 - +static inline int lm4_watchdog_addr(int num, int offset) +{ + return offset + (num ? LM4_WATCHDOG1_BASE : LM4_WATCHDOG0_BASE); +} +#define LM4WDTREG(num, offset) LM4REG(lm4_watchdog_addr(num, offset)) #define LM4_WATCHDOG_LOAD(n) LM4WDTREG(n, 0x000) #define LM4_WATCHDOG_VALUE(n) LM4WDTREG(n, 0x004) #define LM4_WATCHDOG_CTL(n) LM4WDTREG(n, 0x008) -#define LM4_WATCHDOG_ICR(n) LM4WDTREG(n, 0x00C) +#define LM4_WATCHDOG_ICR(n) LM4WDTREG(n, 0x00c) #define LM4_WATCHDOG_RIS(n) LM4WDTREG(n, 0x010) #define LM4_WATCHDOG_TEST(n) LM4WDTREG(n, 0x418) -#define LM4_WATCHDOG_LOCK(n) LM4WDTREG(n, 0xC00) +#define LM4_WATCHDOG_LOCK(n) LM4WDTREG(n, 0xc00) #endif /* __LM4_REGISTERS */ diff --git a/chip/lm4/timer.c b/chip/lm4/timer.c index 5d83edba4b..9c273a0d9b 100644 --- a/chip/lm4/timer.c +++ b/chip/lm4/timer.c @@ -35,20 +35,20 @@ static uint32_t next_deadline = 0xffffffff; void __hw_clock_event_set(uint32_t deadline) { /* set the match on the deadline */ - LM4_TIMER_TAMATCHR(W0) = 0xffffffff - deadline; + LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline; /* Set the match interrupt */ - LM4_TIMER_IMR(W0) |= 0x10; + LM4_TIMER_IMR(6) |= 0x10; } void __hw_clock_event_clear(void) { /* Disable the match interrupt */ - LM4_TIMER_IMR(W0) &= ~0x10; + LM4_TIMER_IMR(6) &= ~0x10; } static uint32_t __hw_clock_source_read(void) { - return 0xffffffff - LM4_TIMER_TAV(W0); + return 0xffffffff - LM4_TIMER_TAV(6); } static void expire_timer(task_id_t tskid) @@ -107,10 +107,10 @@ reprocess_timers: static void __hw_clock_source_irq(void) { - uint32_t status = LM4_TIMER_RIS(W0); + uint32_t status = LM4_TIMER_RIS(6); /* clear interrupt */ - LM4_TIMER_ICR(W0) = status; + LM4_TIMER_ICR(6) = status; /* free running counter as overflowed */ if (status & 0x01) { clksrc_high++; @@ -133,19 +133,19 @@ static void __hw_clock_source_init(void) scratch = LM4_SYSTEM_RCGCWTIMER; /* Ensure timer is disabled : TAEN = TBEN = 0 */ - LM4_TIMER_CTL(W0) &= ~0x101; + LM4_TIMER_CTL(6) &= ~0x101; /* Set overflow interrupt */ - LM4_TIMER_IMR(W0) = 0x1; + LM4_TIMER_IMR(6) = 0x1; /* 32-bit timer mode */ - LM4_TIMER_CFG(W0) = 4; + LM4_TIMER_CFG(6) = 4; /* set the prescaler to increment every microsecond */ - LM4_TIMER_TAPR(W0) = CLOCKSOURCE_DIVIDER; + LM4_TIMER_TAPR(6) = CLOCKSOURCE_DIVIDER; /* Periodic mode, counting down */ - LM4_TIMER_TAMR(W0) = 0x22; + LM4_TIMER_TAMR(6) = 0x22; /* use the full 32-bits of the timer */ - LM4_TIMER_TAILR(W0) = 0xffffffff; + LM4_TIMER_TAILR(6) = 0xffffffff; /* Starts counting in timer A */ - LM4_TIMER_CTL(W0) |= 0x1; + LM4_TIMER_CTL(6) |= 0x1; } @@ -245,7 +245,7 @@ int command_timer_info(int argc, char **argv) "Deadline: 0x%08x%08x us\n" "Active timers:\n", ts.le.hi, ts.le.lo, clksrc_high, - 0xffffffff -LM4_TIMER_TAMATCHR(W0)); + 0xffffffff - LM4_TIMER_TAMATCHR(6)); for (tskid = 0; tskid < TASK_ID_COUNT; tskid++) { if (timer_running & (1<<tskid)) uart_printf("Tsk %d tmr 0x%08x%08x\n", tskid, diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c index 430c3ecde0..2ff4901d09 100644 --- a/chip/lm4/uart.c +++ b/chip/lm4/uart.c @@ -164,19 +164,21 @@ static void configure_gpio(void) /* UART0 setup; RX and TX are GPIO PA0 and PA1 */ /* Enable alternate function */ - LM4_GPIO_AFSEL(A) |= 0x03; + LM4_GPIO_AFSEL(LM4_GPIO_A) |= 0x03; /* Alternate function 1 */ - LM4_GPIO_PCTL(A) = (LM4_GPIO_PCTL(A) & 0xffffff00) | 0x11; + LM4_GPIO_PCTL(LM4_GPIO_A) = (LM4_GPIO_PCTL(LM4_GPIO_A) & 0xffffff00) + | 0x11; /* Enable digital function */ - LM4_GPIO_DEN(A) |= 0x03; + LM4_GPIO_DEN(LM4_GPIO_A) |= 0x03; /* UART1 setup; RX and TX are GPIO PB0 and PB1 */ /* Enable alternate function */ - LM4_GPIO_AFSEL(B) |= 0x03; + LM4_GPIO_AFSEL(LM4_GPIO_B) |= 0x03; /* Alternate function 1 */ - LM4_GPIO_PCTL(B) = (LM4_GPIO_PCTL(B) & 0xffffff00) | 0x11; + LM4_GPIO_PCTL(LM4_GPIO_B) = (LM4_GPIO_PCTL(LM4_GPIO_B) & 0xffffff00) + | 0x11; /* Enable digital function */ - LM4_GPIO_DEN(B) = 0x03; + LM4_GPIO_DEN(LM4_GPIO_B) = 0x03; } diff --git a/chip/lm4/x86_power.c b/chip/lm4/x86_power.c index cda5dcd0eb..2abeaf2c35 100644 --- a/chip/lm4/x86_power.c +++ b/chip/lm4/x86_power.c @@ -30,7 +30,7 @@ enum x86_signal { * PCH_DPWROK via resistor */ PM_SLP_SUS#, PD3, inp, SLP_SUS SLP_A#, PG5, i/o, SLP_A# /* Intel claims inp; why does - * schematic claim I/O? */ + * schematic claim I/O? */ SLP_ME_CSW_DEV#, PG4, i/o, SLP_ME_CSW_DEV# /* Intel also claims * inp? */ PM_SLP_S3#, PJ0, inp, SLP_S3# @@ -121,7 +121,7 @@ struct signal_gpio { }; struct signal_gpio gpios[] = { - + }; @@ -131,20 +131,6 @@ struct signal_gpio gpios[] = { int x86_power_init(void) { -#if 0 - /* Enable clock to GPIO block A */ - LM4_SYSTEM_RCGCGPIO |= 0x0001; - - /* Turn off the LED before we make it an output */ - gpio_set(EC_GPIO_DEBUG_LED, 0); - - /* Clear GPIOAFSEL bits for block A pin 7 */ - LM4_GPIO_AFSEL(A) &= ~(0x80); - - /* Set GPIO to digital enable, output */ - LM4_GPIO_DEN(A) |= 0x80; - LM4_GPIO_DIR(A) |= 0x80; -#endif return EC_SUCCESS; } diff --git a/test/powerdemo.c b/test/powerdemo.c index 9074f3505b..1fe4e00ee8 100644 --- a/test/powerdemo.c +++ b/test/powerdemo.c @@ -33,9 +33,9 @@ static volatile enum { static void __stop_timer(void) { /* Disable timer A */ - LM4_TIMER_CTL(W1) &= ~0x01; + LM4_TIMER_CTL(7) &= ~0x01; /* Clear any pending interrupts */ - LM4_TIMER_ICR(W1) = LM4_TIMER_RIS(W1); + LM4_TIMER_ICR(7) = LM4_TIMER_RIS(7); } @@ -46,15 +46,15 @@ static void __start_timer(int usec) /* Stop the timer, if it was started */ __stop_timer(); /* Set the delay, counting function overhead */ - LM4_TIMER_TAILR(W1) = usec; + LM4_TIMER_TAILR(7) = usec; /* Start timer A */ - LM4_TIMER_CTL(W1) |= 0x01; + LM4_TIMER_CTL(7) |= 0x01; } static void __set_state(int new_state, int pin_value, int timeout) { - LM4_GPIO_DATA_BITS(D, 0x08 << 2) = (pin_value ? 0x08 : 0); + LM4_GPIO_DATA(LM4_GPIO_D, 0x08) = (pin_value ? 0x08 : 0); if (timeout) __start_timer(timeout); else @@ -73,36 +73,36 @@ int power_demo_init(void) /* wait 3 clock cycles before using the module */ scratch = LM4_SYSTEM_RCGCWTIMER; /* Ensure timer is disabled : TAEN = TBEN = 0 */ - LM4_TIMER_CTL(W1) &= ~0x101; + LM4_TIMER_CTL(7) &= ~0x101; /* 32-bit timer mode */ - LM4_TIMER_CFG(W1) = 4; + LM4_TIMER_CFG(7) = 4; /* Set the prescaler to increment every microsecond */ - LM4_TIMER_TAPR(W1) = CLOCKSOURCE_DIVIDER; + LM4_TIMER_TAPR(7) = CLOCKSOURCE_DIVIDER; /* One-shot, counting down */ - LM4_TIMER_TAMR(W1) = 0x01; + LM4_TIMER_TAMR(7) = 0x01; /* Set overflow interrupt */ - LM4_TIMER_IMR(W1) = 0x1; + LM4_TIMER_IMR(7) = 0x1; /* Enable clock to GPIO module D */ LM4_SYSTEM_RCGCGPIO |= 0x0008; /* Clear GPIOAFSEL and enable digital function for pins 0-3 */ - LM4_GPIO_AFSEL(D) &= ~0x0f; - LM4_GPIO_DEN(D) |= 0x0f; + LM4_GPIO_AFSEL(LM4_GPIO_D) &= ~0x0f; + LM4_GPIO_DEN(LM4_GPIO_D) |= 0x0f; /* Set pins 0-2 as input, pin 3 as output */ - LM4_GPIO_DIR(D) = (LM4_GPIO_DIR(D) & ~0x0f) | 0x08; + LM4_GPIO_DIR(LM4_GPIO_D) = (LM4_GPIO_DIR(LM4_GPIO_D) & ~0x0f) | 0x08; /* Set pin 0 to edge-sensitive, both edges, pull-up */ - LM4_GPIO_IS(D) &= ~0x01; - LM4_GPIO_IBE(D) |= 0x01; - LM4_GPIO_PUR(D) |= 0x01; + LM4_GPIO_IS(LM4_GPIO_D) &= ~0x01; + LM4_GPIO_IBE(LM4_GPIO_D) |= 0x01; + LM4_GPIO_PUR(LM4_GPIO_D) |= 0x01; /* Move to idle state */ __set_state(POWER_STATE_IDLE, 1, 0); /* Enable interrupt on pin 0 */ - LM4_GPIO_IM(D) |= 0x01; + LM4_GPIO_IM(LM4_GPIO_D) |= 0x01; return EC_SUCCESS; } @@ -111,14 +111,14 @@ int power_demo_init(void) /* GPIO interrupt handler */ static void __gpio_d_interrupt(void) { - uint32_t mis = LM4_GPIO_MIS(D); + uint32_t mis = LM4_GPIO_MIS(LM4_GPIO_D); /* Clear the interrupt bits we're handling */ - LM4_GPIO_ICR(D) = mis; + LM4_GPIO_ICR(LM4_GPIO_D) = mis; /* Handle edges */ if (mis & 0x01) { - if (LM4_GPIO_DATA_BITS(D, 0x01 << 2)) { + if (LM4_GPIO_DATA(LM4_GPIO_D, 0x01)) { if (state == POWER_STATE_WAIT) __set_state(POWER_STATE_DOWN2, 0, 2000 - 28); } else { @@ -134,9 +134,9 @@ DECLARE_IRQ(3, __gpio_d_interrupt, 1); /* Timer interrupt handler */ static void __timer_w1_interrupt(void) { - uint32_t mis = LM4_TIMER_RIS(W1); + uint32_t mis = LM4_TIMER_RIS(7); /* Clear the interrupt reasons we're handling */ - LM4_TIMER_ICR(W1) = mis; + LM4_TIMER_ICR(7) = mis; /* Transition to next state */ switch (state) { @@ -157,7 +157,7 @@ static void __timer_w1_interrupt(void) __set_state(POWER_STATE_DOWN15, 0, 15000 - 328); break; case POWER_STATE_DOWN15: - if (LM4_GPIO_DATA_BITS(D, 0x01 << 2)) { + if (LM4_GPIO_DATA(LM4_GPIO_D, 0x01)) { /* Button has already been released; go straight to * idle */ __set_state(POWER_STATE_IDLE, 1, 0); |