diff options
| -rw-r--r-- | chip/it83xx/pwm.c | 8 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c index 8aae12b9a1..6328c69b46 100644 --- a/chip/it83xx/pwm.c +++ b/chip/it83xx/pwm.c @@ -265,6 +265,14 @@ static void pwm_init(void) for (ch = 0; ch < PWM_CH_COUNT; ch++) pwm_ch_freq(ch); + /* + * The cycle timer1 of chip 8320 later series was enhanced from + * 8bits to 10bits resolution, and others are still 8bit resolution. + * Because the cycle timer1 high byte default value is not zero, + * we clear cycle timer1 high byte at init and use it as 8-bit + * resolution like others. + */ + IT83XX_PWM_CTR1M = 0; /* enable PWMs clock counter. */ IT83XX_PWM_ZTIER |= 0x02; } diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index febf5093c9..b5bcd59ca0 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1001,6 +1001,7 @@ enum clock_gate_offsets { #define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE+0x0D) #define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE+0x0E) #define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE+0x0F) +#define IT83XX_PWM_CTR1M REG8(IT83XX_PWM_BASE+0x10) #define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE+0x1E) #define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE+0x1F) #define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE+0x20) |