diff options
| -rw-r--r-- | baseboard/octopus/variant_usbc_standalone_tcpcs.c | 18 | ||||
| -rw-r--r-- | board/bobba/gpio.inc | 1 | ||||
| -rw-r--r-- | board/fleex/gpio.inc | 2 | ||||
| -rw-r--r-- | board/meep/gpio.inc | 3 | ||||
| -rw-r--r-- | board/phaser/gpio.inc | 5 | ||||
| -rw-r--r-- | board/yorp/gpio.inc | 3 | ||||
| -rw-r--r-- | driver/tcpm/anx7447.h | 9 |
7 files changed, 36 insertions, 5 deletions
diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c index 2068231519..b4affc197c 100644 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c @@ -124,7 +124,23 @@ uint16_t tcpc_get_alert_status(void) */ void board_reset_pd_mcu(void) { - /* C0: ANX7447 does not have a reset pin. */ + /* + * C0: Assert reset to TCPC0 (ANX7447) for required delay (1ms) only if + * we have a battery + * + * Note: The TEST_R pin is not hooked up to a GPIO on all boards, so + * verify the name exists before setting it. After the name is + * introduced for later board firmware, this pin will still be wired + * to USB2_OTG_ID on the proto boards, which should be set to open + * drain so it can't be driven high. + */ + if (gpio_is_implemented(GPIO_USB_C0_PD_RST) && + battery_is_present() == BP_YES) { + gpio_set_level(GPIO_USB_C0_PD_RST, 1); + msleep(ANX74XX_RESET_HOLD_MS); + gpio_set_level(GPIO_USB_C0_PD_RST, 0); + msleep(ANX74XX_RESET_FINISH_MS); + } /* * C1: Assert reset to TCPC1 (PS8751) for required delay (1ms) only if diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc index bcc918d93c..722d04ff64 100644 --- a/board/bobba/gpio.inc +++ b/board/bobba/gpio.inc @@ -113,7 +113,6 @@ GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ -/* TODO(b/112756630): octopus: add reset logic for C0 TCPC */ GPIO(USB_C0_PD_RST, PIN(8, 3), GPIO_OUT_LOW) /* C0 PD Reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc index 99e71c32a4..294d2ce1b5 100644 --- a/board/fleex/gpio.inc +++ b/board/fleex/gpio.inc @@ -116,8 +116,6 @@ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ /* - * TODO(b/112756630): octopus: add reset logic for C0 TCPC - * * Proto USB2_OTG_ID pin * Configure as default since on proto boards this pin should not be driven high */ diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc index b05068d011..6b3d5c8a6f 100644 --- a/board/meep/gpio.inc +++ b/board/meep/gpio.inc @@ -129,6 +129,9 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) +/* Not implemented in hardware yet */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index 3effe54d91..7205d1bf9d 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -118,7 +118,6 @@ GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ -/* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ @@ -128,6 +127,10 @@ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) + +/* Not implemented in hardware yet */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index d138d530cd..1f5e230623 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -126,6 +126,9 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) +/* Not implemented in hardware */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h index 75f9fd449c..3f4947a556 100644 --- a/driver/tcpm/anx7447.h +++ b/driver/tcpm/anx7447.h @@ -94,6 +94,15 @@ struct anx7447_i2c_addr { #define AN7447_SPI2_I2C_ADDR 0x64 #define AN7447_SPI3_I2C_ADDR 0x62 +/* + * Time TEST_R must be held high for a reset + */ +#define ANX74XX_RESET_HOLD_MS 1 +/* + * Time after TEST_R reset to wait for eFuse loading + */ +#define ANX74XX_RESET_FINISH_MS 2 + int anx7447_set_power_supply_ready(int port); int anx7447_power_supply_reset(int port); int anx7447_board_charging_enable(int port, int enable); |