diff options
| -rw-r--r-- | board/kukui_scp/board.h | 7 | ||||
| -rw-r--r-- | chip/mt_scp/config_chip.h | 2 | ||||
| -rw-r--r-- | chip/mt_scp/system.c | 2 | ||||
| -rw-r--r-- | common/system.c | 2 | ||||
| -rw-r--r-- | core/cortex-m/include/mpu.h | 2 | ||||
| -rw-r--r-- | core/cortex-m/mpu.c | 6 | ||||
| -rw-r--r-- | include/config.h | 19 |
7 files changed, 30 insertions, 10 deletions
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h index 56eb59909e..faab336061 100644 --- a/board/kukui_scp/board.h +++ b/board/kukui_scp/board.h @@ -34,6 +34,8 @@ #define CONFIG_RAM_BASE 0x10000 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) #define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE) +#define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE +#define CONFIG_DATA_RAM_SIZE (ICACHE_BASE - CONFIG_RAM_BASE) #define CONFIG_RO_MEM_OFF 0 /* Access DRAM through cached access */ @@ -87,11 +89,6 @@ #undef UART0_PINMUX_11_12 #undef UART0_PINMUX_110_112 -/* - * Allow dangerous commands all the time, since we don't have a write protect - * switch. - */ -#define CONFIG_SYSTEM_UNLOCKED /* Debugging features */ #define CONFIG_DEBUG_EXCEPTIONS #define CONFIG_DEBUG_STACK_OVERFLOW diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h index d2e6ca3b9d..245c9f1bc6 100644 --- a/chip/mt_scp/config_chip.h +++ b/chip/mt_scp/config_chip.h @@ -37,6 +37,8 @@ #define CONFIG_RW_STORAGE_OFF 0 #define CONFIG_PROGRAM_MEMORY_BASE 0 #define CONFIG_MAPPED_STORAGE_BASE 0 +/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/ +#define CONFIG_MPU /* Unsupported features/commands */ #undef CONFIG_CMD_FLASHINFO diff --git a/chip/mt_scp/system.c b/chip/mt_scp/system.c index 3011b7024f..bd5e2ee36c 100644 --- a/chip/mt_scp/system.c +++ b/chip/mt_scp/system.c @@ -87,6 +87,8 @@ void system_pre_init(void) scp_enable_pirq(); /* Init dram mapping (and cache) */ scp_memmap_init(); + /* Disable jump (mt_scp has only RW) and enable MPU. */ + system_disable_jump(); } void system_reset(int flags) diff --git a/common/system.c b/common/system.c index 53282b278d..430b611174 100644 --- a/common/system.c +++ b/common/system.c @@ -403,7 +403,7 @@ void system_disable_jump(void) return; } -#ifdef CONFIG_EXTERNAL_STORAGE +#if defined(CONFIG_EXTERNAL_STORAGE) || !defined(CONFIG_FLASH_PHYSICAL) /* * Protect code RAM from being overwritten */ diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h index 84a82bb3f8..c252ab6ddc 100644 --- a/core/cortex-m/include/mpu.h +++ b/core/cortex-m/include/mpu.h @@ -58,6 +58,8 @@ enum mpu_region { /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */ #define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */ +#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */ +#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */ #define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */ #define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */ diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c index 8376a00b32..b239de3e57 100644 --- a/core/cortex-m/mpu.c +++ b/core/cortex-m/mpu.c @@ -147,7 +147,7 @@ void mpu_enable(void) MPU_CTRL |= MPU_CTRL_PRIVDEFEN | MPU_CTRL_HFNMIENA | MPU_CTRL_ENABLE; } -void mpu_disable(void) +static void mpu_disable(void) { MPU_CTRL &= ~(MPU_CTRL_PRIVDEFEN | MPU_CTRL_HFNMIENA | MPU_CTRL_ENABLE); } @@ -179,13 +179,13 @@ int mpu_protect_data_ram(void) MPU_ATTR_INTERNAL_SRAM); } -#ifdef CONFIG_EXTERNAL_STORAGE +#if defined(CONFIG_EXTERNAL_STORAGE) || !defined(CONFIG_FLASH_PHYSICAL) int mpu_protect_code_ram(void) { /* Prevent write access to code RAM */ return mpu_config_region(REGION_STORAGE, CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF, - CONFIG_RO_SIZE, + CONFIG_CODE_RAM_SIZE, MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1); } diff --git a/include/config.h b/include/config.h index 22fbe4c6f7..171938d9cc 100644 --- a/include/config.h +++ b/include/config.h @@ -2773,10 +2773,19 @@ * Usually, CONFIG_DATA_RAM_SIZE = CONFIG_RAM_SIZE but some chips need to * allocate RAM for the mask ROM. Then CONFIG_DATA_RAM_SIZE > CONFIG_RAM_SIZE. * + * CONFIG_CODE_RAM_SIZE indicates the size of all code RAM available on the chip + * in bytes. This is needed when a chip with external storage where stored with + * code section, or a chip without an internal flash but need to protect its + * code section by MPU. + * Usually, CONFIG_CODE_RAM_SIZE = CONFIG_RO_SIZE. However, some chips may + * have other value, e.g. mt_scp which doesn't have RO image, and the code RAM + * size is actually its CONFIG_ROM_SIZE plus a reserved memory space. + * * CONFIG_ROM_SIZE indicates the size of ROM allocated by a linker script. This * is only needed when no physical flash present (!CONFIG_FLASH_PHYSICAL). The * ROM region will place common RO setions, e.g. .text, .rodata, .data LMA etc. */ +#undef CONFIG_CODE_RAM_SIZE #undef CONFIG_DATA_RAM_SIZE #undef CONFIG_RAM_SIZE #undef CONFIG_ROM_SIZE @@ -4009,10 +4018,18 @@ /******************************************************************************/ /* + * Set default code ram size unless it's customized by the chip. + */ +#ifndef CONFIG_CODE_RAM_SIZE +#define CONFIG_CODE_RAM_SIZE CONFIG_RO_SIZE +#endif + +/******************************************************************************/ +/* * Set default data ram size unless it's customized by the chip. */ #ifndef CONFIG_DATA_RAM_SIZE -#define CONFIG_DATA_RAM_SIZE CONFIG_RAM_SIZE +#define CONFIG_DATA_RAM_SIZE CONFIG_RAM_SIZE #endif /******************************************************************************/ |