diff options
| -rw-r--r-- | chip/stm32/clock-f.c | 18 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 2 |
2 files changed, 19 insertions, 1 deletions
diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c index 1d28fa2168..e9737ddb14 100644 --- a/chip/stm32/clock-f.c +++ b/chip/stm32/clock-f.c @@ -165,14 +165,30 @@ void clock_init(void) * put 1 Wait-State for flash access to ensure proper reads at 48Mhz * and enable prefetch buffer. */ - /* Enable data and instruction cache. */ STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; +#ifdef CHIP_FAMILY_STM32F4 + /* Enable data and instruction cache. */ + STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN; +#endif + config_hispeed_clock(); rtc_init(); } +#ifdef CHIP_FAMILY_STM32F4 +void reset_flash_cache(void) +{ + /* Disable data and instruction cache. */ + STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN); + + /* Reset data and instruction cache */ + STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST; +} +DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT); +#endif + /*****************************************************************************/ /* Console commands */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 1e2cc14bd7..7616ea0355 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1356,6 +1356,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR_PRFTEN (1 << 8) #define STM32_FLASH_ACR_ICEN (1 << 9) #define STM32_FLASH_ACR_DCEN (1 << 10) +#define STM32_FLASH_ACR_ICRST (1 << 11) +#define STM32_FLASH_ACR_DCRST (1 << 12) #define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) #define FLASH_KEYR_KEY1 0x45670123 |