diff options
| -rw-r--r-- | baseboard/dedede/baseboard.c | 64 | ||||
| -rw-r--r-- | baseboard/dedede/baseboard.h | 1 | ||||
| -rw-r--r-- | baseboard/dragonegg/baseboard.c | 13 | ||||
| -rw-r--r-- | baseboard/volteer/baseboard.c | 52 | ||||
| -rw-r--r-- | board/dragonegg/gpio.inc | 1 | ||||
| -rw-r--r-- | board/halvor/gpio.inc | 1 | ||||
| -rw-r--r-- | board/jslrvp_ite/board.c | 13 | ||||
| -rw-r--r-- | board/jslrvp_ite/gpio.inc | 8 | ||||
| -rw-r--r-- | board/malefor/gpio.inc | 1 | ||||
| -rw-r--r-- | board/tglrvpu_ite/board.c | 13 | ||||
| -rw-r--r-- | board/tglrvpu_ite/gpio.inc | 7 | ||||
| -rw-r--r-- | board/volteer/board.h | 1 | ||||
| -rw-r--r-- | board/volteer/gpio.inc | 1 | ||||
| -rw-r--r-- | power/icelake.c | 119 | ||||
| -rw-r--r-- | power/icelake.h | 39 |
15 files changed, 239 insertions, 95 deletions
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c index 9ff750785f..59c23f560a 100644 --- a/baseboard/dedede/baseboard.c +++ b/baseboard/dedede/baseboard.c @@ -13,6 +13,62 @@ #include "hooks.h" #include "intel_x86.h" +/******************************************************************************/ +/* + * PWROK signal configuration, see the PWROK Generation Flow Diagram in the + * Jasper Lake Platform Design Guide for the list of potential signals. + * + * Dedede boards use this PWROK sequence: + * GPIO_ALL_SYS_PWRGD - turns on VCCIN rail + * GPIO_EC_AP_VCCST_PWRGD_OD - asserts VCCST_PWRGD to AP, requires 2ms + * delay from VCCST stable to meet the tCPU00 platform sequencing + * timing + * GPIO_EC_AP_PCH_PWROK_OD - asserts PMC_PCH_PWROK to the AP. Note that + * PMC_PCH_PWROK is also gated by the IMVP9_VRRDY_OD output from + * the VCCIN voltage rail controller. + * GPIO_EC_AP_SYS_PWROK - asserts PMC_SYS_PWROK to the AP + * + * Both PMC_PCH_PWROK and PMC_SYS_PWROK signals must both be asserted before + * the Jasper Lake SoC deasserts PMC_RLTRST_N. The platform may deassert + * PMC_PCH_PWROK and PMC_SYS_PWROK in any order to optimize overall boot + * latency. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { + { + .gpio = GPIO_ALL_SYS_PWRGD, + }, + { + .gpio = GPIO_EC_AP_VCCST_PWRGD_OD, + .delay_ms = 2, + }, + { + .gpio = GPIO_EC_AP_PCH_PWROK_OD, + }, + { + .gpio = GPIO_EC_AP_SYS_PWROK, + }, +}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { + /* No delays needed during S0 exit */ + { + .gpio = GPIO_EC_AP_VCCST_PWRGD_OD, + }, + { + .gpio = GPIO_EC_AP_PCH_PWROK_OD, + }, + { + .gpio = GPIO_EC_AP_SYS_PWROK, + }, + /* Turn off the VCCIN rail last */ + { + .gpio = GPIO_ALL_SYS_PWRGD, + }, +}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); + + /* * Dedede does not use hibernate wake pins, but the super low power "Z-state" * instead in which the EC is powered off entirely. Power will be restored to @@ -61,14 +117,6 @@ __override int intel_x86_get_pg_ec_all_sys_pwrgd(void) gpio_get_level(GPIO_PG_VCCIO_EXT_OD); } -__override void board_jsl_all_sys_pwrgd(int value) -{ - /* - * ALL_SYS_PWRGD is an AND of both DRAM PGOOD and VCCST PGOOD. - */ - gpio_set_level(GPIO_ALL_SYS_PWRGD, value); -} - __override int power_signal_get_level(enum gpio_signal signal) { if (signal == GPIO_PG_EC_DSW_PWROK) diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index f4f2e0e9d3..a684002f65 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -88,7 +88,6 @@ #define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L #define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_AP_SYS_PWROK #define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L #define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL diff --git a/baseboard/dragonegg/baseboard.c b/baseboard/dragonegg/baseboard.c index aa2ee875b7..e737530570 100644 --- a/baseboard/dragonegg/baseboard.c +++ b/baseboard/dragonegg/baseboard.c @@ -21,6 +21,7 @@ #include "gpio.h" #include "hooks.h" #include "i2c.h" +#include "icelake.h" #include "keyboard_scan.h" #include "power.h" #include "timer.h" @@ -91,6 +92,18 @@ const struct charger_config_t chg_chips[] = { const unsigned int chg_cnt = ARRAY_SIZE(chg_chips); /******************************************************************************/ +/* PWROK signal configuration */ +/* + * On Dragonegg the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK + * signals are handled by the board. No EC control needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +/******************************************************************************/ /* Chipset callbacks/hooks */ /* Called on AP S5 -> S3 transition */ diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c index 144d26b57c..47d0a955ba 100644 --- a/baseboard/volteer/baseboard.c +++ b/baseboard/volteer/baseboard.c @@ -23,6 +23,7 @@ #include "gpio.h" #include "hooks.h" #include "i2c.h" +#include "icelake.h" #include "keyboard_scan.h" #include "pwm.h" #include "pwm_chip.h" @@ -176,6 +177,47 @@ const struct charger_config_t chg_chips[] = { const unsigned int chg_cnt = ARRAY_SIZE(chg_chips); +/******************************************************************************/ +/* + * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure + * 235) in the Tiger Lake Platform Design Guide for the list of potential + * signals. + * + * Volteer uses this power sequence: + * GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to + * the VCCST_PWRGD input to the AP so this signal must be delayed + * 5 ms to meet the tCPU00 timing requirement. + * GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed + * a total of 50 ms after ALL_SYS_PWRGD input is asserted. See + * b/144478941 for full discussion. + * + * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK + * signals. If your board adds these signals to the EC, copy this array + * to your board.c file and modify as needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { + { + .gpio = GPIO_EN_PPVAR_VCCIN, + .delay_ms = 5, + }, + { + .gpio = GPIO_EC_PCH_SYS_PWROK, + .delay_ms = 50 - 5, + }, +}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { + /* No delays needed during S0 exit */ + { + .gpio = GPIO_EC_PCH_SYS_PWROK, + }, + /* Turn off VCCIN last */ + { + .gpio = GPIO_EN_PPVAR_VCCIN, + }, +}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); /******************************************************************************/ /* PWM configuration */ @@ -636,16 +678,6 @@ void board_overcurrent_event(int port, int is_overcurrented) /* TODO: b/140561826 - check correct operation for Volteer */ } -/* - * Delay assertion of PCH_SYS_PWROK from assertion of the PG_EC_ALL_SYS_PWRGD - * input. This ensures PCH_SYS_PWROK is asserted only after all rails have - * stabilized. See b/144478941 for full discussion. - */ -__override void board_icl_tgl_all_sys_pwrgood(void) -{ - msleep(50); -} - static void baseboard_init(void) { /* Illuminate motherboard and daughter board LEDs equally to start. */ diff --git a/board/dragonegg/gpio.inc b/board/dragonegg/gpio.inc index 474bf49643..ac46ccbd6f 100644 --- a/board/dragonegg/gpio.inc +++ b/board/dragonegg/gpio.inc @@ -66,7 +66,6 @@ GPIO(PP5000_PG_OD, PIN(F, 0), GPIO_INPUT) /* SYS_PWROK generation is done by the Dialog power good IC */ UNIMPLEMENTED(PG_EC_ALL_SYS_PWRGD) -UNIMPLEMENTED(PCH_SYS_PWROK) /* USB and USBC Signals */ GPIO(USB_OC_ODL, PIN(J, 6), GPIO_ODR_HIGH) diff --git a/board/halvor/gpio.inc b/board/halvor/gpio.inc index 19da03aa61..6ebbcc93b8 100644 --- a/board/halvor/gpio.inc +++ b/board/halvor/gpio.inc @@ -53,6 +53,7 @@ GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_inte /* Power Sequencing Signals */ GPIO(EN_PP3300_A, PIN(A, 3), GPIO_OUT_LOW) GPIO(EN_PP5000_A, PIN(A, 4), GPIO_OUT_LOW) +GPIO(EN_PPVAR_VCCIN, PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */ /* The EC does not buffer this signal on Volteer. */ UNIMPLEMENTED(PCH_DSW_PWROK) diff --git a/board/jslrvp_ite/board.c b/board/jslrvp_ite/board.c index bb41fedcc9..5ea6f057b6 100644 --- a/board/jslrvp_ite/board.c +++ b/board/jslrvp_ite/board.c @@ -10,6 +10,7 @@ #include "driver/charger/isl923x.h" #include "extpower.h" #include "i2c.h" +#include "icelake.h" #include "intc.h" #include "lid_switch.h" #include "power.h" @@ -101,6 +102,18 @@ const struct charger_config_t chg_chips[] = { const unsigned int chg_cnt = ARRAY_SIZE(chg_chips); +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * On JSLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK + * signals are handled by the board. No EC control needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); + /* * Returns board information (board id[7:0] and Fab id[15:8]) on success * -1 on error. diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc index 3d46c1ddd3..66e0fe5595 100644 --- a/board/jslrvp_ite/gpio.inc +++ b/board/jslrvp_ite/gpio.inc @@ -68,15 +68,7 @@ GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) GPIO(EN_PP3300_A, PIN(C, 3), GPIO_OUT_LOW) GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) -/* - * SYS_PWROK driven directly to AP by Silego, EC not needed for generation. - * PCH_SYS_PWROK is routed to EC, but mark unimplemented to prevent common - * Ice Lake code from driving signal. - */ -UNIMPLEMENTED(PCH_SYS_PWROK) UNIMPLEMENTED(EN_VCCIO_EXT) -UNIMPLEMENTED(EC_AP_PCH_PWROK_OD) -UNIMPLEMENTED(EC_AP_VCCST_PWRGD_OD) /* Host communication GPIOs */ GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) diff --git a/board/malefor/gpio.inc b/board/malefor/gpio.inc index 6aa4712f98..67dc3553e1 100644 --- a/board/malefor/gpio.inc +++ b/board/malefor/gpio.inc @@ -53,6 +53,7 @@ GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_inte /* Power Sequencing Signals */ GPIO(EN_PP3300_A, PIN(A, 3), GPIO_OUT_LOW) GPIO(EN_PP5000_A, PIN(A, 4), GPIO_OUT_LOW) +GPIO(EN_PPVAR_VCCIN, PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */ /* The EC does not buffer this signal on Volteer. */ UNIMPLEMENTED(PCH_DSW_PWROK) diff --git a/board/tglrvpu_ite/board.c b/board/tglrvpu_ite/board.c index c46772aaaa..f62a90d177 100644 --- a/board/tglrvpu_ite/board.c +++ b/board/tglrvpu_ite/board.c @@ -10,6 +10,7 @@ #include "driver/charger/isl9241.h" #include "extpower.h" #include "i2c.h" +#include "icelake.h" #include "intc.h" #include "lid_switch.h" #include "power.h" @@ -119,6 +120,18 @@ const struct charger_config_t chg_chips[] = { const unsigned int chg_cnt = ARRAY_SIZE(chg_chips); +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * On TGLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK + * signals are handled by the board. No EC control needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); + /* * Returns board information (board id[7:0] and Fab id[15:8]) on success * -1 on error. diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc index e5ad8cd79b..9ce04cdc71 100644 --- a/board/tglrvpu_ite/gpio.inc +++ b/board/tglrvpu_ite/gpio.inc @@ -74,13 +74,6 @@ GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) GPIO(EN_PP3300_A, PIN(K, 2), GPIO_OUT_LOW) GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) -/* - * SYS_PWROK driven directly to AP by Silego, EC not needed for generation. - * PCH_SYS_PWROK is routed to EC, but mark unimplemented to prevent common - * Ice Lake code from driving signal. - */ -UNIMPLEMENTED(PCH_SYS_PWROK) - /* Host communication GPIOs */ GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) #ifndef CONFIG_HOSTCMD_ESPI diff --git a/board/volteer/board.h b/board/volteer/board.h index 8ebc01ede8..3c7bd930a9 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -72,7 +72,6 @@ #define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL #define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL #define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK #define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L #define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index 73634db510..ce1c1eae43 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -60,6 +60,7 @@ GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_inte /* Power Sequencing Signals */ GPIO(EN_PP3300_A, PIN(A, 3), GPIO_OUT_LOW) GPIO(EN_PP5000_A, PIN(A, 4), GPIO_OUT_LOW) +GPIO(EN_PPVAR_VCCIN, PIN(4, 3), GPIO_OUT_LOW) /* Enables VCCIN IMPV9 */ /* The EC does not buffer this signal on Volteer. */ UNIMPLEMENTED(PCH_DSW_PWROK) diff --git a/power/icelake.c b/power/icelake.c index fe48e22d24..a40395434c 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -83,11 +83,6 @@ __overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void) return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD); } -__overridable void board_jsl_all_sys_pwrgd(int value) -{ - -} - void chipset_force_shutdown(enum chipset_shutdown_reason reason) { int timeout_ms = 50; @@ -149,16 +144,6 @@ enum power_state chipset_force_g3(void) return POWER_G3; } -/* - * Ice Lake and Tiger Lake permit PCH_PWROK and SYS_PWROK signals coming - * up in any order. If the platform needs extra time for peripherals to come - * up, the board can override this function. - */ -__overridable void board_icl_tgl_all_sys_pwrgood(void) -{ - -} - static void enable_pp5000_rail(void) { if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL)) @@ -168,15 +153,6 @@ static void enable_pp5000_rail(void) } -#ifdef CONFIG_CHIPSET_JASPERLAKE -static void assert_ec_ap_vccst_pwrgd_pch_pwrok(void) -{ - GPIO_SET_LEVEL(GPIO_EC_AP_VCCST_PWRGD_OD, 1); - GPIO_SET_LEVEL(GPIO_EC_AP_PCH_PWROK_OD, 1); -} -DECLARE_DEFERRED(assert_ec_ap_vccst_pwrgd_pch_pwrok); -#endif /* CONFIG_CHIPSET_JASPERLAKE */ - static void dsw_pwrok_pass_thru(void) { int dswpwrok_in = intel_x86_get_pg_ec_dsw_pwrok(); @@ -207,33 +183,74 @@ static void dsw_pwrok_pass_thru(void) } } -enum power_state power_handle_state(enum power_state state) +/* + * Return 0 if PWROK signal is deasserted, non-zero if asserted + */ +static int pwrok_signal_get(const struct intel_x86_pwrok_signal *signal) +{ + int level = gpio_get_level(signal->gpio); + + if (signal->active_low) + level = !level; + + return level; +} + +/* + * Set the PWROK signal state + * + * ¶m level 0 deasserts the signal, other values assert the signal + */ +static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal, + int level) +{ + GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level); +} + +/* + * Pass through the state of the ALL_SYS_PWRGD input to all the PWROK outputs + * defined by the board. + */ +static void all_sys_pwrgd_pass_thru(void) { int all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd(); - int all_sys_pwrgd_out; + const struct intel_x86_pwrok_signal *pwrok_signal; + int signal_count; + int i; + + if (all_sys_pwrgd_in) { + pwrok_signal = pwrok_signal_assert_list; + signal_count = pwrok_signal_assert_count; + } else { + pwrok_signal = pwrok_signal_deassert_list; + signal_count = pwrok_signal_deassert_count; + } + + /* + * Loop through all PWROK signals defined by the board and set + * to match the current ALL_SYS_PWRGD input. + */ + for (i = 0; i < signal_count; i++, pwrok_signal++) { + if ((!all_sys_pwrgd_in && !pwrok_signal_get(pwrok_signal)) + || (all_sys_pwrgd_in && pwrok_signal_get(pwrok_signal))) + continue; + + if (pwrok_signal->delay_ms > 0) + msleep(pwrok_signal->delay_ms); + + pwrok_signal_set(pwrok_signal, all_sys_pwrgd_in); + } +} + +enum power_state power_handle_state(enum power_state state) +{ #ifdef CONFIG_CHIPSET_JASPERLAKE int timeout_ms = 10; #endif /* CONFIG_CHIPSET_JASPERLAKE */ dsw_pwrok_pass_thru(); -#ifdef CONFIG_CHIPSET_JASPERLAKE - /* - * Set ALL_SYS_PWRGD after receiving both PG_DRAM and PG_PP1050_ST. - * Assert VCCST power good and PCH_PWROK, when ALL_SYS_PWRGD is - * received with a 2ms delay minimum. - */ - if (all_sys_pwrgd_in && !gpio_get_level(GPIO_EC_AP_VCCST_PWRGD_OD)) { - board_jsl_all_sys_pwrgd(all_sys_pwrgd_in); - hook_call_deferred(&assert_ec_ap_vccst_pwrgd_pch_pwrok_data, - 2 * MSEC); - } else if (!all_sys_pwrgd_in && - gpio_get_level(GPIO_EC_AP_VCCST_PWRGD_OD)) { - GPIO_SET_LEVEL(GPIO_EC_AP_VCCST_PWRGD_OD, 0); - GPIO_SET_LEVEL(GPIO_EC_AP_PCH_PWROK_OD, 0); - board_jsl_all_sys_pwrgd(all_sys_pwrgd_in); - } -#endif /* CONFIG_CHIPSET_JASPERLAKE */ + all_sys_pwrgd_pass_thru(); common_intel_x86_handle_rsmrst(state); @@ -312,22 +329,6 @@ enum power_state power_handle_state(enum power_state state) break; #endif /* CONFIG_CHIPSET_JASPERLAKE */ - case POWER_S0: - /* - * Check value of PG_EC_ALL_SYS_PWRGD to see if PCH_SYS_PWROK - * needs to be changed. If it's low->high transition, call board - * specific handling if provided. - */ - all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd(); - all_sys_pwrgd_out = gpio_get_level(GPIO_PCH_SYS_PWROK); - - if (all_sys_pwrgd_in != all_sys_pwrgd_out) { - if (all_sys_pwrgd_in) - board_icl_tgl_all_sys_pwrgood(); - GPIO_SET_LEVEL(GPIO_PCH_SYS_PWROK, all_sys_pwrgd_in); - } - break; - default: break; } diff --git a/power/icelake.h b/power/icelake.h index c051a2516a..08c14718ec 100644 --- a/power/icelake.h +++ b/power/icelake.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_ICELAKE_H #define __CROS_EC_ICELAKE_H +#include "stdbool.h" + /* Input state flags. */ #define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) #define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) @@ -40,4 +42,41 @@ enum power_signal { POWER_SIGNAL_COUNT }; +struct intel_x86_pwrok_signal { + enum gpio_signal gpio; + bool active_low; + int delay_ms; +}; + +/* + * Ice Lake/Tiger Lake/Jasper Lake PWROK Generation + * + * The following signals are controlled based on the state of the ALL_SYS_PWRGD + * signal + * + * VCCIN enable (input to the VCCIN voltage rail controller) + * VCCST_PWRGD (input to the SoC) + * PCH_PWROK (input to the SoC) + * SYS_PWROK (input to the SoC) + * + * For any the above signals that are controlled by the EC, create an entry + * in the pwrok_signal_assert_list[] and pwrok_signal_deassert_list[] arrays. + * The typical order for asserting the signals is shown above, the deassert + * order is the reverse. + * + * ALL_SYS_PWRGD indicates when all the following are asserted. + * RSMRST_PWRGD & DPWROK + * S4 voltage rails good (DDR) + * VCCST voltage rail good + * S0 voltage rails good + * + * ALL_SYS_PWRGD can be implemented as a single GPIO if the platform power logic + * combines the above power good signals. Otherwise your board can override + * intel_x86_get_pg_ec_all_sys_pwrgd() to check multiple power good signals. + */ +extern const struct intel_x86_pwrok_signal pwrok_signal_assert_list[]; +extern const int pwrok_signal_assert_count; +extern const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[]; +extern const int pwrok_signal_deassert_count; + #endif /* __CROS_EC_ICELAKE_H */ |