diff options
| -rw-r--r-- | core/riscv-rv32i/build.mk | 6 | ||||
| -rw-r--r-- | core/riscv-rv32i/math.c | 8 |
2 files changed, 3 insertions, 11 deletions
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index df4e5e7ca9..34f059e70c 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -15,9 +15,9 @@ _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) # CPU specific compilation flags CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os # RISC-V does not trap division by zero, enable the sanitizer to check those. -# TODO(b:173969773): It might be better to add a new compiler flag for this -# (e.g. -mcheck-zero-division that is only only available on MIPS currently). -CFLAGS_CPU+=-fsanitize=integer-divide-by-zero +# With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the +# exact issue, but the added code is as small as it gets. +CFLAGS_CPU+=-fsanitize=integer-divide-by-zero -fsanitize-undefined-trap-on-error LDFLAGS_EXTRA+=-mrelax LDFLAGS_EXTRA+=-static-libgcc -lgcc diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c index 2a637c8bcc..591a67eb8f 100644 --- a/core/riscv-rv32i/math.c +++ b/core/riscv-rv32i/math.c @@ -4,8 +4,6 @@ */ #include "common.h" -#include "cpu.h" -#include "panic.h" #ifdef CONFIG_FPU /* Single precision floating point square root. */ @@ -19,9 +17,3 @@ float sqrtf(float x) return x; } #endif - -void __ubsan_handle_divrem_overflow(void *data, - void *lhs, void *rhs) -{ - exception_panic(PANIC_SW_DIV_ZERO, 0); -} |