diff options
| -rw-r--r-- | zephyr/boards/arm/npcx_evb/Kconfig.board | 6 | ||||
| -rw-r--r-- | zephyr/boards/arm/npcx_evb/Kconfig.defconfig | 1 | ||||
| -rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx9_evb.dts | 21 | ||||
| -rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig | 33 | ||||
| -rw-r--r-- | zephyr/projects/npcx_evb/npcx9/CMakeLists.txt | 11 | ||||
| -rw-r--r-- | zephyr/projects/npcx_evb/npcx9/gpio.dts | 10 | ||||
| -rw-r--r-- | zephyr/projects/npcx_evb/npcx9/include/gpio_map.h | 32 | ||||
| -rw-r--r-- | zephyr/projects/npcx_evb/npcx9/prj.conf | 26 | ||||
| -rw-r--r-- | zephyr/projects/npcx_evb/npcx9/zmake.yaml | 11 |
9 files changed, 151 insertions, 0 deletions
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board index d7cdd067da..0ac4a80833 100644 --- a/zephyr/boards/arm/npcx_evb/Kconfig.board +++ b/zephyr/boards/arm/npcx_evb/Kconfig.board @@ -10,3 +10,9 @@ config BOARD_NPCX7_EVB depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC # Allow generating initial 0 line coverage. select HAS_COVERAGE_SUPPORT + +config BOARD_NPCX9_EVB + bool "NPCX9 Evaluation Board" + depends on SOC_NPCX9M3F || SOC_NPCX9M6F + # Allow generating initial 0 line coverage. + select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig index 81268a4636..c0c874ad26 100644 --- a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig +++ b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig @@ -4,3 +4,4 @@ config BOARD default "npcx7_evb" if BOARD_NPCX7_EVB + default "npcx9_evb" if BOARD_NPCX9_EVB diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts new file mode 100644 index 0000000000..4ab68cdde1 --- /dev/null +++ b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts @@ -0,0 +1,21 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/dts-v1/; + +#include <cros/nuvoton/npcx9.dtsi> + +/* + * #include <nuvoton/npcx9m3f.dtsi> + * #include <nuvoton/npcx9m6f.dtsi> + */ +#include <nuvoton/npcx9m6f.dtsi> +#include "npcx_evb.dtsi" + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; +}; diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig new file mode 100644 index 0000000000..cfb3a263e8 --- /dev/null +++ b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig @@ -0,0 +1,33 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Kernel Configuration +CONFIG_SOC_SERIES_NPCX9=y +# NPCX9 soc list +# CONFIG_SOC_NPCX9M3F +# CONFIG_SOC_NPCX9M6F +CONFIG_SOC_NPCX9M6F=y + +# Platform Configuration +CONFIG_BOARD_NPCX9_EVB=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Pinmux Driver +CONFIG_PINMUX=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# WATCHDOG configuration +CONFIG_WATCHDOG=y diff --git a/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt new file mode 100644 index 0000000000..8d605a001c --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) +set(BOARD_ROOT "${CMAKE_CURRENT_LIST_DIR}/..") + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(npcx9) + +zephyr_include_directories(include) diff --git a/zephyr/projects/npcx_evb/npcx9/gpio.dts b/zephyr/projects/npcx_evb/npcx9/gpio.dts new file mode 100644 index 0000000000..5de0a5e422 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/gpio.dts @@ -0,0 +1,10 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-gpios { + compatible = "named-gpios"; + }; +}; diff --git a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h new file mode 100644 index 0000000000..61258d1184 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h @@ -0,0 +1,32 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_GPIO_MAP_H +#define __ZEPHYR_GPIO_MAP_H + +#include <devicetree.h> +#include <gpio_signal.h> + +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_WP_L GPIO_UNIMPLEMENTED + +/* + * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items. + * + * Each GPIO_INT requires three parameters: + * gpio_signal - The enum gpio_signal for the interrupt gpio + * interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH) + * handler - The platform/ec interrupt handler. + * + * Ensure that this files includes all necessary headers to declare all + * referenced handler functions. + * + * For example, one could use the follow definition: + * #define EC_CROS_GPIO_INTERRUPTS \ + * GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print) + */ +#define EC_CROS_GPIO_INTERRUPTS + +#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf new file mode 100644 index 0000000000..04917a78d4 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/prj.conf @@ -0,0 +1,26 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_SHIMMED_TASKS=y + +CONFIG_CROS_KB_RAW_NPCX=n + +CONFIG_AP=n +CONFIG_PLATFORM_EC_ADC=n +CONFIG_PLATFORM_EC_I2C=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_VBOOT=n +CONFIG_PLATFORM_EC_VSTORE=n + +# Workaround npcx9 A1 chip's bug for download_from_flash API in th booter. +# This can be removed when A2 chip is available. +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y + +# Zephyr feature +CONFIG_ASSERT=y +CONFIG_SHELL_MINIMAL=n +CONFIG_LOG=y diff --git a/zephyr/projects/npcx_evb/npcx9/zmake.yaml b/zephyr/projects/npcx_evb/npcx9/zmake.yaml new file mode 100644 index 0000000000..5aaa630542 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/zmake.yaml @@ -0,0 +1,11 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +board: npcx9_evb +dts-overlays: + - gpio.dts +supported-zephyr-versions: + - v2.6 +toolchain: coreboot-sdk +output-type: npcx |