diff options
| -rw-r--r-- | zephyr/app/ec/Kconfig | 6 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/Kconfig.npcx7 | 128 |
2 files changed, 134 insertions, 0 deletions
diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig index c5ca463457..7507f49e83 100644 --- a/zephyr/app/ec/Kconfig +++ b/zephyr/app/ec/Kconfig @@ -18,6 +18,12 @@ if CROS_EC rsource "soc/Kconfig" +if SOC_SERIES_NPCX7 + +rsource "chip/Kconfig.npcx7" + +endif # SOC_SERIES_NPCX7 + config LTO bool "Link Time Optimization (LTO)" default y if !SOC_POSIX diff --git a/zephyr/app/ec/chip/Kconfig.npcx7 b/zephyr/app/ec/chip/Kconfig.npcx7 new file mode 100644 index 0000000000..31bb2ec635 --- /dev/null +++ b/zephyr/app/ec/chip/Kconfig.npcx7 @@ -0,0 +1,128 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# +# This file defines the correct defaults when using the NPCX7 series chipset +# + +if SOC_NPCX7M6FC + +# +# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM +# + +# Code RAM base for NPCX796FC +config CROS_EC_PROGRAM_MEMORY_BASE + default 0x10090000 + +config CROS_EC_RAM_BASE + default 0x200c0000 + +config CROS_EC_DATA_RAM_SIZE + default 0x00010000 + +config CROS_EC_RAM_SIZE + default 0x0000f800 + +config FLASH_SIZE + default 512 + +config CROS_EC_RO_MEM_OFF + default 0x0 + +# Image size limited by code RAM size (192 KiB) +config CROS_EC_RO_SIZE + default 0x30000 + +# RW firmware in program memory - Identical to RO, only one image loaded at a +# time. +config CROS_EC_RW_MEM_OFF + default 0x0 + +config CROS_EC_RW_SIZE + default 0x30000 + +endif # SOC_NPCX7M6FC + +if SOC_NPCX7M7FC + +# +# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM +# + +# Code RAM base for NPCX797FC +config CROS_EC_PROGRAM_MEMORY_BASE + default 0x10070000 + +config CROS_EC_RAM_BASE + default 0x200c0000 + +config CROS_EC_DATA_RAM_SIZE + default 0x00010000 + +config CROS_EC_RAM_SIZE + default 0x0000f800 + +config FLASH_SIZE + default 512 + +config CROS_EC_RO_MEM_OFF + default 0x0 + +# Image size limited by 1/2 Flash size (256 KiB) +config CROS_EC_RO_SIZE + default 0x40000 + +# RW firmware in program memory - Identical to RO, only one image loaded at a +# time. +config CROS_EC_RW_MEM_OFF + default 0x0 + +config CROS_EC_RW_SIZE + default 0x40000 + +endif # SOC_NPCX7M7FC + +# +# Default config values shared by all NPCX7 devices +# + +# ADC +# The resolution and oversamplig values are fixed by the NPCX ADC driver +config PLATFORM_EC_ADC_RESOLUTION + default 10 + +config PLATFORM_EC_ADC_OVERSAMPLING + default 0 + +# PLL configuration +config CLOCK_NPCX_OSC_CYCLES_PER_SEC + default 90000000 + +config CLOCK_NPCX_APB1_PRESCALER + default 6 + +config CLOCK_NPCX_APB2_PRESCALER + default 6 + +config CLOCK_NPCX_APB3_PRESCALER + default 6 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 15000000 + +if WATCHDOG + +# Set the delay time for printing panic data. +# 1 cycle is about 32ms. 500ms is about 16 cycles. +config WDT_NPCX_DELAY_CYCLES + default 16 + +endif # WATCHDOG + +# The maximum supported time the NPCX can spend in deep-sleep with instant +# wake is 200 ms, so the hook tick interval is set to match. +config CROS_EC_HOOK_TICK_INTERVAL + default 200000 + |