diff options
| -rw-r--r-- | chip/mec1322/registers.h | 3 | ||||
| -rw-r--r-- | chip/mec1322/system.c | 24 |
2 files changed, 25 insertions, 2 deletions
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index b7a8612f83..d31b66584b 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -41,6 +41,9 @@ #define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44) #define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) +/* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ +#define MEC1322_PWR_RST_STS_VCC1 (1 << 6) +#define MEC1322_PWR_RST_STS_VBAT (1 << 5) /* EC Subsystem */ #define MEC1322_EC_BASE 0x4000fc00 diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c index b779bac26c..04afff3c15 100644 --- a/chip/mec1322/system.c +++ b/chip/mec1322/system.c @@ -43,13 +43,33 @@ static void check_reset_cause(void) { uint32_t status = MEC1322_VBAT_STS; uint32_t flags = 0; + uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & + (MEC1322_PWR_RST_STS_VCC1 | + MEC1322_PWR_RST_STS_VBAT); /* Clear the reset causes now that we've read them */ MEC1322_VBAT_STS |= status; + MEC1322_PCR_CHIP_PWR_RST |= rst_sts; - if (status & (1 << 7) || check_vcc1_por()) + /* + * BIT[6:5] determine VCC1 reset and VBAT reset status. + * when Poweron watchdog is reset and both VCC1 and VBAT + * are set + */ + if ((rst_sts == (MEC1322_PWR_RST_STS_VCC1 | + MEC1322_PWR_RST_STS_VBAT)) + && check_vcc1_por()) flags |= RESET_FLAG_POWER_ON; + /* + * Check for only BIT 6 to determine VCC1_RST# and no + * change on VBAT status indicates this is VCC1_RST# + */ + if ((rst_sts & MEC1322_PWR_RST_STS_VCC1) && + !(rst_sts & MEC1322_PWR_RST_STS_VBAT)) + flags |= RESET_FLAG_RESET_PIN; + + flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; @@ -94,7 +114,7 @@ void system_pre_init(void) MEC1322_PCR_PWR_RST_CTL &= ~(1 << 0); if (MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) & - RESET_FLAG_POWER_ON) + (RESET_FLAG_POWER_ON|RESET_FLAG_RESET_PIN)) MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = 0; check_reset_cause(); |