diff options
| -rw-r--r-- | chip/ish/reset_prep_wr.c | 18 | ||||
| -rw-r--r-- | chip/ish/system.c | 6 |
2 files changed, 15 insertions, 9 deletions
diff --git a/chip/ish/reset_prep_wr.c b/chip/ish/reset_prep_wr.c index 6d8702bee9..c6524b9f49 100644 --- a/chip/ish/reset_prep_wr.c +++ b/chip/ish/reset_prep_wr.c @@ -6,10 +6,11 @@ /* Power managerment module for ISH */ #include "common.h" #include "console.h" -#include "registers.h" +#include "hooks.h" #include "interrupts.h" +#include "registers.h" +#include "system.h" #include "task.h" -#include "hooks.h" #ifdef PM_DEBUG #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) @@ -21,14 +22,13 @@ #define CPRINTF(format, args...) #endif +/* + * IRQ fires when we receive a RESET_PREP message from AP. This happens at S0 + * entry. + */ static void reset_prep_wr_isr(void) { - /* - * ISH HW looks at the rising edge of this bit to - * trigger a MIA reset. Now in S0, reset MIA. - */ - ISH_RST_REG = 0; - ISH_RST_REG = 1; + system_reset(SYSTEM_RESET_HARD); } DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_wr_isr); @@ -37,7 +37,7 @@ void reset_prep_init(void) /* Clear reset bit */ ISH_RST_REG = 0; - /* clear reset history register in CCU */ + /* Clear reset history register from previous boot. */ CCU_RST_HST = CCU_RST_HST; /* Unmask reset prep avail interrupt mask */ PMU_RST_PREP = 0; diff --git a/chip/ish/system.c b/chip/ish/system.c index f532e8bf85..6c8550b0b4 100644 --- a/chip/ish/system.c +++ b/chip/ish/system.c @@ -46,6 +46,12 @@ uint32_t chip_read_reset_flags(void) void _system_reset(int flags, int wake_from_hibernate) { + /* + * ISH HW looks at the rising edge of this bit to + * trigger a MIA reset. + */ + ISH_RST_REG = 0; + ISH_RST_REG = 1; } void system_reset(int flags) |