diff options
| -rw-r--r-- | zephyr/drivers/cros_system/cros_system_npcx.c | 28 | ||||
| -rw-r--r-- | zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml | 17 | ||||
| -rw-r--r-- | zephyr/include/cros/nuvoton/npcx.dtsi | 8 |
3 files changed, 53 insertions, 0 deletions
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index b63743a13d..71eb1c4b9f 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -134,3 +134,31 @@ static const struct cros_system_driver_api cros_system_driver_npcx_api = { DEVICE_DEFINE(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init, NULL, &cros_system_npcx_dev_data, &cros_system_dev_cfg, PRE_KERNEL_1, 30, &cros_system_driver_npcx_api); + +#define HAL_DBG_REG_BASE_ADDR \ + ((struct dbg_reg *)DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_dbg))) + +#define DBG_NODE DT_NODELABEL(dbg) +#define DBG_PINCTRL_PH DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0) +#define DBG_ALT_FILED(f) DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f) + +static int jtag_init(const struct device *dev) +{ + ARG_UNUSED(dev); + struct dbg_reg *const dbg_reg_base = HAL_DBG_REG_BASE_ADDR; + const struct npcx_alt jtag_alts[] = { + { + .group = DBG_ALT_FILED(group), + .bit = DBG_ALT_FILED(bit), + .inverted = DBG_ALT_FILED(inv) + } + }; + + dbg_reg_base->DBGCTRL = 0x04; + dbg_reg_base->DBGFRZEN3 &= ~BIT(NPCX_DBGFRZEN3_GLBL_FRZ_DIS); + if (DT_NODE_HAS_STATUS(DT_NODELABEL(dbg), okay)) + npcx_pinctrl_mux_configure(jtag_alts, 1, 1); + + return 0; +} +SYS_INIT(jtag_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT + 1); diff --git a/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml new file mode 100644 index 0000000000..109fa11d50 --- /dev/null +++ b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Google Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: Nuvoton, NPCX Debug Interface + +compatible: "nuvoton,npcx-cros-dbg" + +include: base.yaml + +properties: + reg: + required: true + + pinctrl-0: + type: phandles + required: true + description: configurations of pinmux controllers diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi index 89fb9484d9..2d87e91dca 100644 --- a/zephyr/include/cros/nuvoton/npcx.dtsi +++ b/zephyr/include/cros/nuvoton/npcx.dtsi @@ -69,6 +69,14 @@ reg-names = "memory", "status"; label = "BBRAM"; }; + + dbg: dbg@400c3074 { + compatible = "nuvoton,npcx-cros-dbg"; + reg = <0x400c3074 0x0C>; + pinctrl-0 = <&alt5_njen0_en>; + label = "DBG"; + status = "disabled"; + }; }; }; |