diff options
| -rw-r--r-- | chip/npcx/registers-npcx5.h | 8 | ||||
| -rw-r--r-- | chip/npcx/registers-npcx7.h | 8 | ||||
| -rw-r--r-- | chip/npcx/registers-npcx9.h | 8 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 8 | ||||
| -rw-r--r-- | zephyr/shim/chip/npcx/system_external_storage.c | 8 |
5 files changed, 32 insertions, 8 deletions
diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h index 3d241a1984..c441c1c926 100644 --- a/chip/npcx/registers-npcx5.h +++ b/chip/npcx/registers-npcx5.h @@ -87,6 +87,14 @@ #define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ + +/* Miscellaneous Device Control (MDC) registers */ +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) + +/* MDC register fields */ +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 + #define NPCX_ITIM32_BASE_ADDR 0x400BC000 #define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) #define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h index cbd9be30dc..535abfbf0f 100644 --- a/chip/npcx/registers-npcx7.h +++ b/chip/npcx/registers-npcx7.h @@ -104,6 +104,14 @@ #define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ + +/* Miscellaneous Device Control (MDC) registers */ +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) + +/* MDC register fields */ +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 + #define NPCX_ITIM32_BASE_ADDR 0x400BC000 #define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) #define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h index 296f1af25c..a013a8b645 100644 --- a/chip/npcx/registers-npcx9.h +++ b/chip/npcx/registers-npcx9.h @@ -90,6 +90,14 @@ #define LCT_WUI_MASK MASK_PIN7 /* Modules Map */ + +/* Miscellaneous Device Control (MDC) registers */ +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x005) + +/* MDC register fields */ +#define NPCX_FWCTRL_RO_REGION 1 +#define NPCX_FWCTRL_FW_SLOT 2 + #define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl) * 0x2000L)) #define NPCX_LCT_BASE_ADDR 0x400D7000 #define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 374e9d58ba..f0c241e7f9 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -175,14 +175,6 @@ #define NPCX_IRQ_COUNT 64 /******************************************************************************/ -/* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) - -/* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 - -/******************************************************************************/ /* High Frequency Clock Generator (HFCG) registers */ #define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) #define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index b53db04e18..bce82b8841 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -12,9 +12,17 @@ /* TODO (b:179900857) Make this implementation not npcx specific. */ #define NPCX_MDC_BASE_ADDR 0x4000C000 +#ifdef CONFIG_SOC_SERIES_NPCX7 #define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) #define NPCX_FWCTRL_RO_REGION 0 #define NPCX_FWCTRL_FW_SLOT 1 +#elif defined(CONFIG_SOC_SERIES_NPCX9) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x005) +#define NPCX_FWCTRL_RO_REGION 1 +#define NPCX_FWCTRL_FW_SLOT 2 +#else +#error "Unsupported NPCX SoC series." +#endif void system_jump_to_booter(void) { |