diff options
| -rw-r--r-- | board/samus/board.h | 3 | ||||
| -rw-r--r-- | chip/lm4/lpc.c | 18 | ||||
| -rw-r--r-- | chip/lm4/registers.h | 2 | ||||
| -rw-r--r-- | chip/mec1322/lpc.c | 10 | ||||
| -rw-r--r-- | chip/npcx/lpc.c | 10 | ||||
| -rw-r--r-- | common/acpi.c | 51 | ||||
| -rw-r--r-- | common/als.c | 9 | ||||
| -rw-r--r-- | common/charge_state_v2.c | 18 | ||||
| -rw-r--r-- | common/fan.c | 10 | ||||
| -rw-r--r-- | common/host_command.c | 12 | ||||
| -rw-r--r-- | include/ec_commands.h | 266 | ||||
| -rw-r--r-- | include/host_command.h | 14 | ||||
| -rw-r--r-- | include/lpc.h | 10 |
13 files changed, 304 insertions, 129 deletions
diff --git a/board/samus/board.h b/board/samus/board.h index c6a6b64ec4..dd5e9265a3 100644 --- a/board/samus/board.h +++ b/board/samus/board.h @@ -77,6 +77,9 @@ (EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER) /* Do we want EC_WIRELESS_SWITCH_WWAN as well? */ +#undef DEFERRABLE_MAX_COUNT +#define DEFERRABLE_MAX_COUNT 9 + #ifndef __ASSEMBLER__ /* I2C ports */ diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index 0f3e9b8b1c..149145f3c0 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -432,6 +432,24 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type) return event_mask[type]; } +void lpc_set_acpi_status_mask(uint8_t mask) +{ + uint32_t set_mask = 0; + if (mask & EC_LPC_STATUS_BURST_MODE) + set_mask |= LM4_LPC_ST_BURST; + + LM4_LPC_ST(LPC_CH_ACPI) |= set_mask; +} + +void lpc_clear_acpi_status_mask(uint8_t mask) +{ + uint32_t clear_mask = 0; + if (mask & EC_LPC_STATUS_BURST_MODE) + clear_mask |= LM4_LPC_ST_BURST; + + LM4_LPC_ST(LPC_CH_ACPI) &= ~clear_mask; +} + int lpc_get_pltrst_asserted(void) { return (LM4_LPC_LPCSTS & (1<<10)) ? 1 : 0; diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index f6e503b208..15c91d1ca3 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -118,7 +118,7 @@ static inline int lm4_lpc_addr(int ch, int offset) #define LM4_LPC_ST_TOH (1 << 0) /* TO Host bit */ #define LM4_LPC_ST_FRMH (1 << 1) /* FRoM Host bit */ #define LM4_LPC_ST_CMD (1 << 3) /* Last from-host byte was command */ -#define LM4_LPC_ST_PRESENT (1 << 8) +#define LM4_LPC_ST_BURST (1 << 8) #define LM4_LPC_ST_SCI (1 << 9) #define LM4_LPC_ST_SMI (1 << 10) #define LM4_LPC_ST_BUSY (1 << 12) diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 07e75f2a09..cd49e4d357 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -449,6 +449,16 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type) return event_mask[type]; } +void lpc_set_acpi_status_mask(uint8_t mask) +{ + MEC1322_ACPI_EC_STATUS(0) |= mask; +} + +void lpc_clear_acpi_status_mask(uint8_t mask) +{ + MEC1322_ACPI_EC_STATUS(0) &= ~mask; +} + int lpc_get_pltrst_asserted(void) { return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0; diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 1622905299..79e0675ede 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -348,6 +348,16 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type) return event_mask[type]; } +void lpc_set_acpi_status_mask(uint8_t mask) +{ + /* TODO (crbug.com/p/38224): Implement */ +} + +void lpc_clear_acpi_status_mask(uint8_t mask) +{ + /* TODO (crbug.com/p/38224): Implement */ +} + int lpc_get_pltrst_asserted(void) { /* Read PLTRST status*/ diff --git a/common/acpi.c b/common/acpi.c index 88c0a8351e..425f7e2337 100644 --- a/common/acpi.c +++ b/common/acpi.c @@ -7,9 +7,12 @@ #include "common.h" #include "console.h" #include "dptf.h" +#include "hooks.h" +#include "host_command.h" #include "lpc.h" #include "ec_commands.h" #include "pwm.h" +#include "timer.h" /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) @@ -26,7 +29,20 @@ static int dptf_temp_sensor_id; /* last sensor ID written */ static int dptf_temp_threshold; /* last threshold written */ #endif -/* This handles AP writes to the EC via the ACPI I/O port. There are only a few +/* + * Deferred function to ensure that ACPI burst mode doesn't remain enabled + * indefinitely. + */ +static void acpi_unlock_memmap_deferred(void) +{ + lpc_clear_acpi_status_mask(EC_LPC_STATUS_BURST_MODE); + host_unlock_memmap(); + CPUTS("ACPI force unlock mutex, missed burst disable?"); +} +DECLARE_DEFERRED(acpi_unlock_memmap_deferred); + +/* + * This handles AP writes to the EC via the ACPI I/O port. There are only a few * ACPI commands (EC_CMD_ACPI_*), but they are all handled here. */ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) @@ -87,7 +103,15 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) break; #endif default: - CPRINTS("ACPI read 0x%02x (ignored)", acpi_addr); + if (acpi_addr >= EC_ACPI_MEM_MAPPED_BEGIN && + acpi_addr < + EC_ACPI_MEM_MAPPED_BEGIN + EC_ACPI_MEM_MAPPED_SIZE) + result = *((uint8_t *)(lpc_get_memmap_range() + + acpi_addr - + EC_ACPI_MEM_MAPPED_BEGIN)); + else + CPRINTS("ACPI read 0x%02x (ignored)", + acpi_addr); break; } @@ -149,16 +173,31 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) acpi_addr, data); break; } - -/* At the moment, ACPI implies LPC. */ -#ifdef CONFIG_LPC } else if (acpi_cmd == EC_CMD_ACPI_QUERY_EVENT && !acpi_data_count) { /* Clear and return the lowest host event */ int evt_index = lpc_query_host_event_state(); CPRINTS("ACPI query = %d", evt_index); *resultptr = evt_index; retval = 1; -#endif + } else if (acpi_cmd == EC_CMD_ACPI_BURST_ENABLE && !acpi_data_count) { + /* Enter burst mode */ + host_lock_memmap(); + lpc_set_acpi_status_mask(EC_LPC_STATUS_BURST_MODE); + + /* + * Unlock from deferred function in case burst mode is enabled + * for an extremely long time (ex. kernel bug / crash). + */ + hook_call_deferred(acpi_unlock_memmap_deferred, 1*SECOND); + + /* ACPI 5.0-12.3.3: Burst ACK */ + *resultptr = 0x90; + retval = 1; + } else if (acpi_cmd == EC_CMD_ACPI_BURST_DISABLE && !acpi_data_count) { + /* Leave burst mode */ + hook_call_deferred(acpi_unlock_memmap_deferred, -1); + lpc_clear_acpi_status_mask(EC_LPC_STATUS_BURST_MODE); + host_unlock_memmap(); } return retval; diff --git a/common/als.c b/common/als.c index e67eb03777..0ae06566aa 100644 --- a/common/als.c +++ b/common/als.c @@ -25,10 +25,15 @@ void als_task(void) { int i, val; uint16_t *mapped = (uint16_t *)host_get_memmap(EC_MEMMAP_ALS); + uint16_t als_data; while (1) { - for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++) - mapped[i] = als_read(i, &val) == EC_SUCCESS ? val : 0; + for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++) { + als_data = als_read(i, &val) == EC_SUCCESS ? val : 0; + host_lock_memmap(); + mapped[i] = als_data; + host_unlock_memmap(); + } task_wait_event(SECOND); } diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c index 5eb37e83a0..7b20c52eef 100644 --- a/common/charge_state_v2.c +++ b/common/charge_state_v2.c @@ -112,6 +112,12 @@ static int update_static_battery_info(void) */ int rv; + /* + * We're updating multi-byte memmap vars, don't allow ACPI to do + * reads while we're updating. + */ + host_lock_memmap(); + /* Smart battery serial number is 16 bits */ batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL); memset(batt_str, 0, EC_MEMMAP_TEXT_MAX); @@ -155,6 +161,9 @@ static int update_static_battery_info(void) *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC) = 0; *host_get_memmap(EC_MEMMAP_BATT_FLAG) = 0; + /* No more multi-byte memmap writes. */ + host_unlock_memmap(); + if (rv) problem(PR_STATIC_UPDATE, 0); else @@ -199,6 +208,12 @@ static void update_dynamic_battery_info(void) batt_present = 0; } + /* + * We're updating multi-byte memmap vars, don't allow ACPI to do + * reads while we're updating. + */ + host_lock_memmap(); + if (!(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE)) *memmap_volt = curr.batt.voltage; @@ -225,6 +240,9 @@ static void update_dynamic_battery_info(void) send_batt_info_event++; } + /* No more multi-byte memmap writes. */ + host_unlock_memmap(); + if (curr.batt.is_present == BP_YES && !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) && curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL) diff --git a/common/fan.c b/common/fan.c index 9196ddf36b..6cb64e777a 100644 --- a/common/fan.c +++ b/common/fan.c @@ -471,17 +471,23 @@ DECLARE_HOOK(HOOK_INIT, pwm_fan_init, HOOK_PRIO_DEFAULT); static void pwm_fan_second(void) { uint16_t *mapped = (uint16_t *)host_get_memmap(EC_MEMMAP_FAN); + uint16_t rpm; int stalled = 0; int fan; for (fan = 0; fan < CONFIG_FANS; fan++) { if (fan_is_stalled(fans[fan].ch)) { - mapped[fan] = EC_FAN_SPEED_STALLED; + rpm = EC_FAN_SPEED_STALLED; stalled = 1; cprints(CC_PWM, "Fan %d stalled!", fan); } else { - mapped[fan] = fan_get_rpm_actual(fans[fan].ch); + rpm = fan_get_rpm_actual(fans[fan].ch); } + + /* Lock ACPI read access to memmap during multi-byte write */ + host_lock_memmap(); + mapped[fan] = rpm; + host_unlock_memmap(); } /* diff --git a/common/host_command.c b/common/host_command.c index 51d1a9cf97..0a6226b59e 100644 --- a/common/host_command.c +++ b/common/host_command.c @@ -81,6 +81,18 @@ uint8_t *host_get_memmap(int offset) #endif } +static struct mutex memmap_write_mutex; + +void host_lock_memmap() +{ + mutex_lock(&memmap_write_mutex); +} + +void host_unlock_memmap() +{ + mutex_unlock(&memmap_write_mutex); +} + int host_get_vboot_mode(void) { return g_vboot_mode; diff --git a/include/ec_commands.h b/include/ec_commands.h index fa1da7f0cd..7da50715d6 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -92,8 +92,14 @@ /* Unused 0x91 */ #define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometer data 0x92 - 0x9f */ #define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ -/* Unused 0xa6 - 0xfe (remember, 0xff is NOT part of the memmap region) */ +/* Unused 0xa6 - 0xdf */ +/* + * ACPI is unable to access memory mapped data at or above this offset due to + * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe + * which might be needed by ACPI. + */ +#define EC_MEMMAP_NO_ACPI 0xe0 /* Define the format of the accelerometer mapped memory status byte. */ #define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f @@ -167,6 +173,146 @@ #define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ #define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ +/*****************************************************************************/ +/* + * ACPI commands + * + * These are valid ONLY on the ACPI command/data port. + */ + +/* + * ACPI Read Embedded Controller + * + * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). + * + * Use the following sequence: + * + * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write address to EC_LPC_ADDR_ACPI_DATA + * - Wait for EC_LPC_CMDR_DATA bit to set + * - Read value from EC_LPC_ADDR_ACPI_DATA + */ +#define EC_CMD_ACPI_READ 0x80 + +/* + * ACPI Write Embedded Controller + * + * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). + * + * Use the following sequence: + * + * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write address to EC_LPC_ADDR_ACPI_DATA + * - Wait for EC_LPC_CMDR_PENDING bit to clear + * - Write value to EC_LPC_ADDR_ACPI_DATA + */ +#define EC_CMD_ACPI_WRITE 0x81 + +/* + * ACPI Burst Enable Embedded Controller + * + * This enables burst mode on the EC to allow the host to issue several + * commands back-to-back. While in this mode, writes to mapped multi-byte + * data are locked out to ensure data consistency. + */ +#define EC_CMD_ACPI_BURST_ENABLE 0x82 + +/* + * ACPI Burst Disable Embedded Controller + * + * This disables burst mode on the EC and stops preventing EC writes to mapped + * multi-byte data. + */ +#define EC_CMD_ACPI_BURST_DISABLE 0x83 + +/* + * ACPI Query Embedded Controller + * + * This clears the lowest-order bit in the currently pending host events, and + * sets the result code to the 1-based index of the bit (event 0x00000001 = 1, + * event 0x80000000 = 32), or 0 if no event was pending. + */ +#define EC_CMD_ACPI_QUERY_EVENT 0x84 + +/* Valid addresses in ACPI memory space, for read/write commands */ + +/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ +#define EC_ACPI_MEM_VERSION 0x00 +/* + * Test location; writing value here updates test compliment byte to (0xff - + * value). + */ +#define EC_ACPI_MEM_TEST 0x01 +/* Test compliment; writes here are ignored. */ +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 + +/* Keyboard backlight brightness percent (0 - 100) */ +#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 +/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ +#define EC_ACPI_MEM_FAN_DUTY 0x04 + +/* + * DPTF temp thresholds. Any of the EC's temp sensors can have up to two + * independent thresholds attached to them. The current value of the ID + * register determines which sensor is affected by the THRESHOLD and COMMIT + * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme + * as the memory-mapped sensors. The COMMIT register applies those settings. + * + * The spec does not mandate any way to read back the threshold settings + * themselves, but when a threshold is crossed the AP needs a way to determine + * which sensor(s) are responsible. Each reading of the ID register clears and + * returns one sensor ID that has crossed one of its threshold (in either + * direction) since the last read. A value of 0xFF means "no new thresholds + * have tripped". Setting or enabling the thresholds for a sensor will clear + * the unread event count for that sensor. + */ +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +/* + * Here are the bits for the COMMIT register: + * bit 0 selects the threshold index for the chosen sensor (0/1) + * bit 1 enables/disables the selected threshold (0 = off, 1 = on) + * Each write to the commit register affects one threshold. + */ +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +/* + * Example: + * + * Set the thresholds for sensor 2 to 50 C and 60 C: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET + * write 0x2 to [0x07] -- enable threshold 0 with this value + * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET + * write 0x3 to [0x07] -- enable threshold 1 with this value + * + * Disable the 60 C threshold, leaving the 50 C threshold unchanged: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x1 to [0x07] -- disable threshold 1 + */ + +/* DPTF battery charging current limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 + +/* Charging limit is specified in 64 mA steps */ +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +/* Value to disable DPTF battery charging limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff + +/* + * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data + * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. + */ +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 + +/* Current version of ACPI memory address space */ +#define EC_ACPI_MEM_VERSION_CURRENT 2 + + /* * This header file is used in coreboot both in C and ACPI code. The ACPI code * is pre-processed to handle constants but the ASL compiler is unable to @@ -191,7 +337,7 @@ #define EC_LPC_STATUS_PROCESSING 0x04 /* Last write to EC was a command, not data */ #define EC_LPC_STATUS_LAST_CMD 0x08 -/* EC is in burst mode. Unsupported by Chrome EC, so this bit is never set */ +/* EC is in burst mode */ #define EC_LPC_STATUS_BURST_MODE 0x10 /* SCI event is pending (requesting SCI query) */ #define EC_LPC_STATUS_SCI_PENDING 0x20 @@ -2519,122 +2665,6 @@ struct ec_params_reboot_ec { /*****************************************************************************/ /* - * ACPI commands - * - * These are valid ONLY on the ACPI command/data port. - */ - -/* - * ACPI Read Embedded Controller - * - * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). - * - * Use the following sequence: - * - * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD - * - Wait for EC_LPC_CMDR_PENDING bit to clear - * - Write address to EC_LPC_ADDR_ACPI_DATA - * - Wait for EC_LPC_CMDR_DATA bit to set - * - Read value from EC_LPC_ADDR_ACPI_DATA - */ -#define EC_CMD_ACPI_READ 0x80 - -/* - * ACPI Write Embedded Controller - * - * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*). - * - * Use the following sequence: - * - * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD - * - Wait for EC_LPC_CMDR_PENDING bit to clear - * - Write address to EC_LPC_ADDR_ACPI_DATA - * - Wait for EC_LPC_CMDR_PENDING bit to clear - * - Write value to EC_LPC_ADDR_ACPI_DATA - */ -#define EC_CMD_ACPI_WRITE 0x81 - -/* - * ACPI Query Embedded Controller - * - * This clears the lowest-order bit in the currently pending host events, and - * sets the result code to the 1-based index of the bit (event 0x00000001 = 1, - * event 0x80000000 = 32), or 0 if no event was pending. - */ -#define EC_CMD_ACPI_QUERY_EVENT 0x84 - -/* Valid addresses in ACPI memory space, for read/write commands */ - -/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 -/* - * Test location; writing value here updates test compliment byte to (0xff - - * value). - */ -#define EC_ACPI_MEM_TEST 0x01 -/* Test compliment; writes here are ignored. */ -#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 - -/* Keyboard backlight brightness percent (0 - 100) */ -#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 -/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ -#define EC_ACPI_MEM_FAN_DUTY 0x04 - -/* - * DPTF temp thresholds. Any of the EC's temp sensors can have up to two - * independent thresholds attached to them. The current value of the ID - * register determines which sensor is affected by the THRESHOLD and COMMIT - * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme - * as the memory-mapped sensors. The COMMIT register applies those settings. - * - * The spec does not mandate any way to read back the threshold settings - * themselves, but when a threshold is crossed the AP needs a way to determine - * which sensor(s) are responsible. Each reading of the ID register clears and - * returns one sensor ID that has crossed one of its threshold (in either - * direction) since the last read. A value of 0xFF means "no new thresholds - * have tripped". Setting or enabling the thresholds for a sensor will clear - * the unread event count for that sensor. - */ -#define EC_ACPI_MEM_TEMP_ID 0x05 -#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 -#define EC_ACPI_MEM_TEMP_COMMIT 0x07 -/* - * Here are the bits for the COMMIT register: - * bit 0 selects the threshold index for the chosen sensor (0/1) - * bit 1 enables/disables the selected threshold (0 = off, 1 = on) - * Each write to the commit register affects one threshold. - */ -#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) -#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) -/* - * Example: - * - * Set the thresholds for sensor 2 to 50 C and 60 C: - * write 2 to [0x05] -- select temp sensor 2 - * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET - * write 0x2 to [0x07] -- enable threshold 0 with this value - * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET - * write 0x3 to [0x07] -- enable threshold 1 with this value - * - * Disable the 60 C threshold, leaving the 50 C threshold unchanged: - * write 2 to [0x05] -- select temp sensor 2 - * write 0x1 to [0x07] -- disable threshold 1 - */ - -/* DPTF battery charging current limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 - -/* Charging limit is specified in 64 mA steps */ -#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 -/* Value to disable DPTF battery charging limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff - -/* Current version of ACPI memory address space */ -#define EC_ACPI_MEM_VERSION_CURRENT 1 - - -/*****************************************************************************/ -/* * Special commands * * These do not follow the normal rules for commands. See each command for diff --git a/include/host_command.h b/include/host_command.h index 4bf903e6ef..f95fe06966 100644 --- a/include/host_command.h +++ b/include/host_command.h @@ -124,6 +124,20 @@ struct host_command { uint8_t *host_get_memmap(int offset); /** + * Grab the memmap write mutex. This function should be called before + * multi-byte variable reads from ACPI, and before updating multi-byte + * memmap variables anywhere else. + */ +void host_lock_memmap(void); + +/** + * Release the memmap write mutex. This function should be called once + * a multi-byte variable read from ACPI is done, and when updating multi-byte + * memmap variables is done. + */ +void host_unlock_memmap(void); + +/** * Process a host command and return its response * * @param args Command handler args diff --git a/include/lpc.h b/include/lpc.h index c16b1bc5d4..c38f711bda 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -97,6 +97,16 @@ void lpc_set_host_event_mask(enum lpc_host_event_type type, uint32_t mask); uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type); /** + * Set the EC_LPC_STATUS_* mask for the specified status. + */ +void lpc_set_acpi_status_mask(uint8_t mask); + +/** + * Clear the EC_LPC_STATUS_* mask for the specified status. + */ +void lpc_clear_acpi_status_mask(uint8_t mask); + +/** * Return the state of platform reset. * * @return non-zero if PLTRST# is asserted (low); 0 if not asserted (high). |