diff options
| -rw-r--r-- | chip/mchp/config_chip.h | 12 | ||||
| -rw-r--r-- | common/spi_flash.c | 2 | ||||
| -rw-r--r-- | include/config.h | 6 | ||||
| -rw-r--r-- | util/config_allowed.txt | 1 |
4 files changed, 20 insertions, 1 deletions
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h index 71b765894a..cf7ead512a 100644 --- a/chip/mchp/config_chip.h +++ b/chip/mchp/config_chip.h @@ -150,6 +150,18 @@ #define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000 #endif +/* + * Optimize SPI flash read timing, MEC172x QMSPI controller controls CS# + * by hardware, it will add several system clock cycles delay between CS + * deassertion to CS assertion at the start of the next transaction, this + * guarantees SPI back to back transactions, so 1ms delay can be removed + * to optimze timing. MEC172x chip supports this hardware feature. + */ +#if defined(CHIP_FAMILY_MEC172X) +#undef CONFIG_SPI_FLASH_READ_WAIT_MS +#define CONFIG_SPI_FLASH_READ_WAIT_MS 0 +#endif + #include "config_flash_layout.h" /************************************************************************/ diff --git a/common/spi_flash.c b/common/spi_flash.c index 1ee39e78d8..e202e1e17d 100644 --- a/common/spi_flash.c +++ b/common/spi_flash.c @@ -170,7 +170,7 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes) read_size); if (ret != EC_SUCCESS) break; - msleep(1); + msleep(CONFIG_SPI_FLASH_READ_WAIT_MS); } return ret; } diff --git a/include/config.h b/include/config.h index c51d8e73cb..43df9737fd 100644 --- a/include/config.h +++ b/include/config.h @@ -3657,6 +3657,12 @@ */ #undef CONFIG_MCHP_GPSPI +/* + * Configure SPI flash read wait time as 1ms + * Chip or board can redefine it per design + */ +#define CONFIG_SPI_FLASH_READ_WAIT_MS 1 + /* Default stack size to use for tasks, in bytes */ #undef CONFIG_STACK_SIZE diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 561416f7c8..d9b5fbc973 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -839,6 +839,7 @@ CONFIG_SPI_FLASH_GD25LQ40 CONFIG_SPI_FLASH_GD25Q41B CONFIG_SPI_FLASH_HAS_SR2 CONFIG_SPI_FLASH_PORT +CONFIG_SPI_FLASH_READ_WAIT_MS CONFIG_SPI_FLASH_W25Q128 CONFIG_SPI_FLASH_W25Q40 CONFIG_SPI_FLASH_W25Q64 |