diff options
20 files changed, 56 insertions, 316 deletions
diff --git a/zephyr/boards/arm/brya/brya_defconfig b/zephyr/boards/arm/brya/brya_defconfig index 4abece1033..e8c412a592 100644 --- a/zephyr/boards/arm/brya/brya_defconfig +++ b/zephyr/boards/arm/brya/brya_defconfig @@ -35,3 +35,7 @@ CONFIG_SOC_POWER_MANAGEMENT_TRACE=y # WATCHDOG configuration CONFIG_WATCHDOG=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig index 43efac9786..907ae9ed34 100644 --- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig +++ b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig @@ -34,3 +34,7 @@ CONFIG_SOC_POWER_MANAGEMENT=y CONFIG_PM_POLICY_APP=y CONFIG_UART_CONSOLE_INPUT_EXPIRED=y CONFIG_SOC_POWER_MANAGEMENT_TRACE=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/kohaku/kohaku_defconfig b/zephyr/boards/arm/kohaku/kohaku_defconfig index 3235c6bc19..eccf6da6ab 100644 --- a/zephyr/boards/arm/kohaku/kohaku_defconfig +++ b/zephyr/boards/arm/kohaku/kohaku_defconfig @@ -28,3 +28,7 @@ CONFIG_CLOCK_CONTROL=y # WATCHDOG configuration CONFIG_WATCHDOG=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig index bad16f240d..b2fc879cbc 100644 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig +++ b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig @@ -49,3 +49,7 @@ CONFIG_SOC_POWER_MANAGEMENT=y CONFIG_PM_POLICY_APP=y CONFIG_UART_CONSOLE_INPUT_EXPIRED=y CONFIG_SOC_POWER_MANAGEMENT_TRACE=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig index 5b58ecd9f2..9a946584ef 100644 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig +++ b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig @@ -48,3 +48,7 @@ CONFIG_SOC_POWER_MANAGEMENT=y CONFIG_PM_POLICY_APP=y CONFIG_UART_CONSOLE_INPUT_EXPIRED=y CONFIG_SOC_POWER_MANAGEMENT_TRACE=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/trogdor/trogdor_defconfig b/zephyr/boards/arm/trogdor/trogdor_defconfig index 4011f89a94..2a61f3dd5c 100644 --- a/zephyr/boards/arm/trogdor/trogdor_defconfig +++ b/zephyr/boards/arm/trogdor/trogdor_defconfig @@ -34,3 +34,7 @@ CONFIG_SOC_POWER_MANAGEMENT=y CONFIG_PM_POLICY_APP=y CONFIG_UART_CONSOLE_INPUT_EXPIRED=y CONFIG_SOC_POWER_MANAGEMENT_TRACE=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/volteer/volteer_defconfig b/zephyr/boards/arm/volteer/volteer_defconfig index d9299c680a..a3f184dff8 100644 --- a/zephyr/boards/arm/volteer/volteer_defconfig +++ b/zephyr/boards/arm/volteer/volteer_defconfig @@ -39,3 +39,7 @@ CONFIG_SOC_POWER_MANAGEMENT=y CONFIG_PM_POLICY_APP=y CONFIG_UART_CONSOLE_INPUT_EXPIRED=y CONFIG_SOC_POWER_MANAGEMENT_TRACE=y + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/riscv/asurada/asurada_defconfig b/zephyr/boards/riscv/asurada/asurada_defconfig index e7f3e7f924..be85cd0f07 100644 --- a/zephyr/boards/riscv/asurada/asurada_defconfig +++ b/zephyr/boards/riscv/asurada/asurada_defconfig @@ -93,3 +93,7 @@ CONFIG_ITE_IT8XXX2_TIMER=y CONFIG_WATCHDOG=y CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500 CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500 + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_IT8XXX2=y diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig index 915af78141..d667fac5a1 100644 --- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig +++ b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig @@ -69,3 +69,7 @@ CONFIG_CROS_EC_RO_MEM_OFF=0x0 CONFIG_CROS_EC_RO_SIZE=0x80000 CONFIG_CROS_EC_RW_MEM_OFF=0x0 CONFIG_CROS_EC_RW_SIZE=0x80000 + +# BBRAM +CONFIG_BBRAM=y +CONFIG_BBRAM_IT8XXX2=y diff --git a/zephyr/drivers/CMakeLists.txt b/zephyr/drivers/CMakeLists.txt index 6ab8383eb5..d246f31703 100644 --- a/zephyr/drivers/CMakeLists.txt +++ b/zephyr/drivers/CMakeLists.txt @@ -2,7 +2,6 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -add_subdirectory(cros_bbram) add_subdirectory(cros_cbi) add_subdirectory(cros_flash) add_subdirectory(cros_kb_raw) diff --git a/zephyr/drivers/Kconfig b/zephyr/drivers/Kconfig index 37cf390a64..041a6cf212 100644 --- a/zephyr/drivers/Kconfig +++ b/zephyr/drivers/Kconfig @@ -2,7 +2,6 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -rsource "cros_bbram/Kconfig" rsource "cros_flash/Kconfig" rsource "cros_kb_raw/Kconfig" rsource "cros_rtc/Kconfig" diff --git a/zephyr/drivers/cros_bbram/CMakeLists.txt b/zephyr/drivers/cros_bbram/CMakeLists.txt deleted file mode 100644 index 5a539a5e61..0000000000 --- a/zephyr/drivers/cros_bbram/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -zephyr_library_sources_ifdef(CONFIG_CROS_BBRAM_IT8XXX2 cros_bbram_it8xxx2.c) -zephyr_library_sources_ifdef(CONFIG_CROS_BBRAM_NPCX cros_bbram_npcx.c) diff --git a/zephyr/drivers/cros_bbram/Kconfig b/zephyr/drivers/cros_bbram/Kconfig deleted file mode 100644 index 63d6911d2b..0000000000 --- a/zephyr/drivers/cros_bbram/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -menuconfig CROS_BBRAM_NPCX - bool "Nuvoton NPCX battery backed RAM driver for Zephyr" - depends on SOC_FAMILY_NPCX - default y - help - This enables the NPCX cros_bbram driver. The NPCX BBRAM module - provides 128 bytes of battery-backed memory area. - -if CROS_BBRAM_NPCX - -config CROS_BBRAM_NPCX_INIT_PRIORITY - int "cros_bbram npcx initialization priority" - default 11 - range 10 19 - help - This sets the npcx cros_bbram driver initialization priority. NPCX - chip uses BBRAM to save some system information that persists across - chip resets. The priority should be higher than - SYSTEM_PRE_INIT_PRIORITY & lower than CROS_SYSTEM_NPCX_INIT_PRIORITY. - -endif # CROS_BBRAM_NPCX - -config CROS_BBRAM_IT8XXX2 - bool "ITE IT81202 battery backed RAM driver for Zephyr" - depends on SOC_FAMILY_RISCV_ITE - default y - help - This module provides 192 bytes of battery-backed memory area. - -if CROS_BBRAM_IT8XXX2 - -config CROS_BBRAM_IT8XXX2_INIT_PRIORITY - int "cros_bbram it8xxx2 initialization priority" - default 11 - help - This sets the it8xxx2 cros_bbram driver initialization priority. - -endif # CROS_BBRAM_IT8XXX2 diff --git a/zephyr/drivers/cros_bbram/cros_bbram_it8xxx2.c b/zephyr/drivers/cros_bbram/cros_bbram_it8xxx2.c deleted file mode 100644 index cf2586ff96..0000000000 --- a/zephyr/drivers/cros_bbram/cros_bbram_it8xxx2.c +++ /dev/null @@ -1,77 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#define DT_DRV_COMPAT ite_it8xxx2_cros_bbram - -#include <drivers/cros_bbram.h> -#include <errno.h> -#include <logging/log.h> -#include <sys/util.h> - -LOG_MODULE_REGISTER(cros_bbram, LOG_LEVEL_ERR); - -/* Device config */ -struct cros_bbram_it8xxx2_config { - /* BBRAM base address */ - uintptr_t base_addr; - /* BBRAM size (Unit:bytes) */ - int size; -}; - -#define DRV_CONFIG(dev) \ - ((const struct cros_bbram_it8xxx2_config *)(dev)->config) - -static int cros_bbram_it8xxx2_read(const struct device *dev, int offset, - int size, uint8_t *data) -{ - const struct cros_bbram_it8xxx2_config *config = DRV_CONFIG(dev); - - if (offset < 0 || size < 1 || offset + size >= config->size) { - return -EFAULT; - } - - for (size_t i = 0; i < size; ++i) { - *(data + i) = - *((volatile uint8_t *)config->base_addr + offset + i); - } - return 0; -} - -static int cros_bbram_it8xxx2_write(const struct device *dev, int offset, - int size, uint8_t *data) -{ - const struct cros_bbram_it8xxx2_config *config = DRV_CONFIG(dev); - - if (offset < 0 || size < 1 || offset + size >= config->size) { - return -EFAULT; - } - - for (size_t i = 0; i < size; ++i) { - *((volatile uint8_t *)config->base_addr + offset + i) = - *(data + i); - } - return 0; -} - -static const struct cros_bbram_driver_api cros_bbram_it8xxx2_driver_api = { - .read = cros_bbram_it8xxx2_read, - .write = cros_bbram_it8xxx2_write, -}; - -static int bbram_it8xxx2_init(const struct device *dev) -{ - ARG_UNUSED(dev); - - return 0; -} - -static const struct cros_bbram_it8xxx2_config cros_bbram_cfg = { - .base_addr = DT_INST_REG_ADDR_BY_NAME(0, memory), - .size = DT_INST_REG_SIZE_BY_NAME(0, memory), -}; - -DEVICE_DT_INST_DEFINE(0, bbram_it8xxx2_init, NULL, NULL, &cros_bbram_cfg, - PRE_KERNEL_1, CONFIG_CROS_BBRAM_IT8XXX2_INIT_PRIORITY, - &cros_bbram_it8xxx2_driver_api); diff --git a/zephyr/drivers/cros_bbram/cros_bbram_npcx.c b/zephyr/drivers/cros_bbram/cros_bbram_npcx.c deleted file mode 100644 index 8f1d96ff91..0000000000 --- a/zephyr/drivers/cros_bbram/cros_bbram_npcx.c +++ /dev/null @@ -1,150 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#define DT_DRV_COMPAT nuvoton_npcx_cros_bbram - -#include <drivers/cros_bbram.h> -#include <drivers/cros_system.h> -#include <errno.h> -#include <logging/log.h> -#include <sys/util.h> - -LOG_MODULE_REGISTER(cros_bbram, LOG_LEVEL_ERR); - -/* Device config */ -struct cros_bbram_npcx_config { - /* BBRAM base address */ - uintptr_t base_addr; - /* BBRAM size (Unit:bytes) */ - int size; - /* Status register base address */ - uintptr_t status_reg_addr; -}; - -#define NPCX_STATUS_IBBR BIT(7) -#define NPCX_STATUS_VSBY BIT(1) -#define NPCX_STATUS_VCC1 BIT(0) - -#define DRV_CONFIG(dev) ((const struct cros_bbram_npcx_config *)(dev)->config) -#define DRV_STATUS(dev) \ - (*((volatile uint8_t *)DRV_CONFIG(dev)->status_reg_addr)) - -static int cros_bbram_npcx_ibbr(const struct device *dev) -{ - return DRV_STATUS(dev) & NPCX_STATUS_IBBR; -} - -static int cros_bbram_npcx_reset_ibbr(const struct device *dev) -{ - DRV_STATUS(dev) = NPCX_STATUS_IBBR; - return 0; -} - -static int cros_bbram_npcx_vsby(const struct device *dev) -{ - return DRV_STATUS(dev) & NPCX_STATUS_VSBY; -} - -static int cros_bbram_npcx_reset_vsby(const struct device *dev) -{ - DRV_STATUS(dev) = NPCX_STATUS_VSBY; - return 0; -} - -static int cros_bbram_npcx_vcc1(const struct device *dev) -{ - return DRV_STATUS(dev) & NPCX_STATUS_VCC1; -} - -static int cros_bbram_npcx_reset_vcc1(const struct device *dev) -{ - DRV_STATUS(dev) = NPCX_STATUS_VCC1; - return 0; -} - -static int cros_bbram_npcx_read(const struct device *dev, int offset, int size, - uint8_t *data) -{ - const struct cros_bbram_npcx_config *config = DRV_CONFIG(dev); - - if (offset < 0 || size < 1 || offset + size >= config->size || - cros_bbram_npcx_ibbr(dev)) { - return -EFAULT; - } - - for (size_t i = 0; i < size; ++i) { - *(data + i) = - *((volatile uint8_t *)config->base_addr + offset + i); - } - return 0; -} - -static int cros_bbram_npcx_write(const struct device *dev, int offset, int size, - uint8_t *data) -{ - const struct cros_bbram_npcx_config *config = DRV_CONFIG(dev); - - if (offset < 0 || size < 1 || offset + size >= config->size || - cros_bbram_npcx_ibbr(dev)) { - return -EFAULT; - } - - for (size_t i = 0; i < size; ++i) { - *((volatile uint8_t *)config->base_addr + offset + i) = - *(data + i); - } - return 0; -} - -static const struct cros_bbram_driver_api cros_bbram_npcx_driver_api = { - .ibbr = cros_bbram_npcx_ibbr, - .reset_ibbr = cros_bbram_npcx_reset_ibbr, - .vsby = cros_bbram_npcx_vsby, - .reset_vsby = cros_bbram_npcx_reset_vsby, - .vcc1 = cros_bbram_npcx_vcc1, - .reset_vcc1 = cros_bbram_npcx_reset_vcc1, - .read = cros_bbram_npcx_read, - .write = cros_bbram_npcx_write, -}; - -static int bbram_npcx_init(const struct device *dev) -{ - const struct device *sys_dev = device_get_binding("CROS_SYSTEM"); - int reset = cros_system_get_reset_cause(sys_dev); - - if (reset == POWERUP) { - /* clear the status register when EC power-up*/ - DRV_STATUS(dev) = NPCX_STATUS_IBBR | NPCX_STATUS_VSBY | - NPCX_STATUS_VCC1; - } - - return 0; -} - -/* - * The priority of bbram_npcx_init() should lower than cros_system_npcx_init(). - */ -#if (CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY <= \ - CONFIG_CROS_SYSTEM_NPCX_INIT_PRIORITY) -#error CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY must greater than \ - CONFIG_CROS_SYSTEM_NPCX_INIT_PRIORITY -#endif - -#define CROS_BBRAM_INIT(inst) \ - static struct { \ - } cros_bbram_data_##inst; \ - static const struct cros_bbram_npcx_config cros_bbram_cfg_##inst = { \ - .base_addr = DT_INST_REG_ADDR_BY_NAME(inst, memory), \ - .size = DT_INST_REG_SIZE_BY_NAME(inst, memory), \ - .status_reg_addr = DT_INST_REG_ADDR_BY_NAME(inst, status), \ - }; \ - DEVICE_DT_INST_DEFINE(inst, \ - bbram_npcx_init, NULL, \ - &cros_bbram_data_##inst, \ - &cros_bbram_cfg_##inst, PRE_KERNEL_1, \ - CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY, \ - &cros_bbram_npcx_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(CROS_BBRAM_INIT); diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index 80c663020f..e3d3bc29b2 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -77,7 +77,7 @@ struct cros_system_npcx_data { /* Get saved reset flag address in battery-backed ram */ #define BBRAM_SAVED_RESET_FLAG_ADDR \ - (DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_bbram)) + \ + (DT_REG_ADDR(DT_INST(0, nuvoton_npcx_bbram)) + \ DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset)) /* Soc specific system local functions */ diff --git a/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml b/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml deleted file mode 100644 index bfd6a8bc8f..0000000000 --- a/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Google Inc. -# SPDX-License-Identifier: Apache-2.0 - -description: Nuvoton, NPCX Battery Backed RAM node - -compatible: "nuvoton,npcx-cros-bbram" - -include: base.yaml - -properties: - reg: - required: true diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi index 8e7b8a7973..1121dcf0a9 100644 --- a/zephyr/include/cros/nuvoton/npcx.dtsi +++ b/zephyr/include/cros/nuvoton/npcx.dtsi @@ -62,17 +62,6 @@ soc { - bbram: bb-ram@400af000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nuvoton,npcx-cros-bbram"; - status = "okay"; - reg = <0x400af000 0x80 - 0x400af100 0x1>; - reg-names = "memory", "status"; - label = "BBRAM"; - }; - cros_kb_raw: cros-kb-raw@400a3000 { compatible = "nuvoton,npcx-cros-kb-raw"; reg = <0x400a3000 0x2000>; @@ -160,3 +149,7 @@ &cpu0 { cpu-power-states = <&suspend_to_idle_instant &suspend_to_idle_normal>; }; + +&bbram { + status = "okay"; +}; diff --git a/zephyr/shim/chip/npcx/Kconfig.npcx b/zephyr/shim/chip/npcx/Kconfig.npcx index 1107a846a8..b044912ae1 100644 --- a/zephyr/shim/chip/npcx/Kconfig.npcx +++ b/zephyr/shim/chip/npcx/Kconfig.npcx @@ -12,7 +12,7 @@ config CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY help This sets the priority of the NPCX chip system initialization. The chip system initialization verifies the integrity of the BBRAM and - must be a lower priority than CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY and + must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT. endif # PLATFORM_EC diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c index 0a1f50844e..3700026104 100644 --- a/zephyr/shim/chip/npcx/system.c +++ b/zephyr/shim/chip/npcx/system.c @@ -3,7 +3,7 @@ * found in the LICENSE file. */ -#include <drivers/cros_bbram.h> +#include <drivers/bbram.h> #include <logging/log.h> #include "system.h" @@ -11,9 +11,10 @@ LOG_MODULE_REGISTER(shim_npcx_system, LOG_LEVEL_ERR); -void chip_bbram_status_check(void) +static void chip_bbram_status_check(void) { const struct device *bbram_dev; + int res; bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram)); if (!device_is_ready(bbram_dev)) { @@ -21,18 +22,18 @@ void chip_bbram_status_check(void) return; } - if (cros_bbram_get_ibbr(bbram_dev)) { + res = bbram_check_invalid(bbram_dev); + if (res != 0 && res != -ENOTSUP) LOG_ERR("VBAT power drop!"); - cros_bbram_reset_ibbr(bbram_dev); - } - if (cros_bbram_get_vsby(bbram_dev)) { + + res = bbram_check_standby_power(bbram_dev); + if (res != 0 && res != -ENOTSUP) LOG_ERR("VSBY power drop!"); - cros_bbram_reset_vsby(bbram_dev); - } - if (cros_bbram_get_vcc1(bbram_dev)) { + + res = bbram_check_power(bbram_dev); + if (res != 0 && res != -ENOTSUP) LOG_ERR("VCC1 power drop!"); - cros_bbram_reset_vcc1(bbram_dev); - } + } /* @@ -89,10 +90,9 @@ static int chip_system_init(const struct device *unused) /* * The priority should be lower than CROS_BBRAM_NPCX_INIT_PRIORITY. */ -#if (CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY <= \ - CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY) +#if (CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY <= CONFIG_BBRAM_INIT_PRIORITY) #error CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY must greater than \ - CONFIG_CROS_BBRAM_NPCX_INIT_PRIORITY + CONFIG_BBRAM_INIT_PRIORITY #endif SYS_INIT(chip_system_init, PRE_KERNEL_1, CONFIG_CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY); |