diff options
-rw-r--r-- | baseboard/herobrine/baseboard.h | 2 | ||||
-rw-r--r-- | baseboard/trogdor/baseboard.h | 2 | ||||
-rw-r--r-- | board/cheza/board.h | 2 | ||||
-rw-r--r-- | board/coral/gpio.inc | 2 | ||||
-rw-r--r-- | board/npcx_evb_arm/board.h | 2 | ||||
-rw-r--r-- | board/reef/gpio.inc | 2 | ||||
-rw-r--r-- | board/reef_mchp/gpio.inc | 2 | ||||
-rw-r--r-- | chip/npcx/build.mk | 2 | ||||
-rw-r--r-- | chip/npcx/gpio-npcx5.c | 2 | ||||
-rw-r--r-- | chip/npcx/gpio-npcx9.c | 2 | ||||
-rw-r--r-- | chip/npcx/gpio.c | 2 | ||||
-rw-r--r-- | chip/npcx/shi_chip.h | 2 | ||||
-rw-r--r-- | docs/configuration/config_ap_to_ec_comm.md | 2 | ||||
-rw-r--r-- | docs/ec_terms.md | 9 | ||||
-rw-r--r-- | include/config.h | 5 | ||||
-rw-r--r-- | util/config_allowed.txt | 2 |
16 files changed, 26 insertions, 16 deletions
diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h index bcb62e9ef4..5d272ea67e 100644 --- a/baseboard/herobrine/baseboard.h +++ b/baseboard/herobrine/baseboard.h @@ -41,7 +41,7 @@ #undef CONFIG_PECI -#define CONFIG_HOSTCMD_SPS +#define CONFIG_HOSTCMD_SHI #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_HOSTCMD_SECTION_SORTED #define CONFIG_KEYBOARD_COL2_INVERTED diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h index faa6b0983c..4eabeb0ca3 100644 --- a/baseboard/trogdor/baseboard.h +++ b/baseboard/trogdor/baseboard.h @@ -41,7 +41,7 @@ #undef CONFIG_PECI -#define CONFIG_HOSTCMD_SPS +#define CONFIG_HOSTCMD_SHI #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_HOSTCMD_SECTION_SORTED #define CONFIG_KEYBOARD_COL2_INVERTED diff --git a/board/cheza/board.h b/board/cheza/board.h index f30219aaf5..9246151698 100644 --- a/board/cheza/board.h +++ b/board/cheza/board.h @@ -50,7 +50,7 @@ #undef CONFIG_PECI -#define CONFIG_HOSTCMD_SPS +#define CONFIG_HOSTCMD_SHI #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_HOSTCMD_SECTION_SORTED /* Host commands are sorted. */ #define CONFIG_MKBP_EVENT diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc index 43a130a140..8e52eeeed2 100644 --- a/board/coral/gpio.inc +++ b/board/coral/gpio.inc @@ -62,7 +62,7 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT) * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). * - * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option. + * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option. */ GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */ diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index 3598457a5e..c3fd341365 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -11,7 +11,7 @@ /* Optional modules */ #define CONFIG_ADC #define CONFIG_PWM -#define CONFIG_HOSTCMD_SPS /* Used in ARM-based platform for host interface */ +#define CONFIG_HOSTCMD_SHI /* Used in ARM-based platform for host interface */ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index 2b6a5342f4..5bf83f88bc 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -67,7 +67,7 @@ GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT) * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). * - * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option. + * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option. */ GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */ diff --git a/board/reef_mchp/gpio.inc b/board/reef_mchp/gpio.inc index ff98b4c1b9..0385d82102 100644 --- a/board/reef_mchp/gpio.inc +++ b/board/reef_mchp/gpio.inc @@ -84,7 +84,7 @@ GPIO(EC_I2C_POWER_SCL, PIN(010), GPIO_INPUT) * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). * - * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option. + * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SHI option. */ GPIO(PCH_SMI_L, PIN(0227), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */ diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index a013ef5ef5..4be1b2994f 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -32,7 +32,7 @@ chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o chip-$(CONFIG_PECI)+=peci.o -chip-$(CONFIG_HOSTCMD_SPS)+=shi.o +chip-$(CONFIG_HOSTCMD_SHI)+=shi.o chip-$(CONFIG_CEC)+=cec.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index d6a28300ba..e1d13c98d1 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -179,7 +179,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index 441924d89e..2bb4ae085c 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -196,7 +196,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index fece08c0f4..e740f0aa9f 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -560,7 +560,7 @@ void gpio_pre_init(void) #endif /* Pin_Mux for LPC & SHI */ -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; /* Alternate Intel bus interface LPC/eSPI to GPIOs first */ diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index f701067715..c14aec196e 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -8,7 +8,7 @@ #ifndef SHI_CHIP_H_ #define SHI_CHIP_H_ -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /** * Called when the NSS level changes, signalling the start of a SHI * transaction. diff --git a/docs/configuration/config_ap_to_ec_comm.md b/docs/configuration/config_ap_to_ec_comm.md index 7110185bcb..1fe3d86e98 100644 --- a/docs/configuration/config_ap_to_ec_comm.md +++ b/docs/configuration/config_ap_to_ec_comm.md @@ -9,7 +9,7 @@ details a system level of the operation of this feature. Configure the AP to EC communication channel, picking exactly one of the following options. -- `CONFIG_HOSTCMD_SPS` - [SPI slave](./ec_terms.md#spi) (SPS) interface +- `CONFIG_HOSTCMD_SHI` - [SPI Host Interface](./ec_terms.md#shi) (SHI) - `CONFIG_HOSTCMD_HECI` - HECI interface - `CONFIG_HOSTCMD_LPC` - [LPC](./ec_terms.md#lpc) bus - `CONFIG_HOSTCMD_ESPI` - [eSPI](./ec_terms.md#espi) bus diff --git a/docs/ec_terms.md b/docs/ec_terms.md index 7e3dadce86..770278eaf6 100644 --- a/docs/ec_terms.md +++ b/docs/ec_terms.md @@ -187,6 +187,15 @@ [chromium.org documentation](https://www.chromium.org/for-testers/saft) for more details. +* **SHI - SPI Host Interface** {#shi} + + [SPI](#spi) host interface used for communication between the AP and the EC. + In this configuration, the AP provides the SPI controller and the EC + provides the SPI peripheral. This interface is only used for non-x86 base + APs. + + x86-based APs use either the [eSPI](#espi) or [LPC](#lpc) interface. + * **SPI - Serial Peripheral Interconnect** {#spi} A 4-wire synchronous communication bus consisting of the signals CLK diff --git a/include/config.h b/include/config.h index 1ca75dc4f9..c51d8e73cb 100644 --- a/include/config.h +++ b/include/config.h @@ -2238,9 +2238,10 @@ #undef CONFIG_HOSTCMD_I2C_ADDR_FLAGS /* - * Accept EC host commands over the SPI slave (SPS) interface. + * Accept EC host commands over the SPI host interface. The AP is SPI + * controller and the EC is the SPI peripheral for this configuration. */ -#undef CONFIG_HOSTCMD_SPS +#undef CONFIG_HOSTCMD_SHI /* * Host command rate limiting assures EC will have time to process lower diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 800dc6a0aa..561416f7c8 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -512,8 +512,8 @@ CONFIG_HOSTCMD_RATE_LIMITING_PERIOD CONFIG_HOSTCMD_RATE_LIMITING_RECESS CONFIG_HOSTCMD_RWHASHPD CONFIG_HOSTCMD_SECTION_SORTED +CONFIG_HOSTCMD_SHI CONFIG_HOSTCMD_SKUID -CONFIG_HOSTCMD_SPS CONFIG_HOSTCMD_X86 CONFIG_HOST_COMMAND_STATUS CONFIG_HOST_ESPI_VW_POWER_SIGNAL |