diff options
263 files changed, 2488 insertions, 2484 deletions
diff --git a/board/atlas/board.c b/board/atlas/board.c index 3be1ebfb3d..e0fc4d07e7 100644 --- a/board/atlas/board.c +++ b/board/atlas/board.c @@ -274,7 +274,7 @@ static void board_report_pmic_fault(const char *str) BD99992GW_REG_RESETIRQ1, &vrfault) != EC_SUCCESS) return; - if (!(vrfault & (1 << 4))) + if (!(vrfault & BIT(4))) return; /* VRFAULT has occurred, print VRFAULT status bits. */ @@ -293,7 +293,7 @@ static void board_report_pmic_fault(const char *str) /* Clear all faults -- Write 1 to clear. */ i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, - BD99992GW_REG_RESETIRQ1, (1 << 4)); + BD99992GW_REG_RESETIRQ1, BIT(4)); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, BD99992GW_REG_PWRSTAT1, pwrstat1); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c index bddfb0d159..e00c9e7b4b 100644 --- a/board/coffeecake/board.c +++ b/board/coffeecake/board.c @@ -140,15 +140,15 @@ void board_set_usb_output_voltage(int mv) void board_config_pre_init(void) { /* Enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Enable DAC interface clock. */ - STM32_RCC_APB1ENR |= (1 << 29); + STM32_RCC_APB1ENR |= BIT(29); /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* Set 5Vsafe Vdac */ board_set_usb_output_voltage(5000); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ } #ifdef CONFIG_SPI_FLASH @@ -156,7 +156,7 @@ void board_config_pre_init(void) static void board_init_spi2(void) { /* Remap SPI2 to DMA channels 6 and 7 */ - STM32_SYSCFG_CFGR1 |= (1 << 24); + STM32_SYSCFG_CFGR1 |= BIT(24); /* Set pin NSS to general purpose output mode (01b). */ /* Set pins SCK, MISO, and MOSI to alternate function (10b). */ @@ -176,8 +176,8 @@ static void board_init_spi2(void) STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000; /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); /* Enable clocks to SPI2 module */ STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h index 2282ea4e4b..e2c1dbb2db 100644 --- a/board/coffeecake/usb_pd_config.h +++ b/board/coffeecake/usb_pd_config.h @@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) (1 << 21) +#define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ diff --git a/board/cr50/rdd.c b/board/cr50/rdd.c index 8128d1b24c..876ba5dcef 100644 --- a/board/cr50/rdd.c +++ b/board/cr50/rdd.c @@ -34,15 +34,15 @@ enum ccd_block_flags { * UARTs. Disabling these can be helpful if the AP or EC is doing * something which creates an interrupt storm on these ports. */ - CCD_BLOCK_AP_UART = (1 << 0), - CCD_BLOCK_EC_UART = (1 << 1), + CCD_BLOCK_AP_UART = BIT(0), + CCD_BLOCK_EC_UART = BIT(1), /* * Any ports shared with servo. Disabling these will stop CCD from * interfering with servo, in the case where both CCD and servo is * connected but servo isn't properly detected. */ - CCD_BLOCK_SERVO_SHARED = (1 << 2) + CCD_BLOCK_SERVO_SHARED = BIT(2) }; /* Which UARTs are blocked by console command */ @@ -128,28 +128,28 @@ enum ccd_state_flag { /* Flags for individual devices/ports */ /* AP UART is enabled. RX-only, unless TX is also enabled. */ - CCD_ENABLE_UART_AP = (1 << 0), + CCD_ENABLE_UART_AP = BIT(0), /* AP UART transmit is enabled. Requires AP UART enabled. */ - CCD_ENABLE_UART_AP_TX = (1 << 1), + CCD_ENABLE_UART_AP_TX = BIT(1), /* EC UART is enabled. RX-only, unless TX is also enabled. */ - CCD_ENABLE_UART_EC = (1 << 2), + CCD_ENABLE_UART_EC = BIT(2), /* EC UART transmit is enabled. Requires EC UART enabled. */ - CCD_ENABLE_UART_EC_TX = (1 << 3), + CCD_ENABLE_UART_EC_TX = BIT(3), /* * EC UART bit-banging is enabled. Requires EC UART enabled, and * blocks EC UART transmit. */ - CCD_ENABLE_UART_EC_BITBANG = (1 << 4), + CCD_ENABLE_UART_EC_BITBANG = BIT(4), /* I2C port is enabled */ - CCD_ENABLE_I2C = (1 << 5), + CCD_ENABLE_I2C = BIT(5), /* SPI port is enabled for AP and/or EC flash */ - CCD_ENABLE_SPI = (1 << 6), + CCD_ENABLE_SPI = BIT(6), }; int console_is_restricted(void) diff --git a/board/cr50/scratch_reg1.h b/board/cr50/scratch_reg1.h index f4388ece18..6fdfe12181 100644 --- a/board/cr50/scratch_reg1.h +++ b/board/cr50/scratch_reg1.h @@ -11,8 +11,8 @@ * Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives * all kinds of resets, it is cleared only on the Power ON event. */ -#define BOARD_SLAVE_CONFIG_SPI (1 << 0) /* TPM uses SPI interface */ -#define BOARD_SLAVE_CONFIG_I2C (1 << 1) /* TPM uses I2C interface */ +#define BOARD_SLAVE_CONFIG_SPI BIT(0) /* TPM uses SPI interface */ +#define BOARD_SLAVE_CONFIG_I2C BIT(1) /* TPM uses I2C interface */ /* * The gaps are left to ensure backwards compatibility with the earliest cr50 @@ -21,20 +21,20 @@ */ /* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */ -#define BOARD_NEEDS_SYS_RST_PULL_UP (1 << 5) /* Add a pullup to sys_rst_l */ -#define BOARD_USE_PLT_RESET (1 << 6) /* Use plt_rst_l instead of */ +#define BOARD_NEEDS_SYS_RST_PULL_UP BIT(5) /* Add a pullup to sys_rst_l */ +#define BOARD_USE_PLT_RESET BIT(6) /* Use plt_rst_l instead of */ /* sys_rst_l to monitor the */ /* system resets */ /* Bits to store write protect bit state across deep sleep and resets. */ -#define BOARD_WP_ASSERTED (1 << 8) -#define BOARD_FORCING_WP (1 << 9) +#define BOARD_WP_ASSERTED BIT(8) +#define BOARD_FORCING_WP BIT(9) /* * Bit to signal to compatible RO to suppress its uart output. * Helps to reduce time to resume from deep sleep. */ -#define BOARD_NO_RO_UART (1 << 10) +#define BOARD_NO_RO_UART BIT(10) /* * Bits to store current case-closed debug state across deep sleep. @@ -46,18 +46,18 @@ #define BOARD_CCD_STATE (3 << BOARD_CCD_SHIFT) /* Prevent Cr50 from entering deep sleep when the AP is off */ -#define BOARD_DEEP_SLEEP_DISABLED (1 << 13) +#define BOARD_DEEP_SLEEP_DISABLED BIT(13) /* Use Cr50_RX_AP_TX to determine if the AP is off or on */ -#define BOARD_DETECT_AP_WITH_UART (1 << 14) +#define BOARD_DETECT_AP_WITH_UART BIT(14) /* ITE EC sync sequence generation after reset is required. */ -#define BOARD_ITE_EC_SYNC_NEEDED (1 << 15) +#define BOARD_ITE_EC_SYNC_NEEDED BIT(15) /* * Enable delayed write protect disable for systems that can be opened * in less than 2 minutes */ -#define BOARD_WP_DISABLE_DELAY (1 << 16) +#define BOARD_WP_DISABLE_DELAY BIT(16) /* * Enable custom options required for the closed source EC on the * Sarien/Arcada boards. Includes the following behavior @@ -67,18 +67,18 @@ * EC extended reset * Power+Refresh recovery mode (instead of Power+Refresh+Esc) */ -#define BOARD_CLOSED_SOURCE_SET1 (1 << 17) +#define BOARD_CLOSED_SOURCE_SET1 BIT(17) /* * Wait until PLT_RST_L is asserted before deasserting reset. */ -#define BOARD_CLOSED_LOOP_RESET (1 << 18) +#define BOARD_CLOSED_LOOP_RESET BIT(18) /* * The board uses INA pins as GPIOs, so it can't support reading inas using usb * i2c. */ -#define BOARD_NO_INA_SUPPORT (1 << 19) +#define BOARD_NO_INA_SUPPORT BIT(19) /* * Macro to capture all properties related to board strapping pins. This must be diff --git a/board/cr50/wp.c b/board/cr50/wp.c index 8c4980a70d..b1be6a87b5 100644 --- a/board/cr50/wp.c +++ b/board/cr50/wp.c @@ -277,7 +277,7 @@ int board_wipe_tpm(void) * git sha c7282f6. */ #define FWMP_HASH_SIZE 32 -#define FWMP_DEV_DISABLE_CCD_UNLOCK (1 << 6) +#define FWMP_DEV_DISABLE_CCD_UNLOCK BIT(6) #define FIRMWARE_FLAG_DEV_MODE 0x02 struct RollbackSpaceFirmware { diff --git a/board/dingdong/board.c b/board/dingdong/board.c index ae79cb5b6b..b03275555e 100644 --- a/board/dingdong/board.c +++ b/board/dingdong/board.c @@ -95,9 +95,9 @@ void hpd_event(enum gpio_signal signal) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ } /* Initialize board. */ diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h index 33e7225131..309c2200f9 100644 --- a/board/dingdong/usb_pd_config.h +++ b/board/dingdong/usb_pd_config.h @@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) (1 << 21) +#define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c index 7a16208498..2cc98da410 100644 --- a/board/discovery-stm32f072/board.c +++ b/board/discovery-stm32f072/board.c @@ -160,7 +160,7 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); void usb_spi_board_enable(struct usb_spi_config const *config) { /* Remap SPI2 to DMA channels 6 and 7 */ - STM32_SYSCFG_CFGR1 |= (1 << 24); + STM32_SYSCFG_CFGR1 |= BIT(24); /* Configure SPI GPIOs */ gpio_config_module(MODULE_SPI_FLASH, 1); diff --git a/board/eve/board.c b/board/eve/board.c index 1af42167b3..ea213d9b9f 100644 --- a/board/eve/board.c +++ b/board/eve/board.c @@ -374,7 +374,7 @@ static void board_report_pmic_fault(const char *str) != EC_SUCCESS) return; - if (!(vrfault & (1 << 4))) + if (!(vrfault & BIT(4))) return; /* VRFAULT has occurred, print VRFAULT status bits. */ @@ -390,7 +390,7 @@ static void board_report_pmic_fault(const char *str) pwrstat2); /* Clear all faults -- Write 1 to clear. */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4)); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4)); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2); @@ -901,7 +901,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &g_bmi160_data, .port = I2C_PORT_GYRO, .addr = BMI160_ADDR0, - .default_range = 1 << 11, /* 16LSB / uT, fixed */ + .default_range = BIT(11), /* 16LSB / uT, fixed */ .rot_standard_ref = &mag_standard_ref, .min_frequency = BMM150_MAG_MIN_FREQ, .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL), diff --git a/board/fizz/board.c b/board/fizz/board.c index 75450fd725..e200c4722e 100644 --- a/board/fizz/board.c +++ b/board/fizz/board.c @@ -703,7 +703,7 @@ static const struct charge_port_info bj_adapters[] = { * KBL-U Celeron 3965 7 65 * KBL-U Celeron 3865 0 65 */ -#define BJ_ADAPTER_90W_MASK (1 << 4 | 1 << 5 | 1 << 6) +#define BJ_ADAPTER_90W_MASK (BIT(4) | BIT(5) | BIT(6)) static void setup_bj(void) { diff --git a/board/flapjack/board.h b/board/flapjack/board.h index 8ca624a1f2..3cf5bacc64 100644 --- a/board/flapjack/board.h +++ b/board/flapjack/board.h @@ -210,7 +210,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)) /* Define panel size mask according to skuid */ -#define SKU_ID_PANEL_SIZE_MASK (1 << 1) +#define SKU_ID_PANEL_SIZE_MASK BIT(1) #ifndef __ASSEMBLER__ diff --git a/board/glados_pd/board.c b/board/glados_pd/board.c index f97845aa24..07ac9b7f06 100644 --- a/board/glados_pd/board.c +++ b/board/glados_pd/board.c @@ -37,7 +37,7 @@ void pd_send_ec_int(void) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* * the DMA mapping is : * Chan 2 : TIM1_CH1 (C0 RX) diff --git a/board/glados_pd/usb_pd_config.h b/board/glados_pd/usb_pd_config.h index 8df3f84dc1..4eee78383d 100644 --- a/board/glados_pd/usb_pd_config.h +++ b/board/glados_pd/usb_pd_config.h @@ -72,7 +72,7 @@ static inline void spi_enable_clock(int port) * EXTI line 22 is connected to the CMP2 output, * C0 uses CMP2, and C1 uses CMP1. */ -#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22)) +#define EXTI_COMP_MASK(p) ((p) ? BIT(21) : BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -108,12 +108,12 @@ static inline void pd_tx_spi_reset(int port) { if (port == 0) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } else { /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); } } diff --git a/board/glkrvp/chg_usb_pd.c b/board/glkrvp/chg_usb_pd.c index 152e79142b..c10c1e14a4 100644 --- a/board/glkrvp/chg_usb_pd.c +++ b/board/glkrvp/chg_usb_pd.c @@ -19,10 +19,10 @@ #define PTN5110_EXT_GPIO_CONFIG 0x92 #define PTN5110_EXT_GPIO_CONTROL 0x93 -#define PTN5110_EXT_GPIO_FRS_EN (1 << 6) -#define PTN5110_EXT_GPIO_EN_SRC (1 << 5) -#define PTN5110_EXT_GPIO_EN_SNK1 (1 << 4) -#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L (1 << 3) +#define PTN5110_EXT_GPIO_FRS_EN BIT(6) +#define PTN5110_EXT_GPIO_EN_SRC BIT(5) +#define PTN5110_EXT_GPIO_EN_SNK1 BIT(4) +#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L BIT(3) enum glkrvp_charge_ports { TYPE_C_PORT_0, diff --git a/board/glkrvp_ite/chg_usb_pd.c b/board/glkrvp_ite/chg_usb_pd.c index 0b1a188081..1ddef2c60d 100644 --- a/board/glkrvp_ite/chg_usb_pd.c +++ b/board/glkrvp_ite/chg_usb_pd.c @@ -19,10 +19,10 @@ #define PTN5110_EXT_GPIO_CONFIG 0x92 #define PTN5110_EXT_GPIO_CONTROL 0x93 -#define PTN5110_EXT_GPIO_FRS_EN (1 << 6) -#define PTN5110_EXT_GPIO_EN_SRC (1 << 5) -#define PTN5110_EXT_GPIO_EN_SNK1 (1 << 4) -#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L (1 << 3) +#define PTN5110_EXT_GPIO_FRS_EN BIT(6) +#define PTN5110_EXT_GPIO_EN_SRC BIT(5) +#define PTN5110_EXT_GPIO_EN_SNK1 BIT(4) +#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L BIT(3) enum glkrvp_charge_ports { TYPE_C_PORT_0, diff --git a/board/hammer/board.c b/board/hammer/board.c index 06f231e25a..8b3de4268c 100644 --- a/board/hammer/board.c +++ b/board/hammer/board.c @@ -224,7 +224,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_PWM - 1); void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ /* @@ -232,7 +232,7 @@ void board_config_pre_init(void) * Chan 4 : USART1_TX * Chan 5 : USART1_RX */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */ } int board_has_keyboard_backlight(void) diff --git a/board/hoho/board.c b/board/hoho/board.c index e6258f19b4..69ef58f59c 100644 --- a/board/hoho/board.c +++ b/board/hoho/board.c @@ -97,9 +97,9 @@ void hpd_event(enum gpio_signal signal) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ } #ifdef CONFIG_SPI_FLASH @@ -107,7 +107,7 @@ void board_config_pre_init(void) static void board_init_spi2(void) { /* Remap SPI2 to DMA channels 6 and 7 */ - STM32_SYSCFG_CFGR1 |= (1 << 24); + STM32_SYSCFG_CFGR1 |= BIT(24); /* Set pin NSS to general purpose output mode (01b). */ /* Set pins SCK, MISO, and MOSI to alternate function (10b). */ @@ -127,8 +127,8 @@ static void board_init_spi2(void) STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000; /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); /* Enable clocks to SPI2 module */ STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h index 33e7225131..309c2200f9 100644 --- a/board/hoho/usb_pd_config.h +++ b/board/hoho/usb_pd_config.h @@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) (1 << 21) +#define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ diff --git a/board/host/charger.c b/board/host/charger.c index 0ec8ab605c..29774359ef 100644 --- a/board/host/charger.c +++ b/board/host/charger.c @@ -24,7 +24,7 @@ static const struct charger_info mock_charger_info = { .input_current_step = 128, }; -#define OPTION_CHARGE_INHIBIT (1 << 0) +#define OPTION_CHARGE_INHIBIT BIT(0) static uint32_t mock_option; static uint32_t mock_mode; diff --git a/board/jerry/board.c b/board/jerry/board.c index 5c7eb8c41f..cbc3d21c16 100644 --- a/board/jerry/board.c +++ b/board/jerry/board.c @@ -48,7 +48,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ /* @@ -58,5 +58,5 @@ void board_config_pre_init(void) * Chan 4 : USART1_TX * Chan 5 : USART1_RX */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */ } diff --git a/board/kukui/board.c b/board/kukui/board.c index f0a32d1583..1c36b5d119 100644 --- a/board/kukui/board.c +++ b/board/kukui/board.c @@ -426,7 +426,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &g_bmi160_data, .port = I2C_PORT_ACCEL, .addr = BMI160_ADDR0, - .default_range = 1 << 11, /* 16LSB / uT, fixed */ + .default_range = BIT(11), /* 16LSB / uT, fixed */ .rot_standard_ref = &mag_standard_ref, .min_frequency = BMM150_MAG_MIN_FREQ, .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL), diff --git a/board/mchpevb1/board.c b/board/mchpevb1/board.c index eeeb557b96..79226d7d71 100644 --- a/board/mchpevb1/board.c +++ b/board/mchpevb1/board.c @@ -880,10 +880,10 @@ static void ds1624_update(void) DS1624_READ_TEMP16, &temp); d = (temp & 0x7FFF) >> 8; - if ((uint32_t)temp & (1 << 7)) + if ((uint32_t)temp & BIT(7)) d++; - if ((uint32_t)temp & (1 << 15)) + if ((uint32_t)temp & BIT(15)) d |= (1u << 31); ds1624_temp = (int32_t)d; diff --git a/board/nami/board.h b/board/nami/board.h index 157ea5554b..45e58d49bc 100644 --- a/board/nami/board.h +++ b/board/nami/board.h @@ -301,9 +301,9 @@ enum model_id { MODEL_BARD = 2, }; -#define SKU_ID_MASK_CONVERTIBLE (1 << 9) -#define SKU_ID_MASK_KEYPAD (1 << 15) -#define SKU_ID_MASK_UK2 (1 << 18) +#define SKU_ID_MASK_CONVERTIBLE BIT(9) +#define SKU_ID_MASK_KEYPAD BIT(15) +#define SKU_ID_MASK_UK2 BIT(18) /* TODO(crosbug.com/p/61098): Verify the numbers below. */ /* diff --git a/board/nami/led.c b/board/nami/led.c index a2866769c2..7f97d360e5 100644 --- a/board/nami/led.c +++ b/board/nami/led.c @@ -80,9 +80,9 @@ struct led_pattern { }; #define PULSE_NO 0 -#define PULSE(interval) (1 << 7 | (interval)) +#define PULSE(interval) (BIT(7) | (interval)) #define BLINK(interval) (interval) -#define ALTERNATE(interval) (1 << 6 | (interval)) +#define ALTERNATE(interval) (BIT(6) | (interval)) #define IS_PULSING(pulse) ((pulse) & 0x80) #define IS_ALTERNATE(pulse) ((pulse) & 0x40) #define PULSE_INTERVAL(pulse) (((pulse) & 0x3f) * 100 * MSEC) diff --git a/board/nautilus/board.c b/board/nautilus/board.c index 71f979401d..b87ff0ed37 100644 --- a/board/nautilus/board.c +++ b/board/nautilus/board.c @@ -288,7 +288,7 @@ static void board_report_pmic_fault(const char *str) != EC_SUCCESS) return; - if (!(vrfault & (1 << 4))) + if (!(vrfault & BIT(4))) return; /* VRFAULT has occurred, print VRFAULT status bits. */ @@ -304,7 +304,7 @@ static void board_report_pmic_fault(const char *str) pwrstat2); /* Clear all faults -- Write 1 to clear. */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4)); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4)); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2); diff --git a/board/nocturne/board.c b/board/nocturne/board.c index c2a13f7655..c3ac854a26 100644 --- a/board/nocturne/board.c +++ b/board/nocturne/board.c @@ -544,7 +544,7 @@ static void board_pmic_init(void) /* Mask V5A_DS3_PG from PMIC PGMASK1. */ if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x18, &pgmask1)) return; - pgmask1 |= (1 << 2); + pgmask1 |= BIT(2); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x18, pgmask1); board_pmic_disable_slp_s0_vr_decay(); @@ -645,7 +645,7 @@ static void board_report_pmic_fault(const char *str) != EC_SUCCESS) return; - if (!(vrfault & (1 << 4))) + if (!(vrfault & BIT(4))) return; /* VRFAULT has occurred, print VRFAULT status bits. */ @@ -661,7 +661,7 @@ static void board_report_pmic_fault(const char *str) pwrstat2); /* Clear all faults -- Write 1 to clear. */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4)); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4)); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2); @@ -799,7 +799,7 @@ uint16_t tcpc_get_alert_status(void) if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) { if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { /* The TCPCI spec says to ignore bits 14:12. */ - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + regval &= ~(BIT(14) | BIT(13) | BIT(12)); if (regval) status |= PD_STATUS_TCPC_ALERT_0; @@ -809,7 +809,7 @@ uint16_t tcpc_get_alert_status(void) if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec says to ignore bits 14:12. */ - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + regval &= ~(BIT(14) | BIT(13) | BIT(12)); if (regval) status |= PD_STATUS_TCPC_ALERT_1; diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h index 74855344e2..4ef1d3707d 100644 --- a/board/plankton/usb_pd_config.h +++ b/board/plankton/usb_pd_config.h @@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) (1 << 21) +#define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ diff --git a/board/poppy/board.c b/board/poppy/board.c index 3a158ef050..235389fc89 100644 --- a/board/poppy/board.c +++ b/board/poppy/board.c @@ -378,7 +378,7 @@ static void board_report_pmic_fault(const char *str) != EC_SUCCESS) return; - if (!(vrfault & (1 << 4))) + if (!(vrfault & BIT(4))) return; /* VRFAULT has occurred, print VRFAULT status bits. */ @@ -394,7 +394,7 @@ static void board_report_pmic_fault(const char *str) pwrstat2); /* Clear all faults -- Write 1 to clear. */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4)); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4)); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2); @@ -808,7 +808,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &g_bmi160_data, .port = I2C_PORT_GYRO, .addr = BMI160_ADDR0, - .default_range = 1 << 11, /* 16LSB / uT, fixed */ + .default_range = BIT(11), /* 16LSB / uT, fixed */ .rot_standard_ref = &mag_standard_ref, .min_frequency = BMM150_MAG_MIN_FREQ, .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL), diff --git a/board/rainier/board.c b/board/rainier/board.c index a8211560d7..1065bbf6ef 100644 --- a/board/rainier/board.c +++ b/board/rainier/board.c @@ -416,7 +416,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &bmp280_drv_data, .port = CONFIG_SPI_ACCEL_PORT, .addr = BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT), - .default_range = 1 << 18, /* 1bit = 4 Pa, 16bit ~= 2600 hPa */ + .default_range = BIT(18), /* 1bit = 4 Pa, 16bit ~= 2600 hPa */ .min_frequency = BMP280_BARO_MIN_FREQ, .max_frequency = BMP280_BARO_MAX_FREQ, }, diff --git a/board/rammus/board.c b/board/rammus/board.c index d4ec8ea13a..7497ac8aa5 100644 --- a/board/rammus/board.c +++ b/board/rammus/board.c @@ -312,7 +312,7 @@ static void board_report_pmic_fault(const char *str) != EC_SUCCESS) return; - if (!(vrfault & (1 << 4))) + if (!(vrfault & BIT(4))) return; /* VRFAULT has occurred, print VRFAULT status bits. */ @@ -328,7 +328,7 @@ static void board_report_pmic_fault(const char *str) pwrstat2); /* Clear all faults -- Write 1 to clear. */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4)); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4)); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2); diff --git a/board/reef/board.c b/board/reef/board.c index beeb5d823f..2579b103fc 100644 --- a/board/reef/board.c +++ b/board/reef/board.c @@ -803,7 +803,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &g_bmi160_data, .port = I2C_PORT_GYRO, .addr = BMI160_ADDR0, - .default_range = 1 << 11, /* 16LSB / uT, fixed */ + .default_range = BIT(11), /* 16LSB / uT, fixed */ .rot_standard_ref = &mag_standard_ref, .min_frequency = BMM150_MAG_MIN_FREQ, .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL), @@ -818,7 +818,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &bmp280_drv_data, .port = I2C_PORT_BARO, .addr = BMP280_I2C_ADDRESS1, - .default_range = 1 << 18, /* 1bit = 4 Pa, 16bit ~= 2600 hPa */ + .default_range = BIT(18), /* 1bit = 4 Pa, 16bit ~= 2600 hPa */ .min_frequency = BMP280_BARO_MIN_FREQ, .max_frequency = BMP280_BARO_MAX_FREQ, }, diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c index ecf938d179..7547b82167 100644 --- a/board/reef_mchp/board.c +++ b/board/reef_mchp/board.c @@ -1052,7 +1052,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &g_bmi160_data, .port = I2C_PORT_GYRO, .addr = BMI160_ADDR0, - .default_range = 1 << 11, /* 16LSB / uT, fixed */ + .default_range = BIT(11), /* 16LSB / uT, fixed */ .rot_standard_ref = &mag_standard_ref, .min_frequency = BMM150_MAG_MIN_FREQ, .max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL), @@ -1067,7 +1067,7 @@ struct motion_sensor_t motion_sensors[] = { .drv_data = &bmp280_drv_data, .port = I2C_PORT_BARO, .addr = BMP280_I2C_ADDRESS1, - .default_range = 1 << 18, /* 1bit = 4 Pa, 16bit ~= 2600 hPa */ + .default_range = BIT(18), /* 1bit = 4 Pa, 16bit ~= 2600 hPa */ .min_frequency = BMP280_BARO_MIN_FREQ, .max_frequency = BMP280_BARO_MAX_FREQ, }, diff --git a/board/samus/board.c b/board/samus/board.c index b8f66ca101..9f5bcf743a 100644 --- a/board/samus/board.c +++ b/board/samus/board.c @@ -87,7 +87,7 @@ const struct adc_t adc_channels[] = { * now. */ {"BatteryTemp", LM4_ADC_SEQ2, 1, 1, 0, - LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, (1<<4)}, + LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, BIT(4)}, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); diff --git a/board/samus/board.h b/board/samus/board.h index 59c3e8ca4d..ac76ff0d4c 100644 --- a/board/samus/board.h +++ b/board/samus/board.h @@ -202,8 +202,8 @@ void bkboost_det_interrupt(enum gpio_signal signal); void jtag_interrupt(enum gpio_signal signal); /* Bit masks for turning on PP5000 rail in G3 */ -#define PP5000_IN_G3_AC (1 << 0) -#define PP5000_IN_G3_LIGHTBAR (1 << 1) +#define PP5000_IN_G3_AC BIT(0) +#define PP5000_IN_G3_LIGHTBAR BIT(1) /* Enable/disable PP5000 rail mask in G3 */ void set_pp5000_in_g3(int mask, int enable); diff --git a/board/samus/panel.c b/board/samus/panel.c index 970197b9c8..961cb6fafe 100644 --- a/board/samus/panel.c +++ b/board/samus/panel.c @@ -35,7 +35,7 @@ #define LP8555_REG_CURRENT_MAXCURR_50MA 0x07 #define LP8555_REG_STEP 0x15 #define LP8555_REG_STEP_STEP_0MS (0 << 0) -#define LP8555_REG_STEP_STEP_8MS (1 << 0) +#define LP8555_REG_STEP_STEP_8MS BIT(0) #define LP8555_REG_STEP_STEP_16MS (2 << 0) #define LP8555_REG_STEP_STEP_24MS (3 << 0) #define LP8555_REG_STEP_STEP_28MS (4 << 0) @@ -43,7 +43,7 @@ #define LP8555_REG_STEP_STEP_100MS (6 << 0) #define LP8555_REG_STEP_STEP_200MS (7 << 0) #define LP8555_REG_STEP_PWM_IN_HYST_NONE (0 << 3) -#define LP8555_REG_STEP_PWM_IN_HYST_1LSB (1 << 3) +#define LP8555_REG_STEP_PWM_IN_HYST_1LSB BIT(3) #define LP8555_REG_STEP_PWM_IN_HYST_2LSB (2 << 3) #define LP8555_REG_STEP_PWM_IN_HYST_4LSB (3 << 3) #define LP8555_REG_STEP_PWM_IN_HYST_8LSB (4 << 3) @@ -51,7 +51,7 @@ #define LP8555_REG_STEP_PWM_IN_HYST_32LSB (6 << 3) #define LP8555_REG_STEP_PWM_IN_HYST_64LSB (7 << 3) #define LP8555_REG_STEP_SMOOTH_NONE (0 << 6) -#define LP8555_REG_STEP_SMOOTH_LIGHT (1 << 6) +#define LP8555_REG_STEP_SMOOTH_LIGHT BIT(6) #define LP8555_REG_STEP_SMOOTH_MEDIUM (2 << 6) #define LP8555_REG_STEP_SMOOTH_HEAVY (3 << 6) diff --git a/board/samus_pd/board.c b/board/samus_pd/board.c index 3087b9ce03..7691865476 100644 --- a/board/samus_pd/board.c +++ b/board/samus_pd/board.c @@ -181,7 +181,7 @@ void pch_evt(enum gpio_signal signal) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* * the DMA mapping is : * Chan 2 : TIM1_CH1 (C0 RX) @@ -196,7 +196,7 @@ void board_config_pre_init(void) * Remap USART1 RX/TX DMA to match uart driver. Remap SPI2 RX/TX and * TIM3_CH1 for unique DMA channels. */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) | (1 << 24) | (1 << 30); + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) | BIT(24) | BIT(30); } #include "gpio_list.h" diff --git a/board/samus_pd/usb_pd_config.h b/board/samus_pd/usb_pd_config.h index d303ae3a51..0f152a7362 100644 --- a/board/samus_pd/usb_pd_config.h +++ b/board/samus_pd/usb_pd_config.h @@ -64,7 +64,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0) #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0) #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) ((p) ? (1<<22) : (1 << 21)) +#define EXTI_COMP_MASK(p) ((p) ? BIT(22) : BIT(21)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -93,12 +93,12 @@ static inline void pd_tx_spi_reset(int port) { if (port == 0) { /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); } else { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } } diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c index db6d8b197a..e717d6207b 100644 --- a/board/servo_micro/board.c +++ b/board/servo_micro/board.c @@ -43,12 +43,12 @@ void board_config_pre_init(void) * i2c : no dma * tim16/17: no dma */ - STM32_SYSCFG_CFGR1 |= (1 << 26); /* Remap USART3 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */ /* Remap SPI2 to DMA channels 6 and 7 */ /* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */ /* but cros_ec hardcodes a 6/7 assumption in registers.h */ - STM32_SYSCFG_CFGR1 |= (1 << 24); + STM32_SYSCFG_CFGR1 |= BIT(24); } diff --git a/board/servo_v4/board.c b/board/servo_v4/board.c index 982ed9ccfb..6890027346 100644 --- a/board/servo_v4/board.c +++ b/board/servo_v4/board.c @@ -41,7 +41,7 @@ void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* * the DMA mapping is : @@ -60,13 +60,13 @@ void board_config_pre_init(void) * Reference Manual */ /* Remap USART1 Tx from DMA channel 2 to channel 4 */ - STM32_SYSCFG_CFGR1 |= (1 << 9); + STM32_SYSCFG_CFGR1 |= BIT(9); /* Remap USART1 Rx from DMA channel 3 to channel 5 */ - STM32_SYSCFG_CFGR1 |= (1 << 10); + STM32_SYSCFG_CFGR1 |= BIT(10); /* Remap TIM3_CH1 from DMA channel 4 to channel 6 */ - STM32_SYSCFG_CFGR1 |= (1 << 30); + STM32_SYSCFG_CFGR1 |= BIT(30); /* Remap SPI2 Tx from DMA channel 5 to channel 7 */ - STM32_SYSCFG_CFGR1 |= (1 << 24); + STM32_SYSCFG_CFGR1 |= BIT(24); } /****************************************************************************** diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h index 56c8d3aa02..41963a8360 100644 --- a/board/servo_v4/usb_pd_config.h +++ b/board/servo_v4/usb_pd_config.h @@ -83,7 +83,7 @@ static inline void spi_enable_clock(int port) * EXTI line 22 is connected to the CMP2 output, * CHG uses CMP2, and DUT uses CMP1. */ -#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22)) +#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -119,12 +119,12 @@ static inline void pd_tx_spi_reset(int port) { if (port == 0) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } else { /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); + STM32_RCC_APB1RSTR |= BIT(14); + STM32_RCC_APB1RSTR &= ~BIT(14); } } diff --git a/board/twinkie/board.c b/board/twinkie/board.c index 513d45d9a7..f15a55400c 100644 --- a/board/twinkie/board.c +++ b/board/twinkie/board.c @@ -34,10 +34,10 @@ void vbus_event(enum gpio_signal signal) void board_config_pre_init(void) { /* enable SYSCFG clock */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver and TIM2 DMA */ - STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) /* Remap USART1 RX/TX DMA */ - | (1 << 29);/* Remap TIM2 DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */ + | BIT(29);/* Remap TIM2 DMA */ /* 40 MHz pin speed on UART PA9/PA10 */ STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000; /* 40 MHz pin speed on TX clock out PB9 */ diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c index e2ee05daab..dc116d951a 100644 --- a/board/twinkie/simpletrace.c +++ b/board/twinkie/simpletrace.c @@ -223,7 +223,7 @@ void trace_packets(void) dma_disable(STM32_DMAC_CH7); task_disable_irq(STM32_IRQ_DMA_CHANNEL_4_7); /* remove TIM1 CH1/2/3 DMA remapping */ - STM32_SYSCFG_CFGR1 &= ~(1 << 28); + STM32_SYSCFG_CFGR1 &= ~BIT(28); #endif /* "classical" PD RX configuration */ diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c index dbdcbb68a7..e35b457ff7 100644 --- a/board/twinkie/sniffer.c +++ b/board/twinkie/sniffer.c @@ -256,7 +256,7 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx) void sniffer_init(void) { /* remap TIM1 CH1/2/3 to DMA channel 6 */ - STM32_SYSCFG_CFGR1 |= 1 << 28; + STM32_SYSCFG_CFGR1 |= BIT(28); /* TIM1 CH1 for CC1 RX */ rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1), @@ -266,7 +266,7 @@ void sniffer_init(void) TIM_RX2_CCR_IDX, 2); /* turn on COMP/SYSCFG */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED | STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP1OUTSEL_TIM1_IC1 | diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h index b125a2dfa9..1b2c22ba1a 100644 --- a/board/twinkie/usb_pd_config.h +++ b/board/twinkie/usb_pd_config.h @@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port) #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_CCR_CS 1 -#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22)) +#define EXTI_COMP_MASK(p) (BIT(21) | BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR @@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index c3cf2b5f4a..1d2ffb1eb3 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -17,12 +17,12 @@ static void system_init(void) { /* Enable access to RCC CSR register and RTC backup registers */ - STM32_PWR_CR |= 1 << 8; + STM32_PWR_CR |= BIT(8); /* switch on LSI */ - STM32_RCC_CSR |= 1 << 0; + STM32_RCC_CSR |= BIT(0); /* Wait for LSI to be ready */ - while (!(STM32_RCC_CSR & (1 << 1))) + while (!(STM32_RCC_CSR & BIT(1))) ; /* re-configure RTC if needed */ if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) { @@ -108,7 +108,7 @@ static void adc_init(void) ; } /* Single conversion, right aligned, 12-bit */ - STM32_ADC_CFGR1 = 1 << 12; /* (1 << 15) => AUTOOFF */; + STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */; /* clock is ADCCLK (ADEN must be off when writing this reg) */ STM32_ADC_CFGR2 = 0; /* Sampling time : 71.5 ADC clock cycles, about 5us */ @@ -172,9 +172,9 @@ void hardware_init(void) power_init(); /* Clear the hardware reset cause by setting the RMVF bit */ - STM32_RCC_CSR |= 1 << 24; + STM32_RCC_CSR |= BIT(24); /* Clear SBF in PWR_CSR */ - STM32_PWR_CR |= 1 << 3; + STM32_PWR_CR |= BIT(3); /* * WORKAROUND: as we cannot de-activate the watchdog during @@ -206,7 +206,7 @@ static int adc_enable_last_watchdog(void) static inline int adc_watchdog_enabled(void) { - return STM32_ADC_CFGR1 & (1 << 23); + return STM32_ADC_CFGR1 & BIT(23); } int adc_read_channel(enum adc_channel ch) @@ -222,9 +222,9 @@ int adc_read_channel(enum adc_channel ch) /* Clear flags */ STM32_ADC_ISR = 0x8e; /* Start conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ /* Wait for end of conversion */ - while (!(STM32_ADC_ISR & (1 << 2))) + while (!(STM32_ADC_ISR & BIT(2))) ; /* read converted value */ value = STM32_ADC_DR; @@ -249,12 +249,12 @@ int adc_enable_watchdog(int ch, int high, int low) /* Clear flags */ STM32_ADC_ISR = 0x8e; /* Set Watchdog enable bit on a single channel / continuous mode */ - STM32_ADC_CFGR1 = (ch << 26) | (1 << 23) | (1 << 22) - | (1 << 13) | (1 << 12); + STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22) + | BIT(13) | BIT(12); /* Enable watchdog interrupt */ - STM32_ADC_IER = 1 << 7; + STM32_ADC_IER = BIT(7); /* Start continuous conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ return EC_SUCCESS; } @@ -262,12 +262,12 @@ int adc_enable_watchdog(int ch, int high, int low) int adc_disable_watchdog(void) { /* Stop on-going conversion */ - STM32_ADC_CR |= 1 << 4; /* ADSTP */ + STM32_ADC_CR |= BIT(4); /* ADSTP */ /* Wait for conversion to stop */ - while (STM32_ADC_CR & (1 << 4)) + while (STM32_ADC_CR & BIT(4)) ; /* CONT=0 -> continuous mode off / Clear Watchdog enable */ - STM32_ADC_CFGR1 = 1 << 12; + STM32_ADC_CFGR1 = BIT(12); /* Disable interrupt */ STM32_ADC_IER = 0; /* Clear flags */ @@ -294,13 +294,13 @@ int adc_disable_watchdog(void) #define KEY2 0xCDEF89AB /* Lock bits for FLASH_CR register */ -#define PG (1<<0) -#define PER (1<<1) -#define OPTPG (1<<4) -#define OPTER (1<<5) -#define STRT (1<<6) -#define CR_LOCK (1<<7) -#define OPTWRE (1<<9) +#define PG BIT(0) +#define PER BIT(1) +#define OPTPG BIT(4) +#define OPTER BIT(5) +#define STRT BIT(6) +#define CR_LOCK BIT(7) +#define OPTWRE BIT(9) int flash_physical_write(int offset, int size, const char *data) { diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c index f92b919398..9e883888af 100644 --- a/board/zinger/runtime.c +++ b/board/zinger/runtime.c @@ -94,19 +94,19 @@ DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1); static void zinger_config_hispeed_clock(void) { /* Ensure that HSI8 is ON */ - if (!(STM32_RCC_CR & (1 << 1))) { + if (!(STM32_RCC_CR & BIT(1))) { /* Enable HSI */ - STM32_RCC_CR |= 1 << 0; + STM32_RCC_CR |= BIT(0); /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR & (1 << 1))) + while (!(STM32_RCC_CR & BIT(1))) ; } /* PLLSRC = HSI, PLLMUL = x12 (x HSI/2) = 48Mhz */ STM32_RCC_CFGR = 0x00288000; /* Enable PLL */ - STM32_RCC_CR |= 1 << 24; + STM32_RCC_CR |= BIT(24); /* Wait for PLL to be ready */ - while (!(STM32_RCC_CR & (1 << 25))) + while (!(STM32_RCC_CR & BIT(25))) ; /* switch SYSCLK to PLL */ diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h index fbe24e0003..2a7e0e7f7d 100644 --- a/board/zinger/usb_pd_config.h +++ b/board/zinger/usb_pd_config.h @@ -47,7 +47,7 @@ static inline void spi_enable_clock(int port) #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 /* connect TIM3 CH1 to TIM3_CH2 input */ #define TIM_CCR_CS 2 -#define EXTI_COMP_MASK(p) (1 << 7) +#define EXTI_COMP_MASK(p) BIT(7) #define IRQ_COMP STM32_IRQ_EXTI4_15 /* the RX is inverted, triggers on rising edge */ #define EXTI_XTSR STM32_EXTI_RTSR @@ -64,8 +64,8 @@ static inline void pd_set_pins_speed(int port) static inline void pd_tx_spi_reset(int port) { /* Reset SPI1 */ - STM32_RCC_APB2RSTR |= (1 << 12); - STM32_RCC_APB2RSTR &= ~(1 << 12); + STM32_RCC_APB2RSTR |= BIT(12); + STM32_RCC_APB2RSTR &= ~BIT(12); } /* Drive the CC line from the TX block */ @@ -81,7 +81,7 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { /* Put TX GND (PA4) in Hi-Z state */ - STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */; + STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */; /* Put SPI MISO (PA6) in Hi-Z by putting it in input mode */ STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6)); } diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c index c210ce9cea..07782c4f3b 100644 --- a/board/zinger/usb_pd_policy.c +++ b/board/zinger/usb_pd_policy.c @@ -70,7 +70,7 @@ static enum faults fault; static timestamp_t fault_deadline; /* ADC in 12-bit mode */ -#define ADC_SCALE (1 << 12) +#define ADC_SCALE BIT(12) /* ADC power supply : VDDA = 3.3V */ #define VDDA_MV 3300 /* Current sense resistor : 5 milliOhm */ diff --git a/chip/g/dcrypto/gcm.c b/chip/g/dcrypto/gcm.c index 18016de612..2caddf4741 100644 --- a/chip/g/dcrypto/gcm.c +++ b/chip/g/dcrypto/gcm.c @@ -46,7 +46,7 @@ static void gcm_init_iv( if (iv_len == 12) { memcpy(counter, iv, 12); - counter[3] = 1 << 24; + counter[3] = BIT(24); } else { size_t i; uint32_t len = iv_len; diff --git a/chip/g/gpio.c b/chip/g/gpio.c index 432608beea..79b40124d5 100644 --- a/chip/g/gpio.c +++ b/chip/g/gpio.c @@ -426,10 +426,10 @@ static void show_pinmux(const char *name, int i, int ofs) ccprintf("%08x: %s%-2d %2d %s%s%s%s ", GC_PINMUX_BASE_ADDR + i * 8 + ofs, name, i, sel, - (ctl & (1<<2)) ? " IN" : "", - (ctl & (1<<3)) ? " PD" : "", - (ctl & (1<<4)) ? " PU" : "", - (ctl & (1<<5)) ? " INV" : ""); + (ctl & BIT(2)) ? " IN" : "", + (ctl & BIT(3)) ? " PD" : "", + (ctl & BIT(4)) ? " PU" : "", + (ctl & BIT(5)) ? " INV" : ""); print_periph(sel); diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c index 55aca1e85a..745853cdc2 100644 --- a/chip/g/i2cs.c +++ b/chip/g/i2cs.c @@ -73,7 +73,7 @@ #include "task.h" #include "tpm_log.h" -#define REGISTER_FILE_SIZE (1 << 6) /* 64 bytes. */ +#define REGISTER_FILE_SIZE BIT(6) /* 64 bytes. */ #define REGISTER_FILE_MASK (REGISTER_FILE_SIZE - 1) /* Console output macros */ diff --git a/chip/g/idle.c b/chip/g/idle.c index e46351d2f5..1ed16de4a4 100644 --- a/chip/g/idle.c +++ b/chip/g/idle.c @@ -202,7 +202,7 @@ static void idle_init(void) * If bus obfuscation is enabled disable sleep. */ if ((GR_FUSE(OBFUSCATION_EN) == 5) || - (GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & (1 << 3)) || + (GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & BIT(3)) || (runlevel_is_high() && GREAD(GLOBALSEC, OBFS_SW_EN))) { CPRINTS("bus obfuscation enabled disabling sleep"); idle_default = IDLE_WFI; diff --git a/chip/g/ite_flash.c b/chip/g/ite_flash.c index b805e09e6a..b4e1699a08 100644 --- a/chip/g/ite_flash.c +++ b/chip/g/ite_flash.c @@ -47,8 +47,8 @@ void generate_ite_sync(void) * 1 to be able to generate two necessary waveforms. */ both_zero = 0; - one_zero = 1 << 13; - zero_one = 1 << 12; + one_zero = BIT(13); + zero_one = BIT(12); both_one = one_zero | zero_one; /* Address of the mask byte register to use to set both pins. */ diff --git a/chip/g/pmu.c b/chip/g/pmu.c index 47b8341d5a..a324e6cee7 100644 --- a/chip/g/pmu.c +++ b/chip/g/pmu.c @@ -10,7 +10,7 @@ * RC Trim constants */ #define RCTRIM_RESOLUTION (12) -#define RCTRIM_LOAD_VAL (1 << 11) +#define RCTRIM_LOAD_VAL BIT(11) #define RCTRIM_RANGE_MAX (7 * 7) #define RCTRIM_RANGE_MIN (-8 * 7) #define RCTRIM_RANGE (RCTRIM_RANGE_MAX - RCTRIM_RANGE_MIN + 1) diff --git a/chip/g/registers.h b/chip/g/registers.h index 9c16df7f62..9127802db3 100644 --- a/chip/g/registers.h +++ b/chip/g/registers.h @@ -387,7 +387,7 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, */ #define GP_OUT(v) (GC_USB_GGPIO_GPO_MASK & ((v) << GC_USB_GGPIO_GPO_LSB)) #define GP_IN(v) (GC_USB_GGPIO_GPI_MASK & ((v) << GC_USB_GGPIO_GPI_LSB)) -#define GGPIO_WRITE(reg, val) GP_OUT(((1 << 15) | /* write bit */ \ +#define GGPIO_WRITE(reg, val) GP_OUT((BIT(15) | /* write bit */ \ (((val) & 0xFF) << 4) | /* value */ \ ((reg) & 0x0F))) /* register */ #define GGPIO_READ(reg) GP_OUT((reg) & 0x0F) /* register */ @@ -399,14 +399,14 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define USB_SEL_PHY0 0x00 /* bit 0 */ #define USB_SEL_PHY1 0x01 /* bit 0 */ #define USB_IDLE_PHY_CTRL_REG 1 /* register number */ -#define USB_FS_SUSPENDB (1 << 7) -#define USB_FS_EDGE_SEL (1 << 6) -#define USB_DM_PULLUP_EN (1 << 5) -#define USB_DP_RPU2_ENB (1 << 4) -#define USB_DP_RPU1_ENB (1 << 3) -#define USB_TX_OEB (1 << 2) -#define USB_TX_DPO (1 << 1) -#define USB_TX_DMO (1 << 0) +#define USB_FS_SUSPENDB BIT(7) +#define USB_FS_EDGE_SEL BIT(6) +#define USB_DM_PULLUP_EN BIT(5) +#define USB_DP_RPU2_ENB BIT(4) +#define USB_DP_RPU1_ENB BIT(3) +#define USB_TX_OEB BIT(2) +#define USB_TX_DPO BIT(1) +#define USB_TX_DMO BIT(0) #define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) #define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB) @@ -515,8 +515,8 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB) #define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) #define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) -#define DXEPCTL_SET_D0PID (1 << 28) -#define DXEPCTL_SET_D1PID (1 << 29) +#define DXEPCTL_SET_D0PID BIT(28) +#define DXEPCTL_SET_D1PID BIT(29) #define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) #define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) @@ -528,12 +528,12 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DOEPDMA_BS_HOST_BSY (3 << 30) #define DOEPDMA_BS_MASK (3 << 30) #define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST (1 << 27) -#define DOEPDMA_SP (1 << 26) -#define DOEPDMA_IOC (1 << 25) -#define DOEPDMA_SR (1 << 24) -#define DOEPDMA_MTRF (1 << 23) -#define DOEPDMA_NAK (1 << 16) +#define DOEPDMA_LAST BIT(27) +#define DOEPDMA_SP BIT(26) +#define DOEPDMA_IOC BIT(25) +#define DOEPDMA_SR BIT(24) +#define DOEPDMA_MTRF BIT(23) +#define DOEPDMA_NAK BIT(16) #define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) #define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) @@ -543,9 +543,9 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DIEPDMA_BS_HOST_BSY (3 << 30) #define DIEPDMA_BS_MASK (3 << 30) #define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST (1 << 27) -#define DIEPDMA_SP (1 << 26) -#define DIEPDMA_IOC (1 << 25) +#define DIEPDMA_LAST BIT(27) +#define DIEPDMA_SP BIT(26) +#define DIEPDMA_IOC BIT(25) #define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) #define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) diff --git a/chip/g/signed_header.h b/chip/g/signed_header.h index 3ee4085a14..6096350a54 100644 --- a/chip/g/signed_header.h +++ b/chip/g/signed_header.h @@ -100,7 +100,7 @@ BUILD_ASSERT(offsetof(struct SignedHeader, info_chk_) == 1020); * * This convention is enforced at the key generation time. */ -#define G_SIGNED_FOR_PROD(h) ((h)->keyid & (1 << 2)) +#define G_SIGNED_FOR_PROD(h) ((h)->keyid & BIT(2)) #endif /* __CROS_EC_SIGNED_HEADER_H */ diff --git a/chip/g/sps.h b/chip/g/sps.h index b9684c4b90..5e95042a7e 100644 --- a/chip/g/sps.h +++ b/chip/g/sps.h @@ -19,7 +19,7 @@ enum sps_mode { }; /* Receive and transmit FIFO size and mask. */ -#define SPS_FIFO_SIZE (1 << 10) +#define SPS_FIFO_SIZE BIT(10) #define SPS_FIFO_MASK (SPS_FIFO_SIZE - 1) /* diff --git a/chip/g/usb_spi.h b/chip/g/usb_spi.h index 72364ab469..cedfe78485 100644 --- a/chip/g/usb_spi.h +++ b/chip/g/usb_spi.h @@ -77,9 +77,9 @@ enum usb_spi_request { /* USB SPI device bitmasks */ enum usb_spi { USB_SPI_DISABLE = 0, - USB_SPI_AP = (1 << 0), - USB_SPI_EC = (1 << 1), - USB_SPI_H1 = (1 << 2), + USB_SPI_AP = BIT(0), + USB_SPI_EC = BIT(1), + USB_SPI_H1 = BIT(2), USB_SPI_ALL = USB_SPI_AP | USB_SPI_EC | USB_SPI_H1 }; diff --git a/chip/host/host_test.h b/chip/host/host_test.h index 6eac0bc62e..1161b36ee7 100644 --- a/chip/host/host_test.h +++ b/chip/host/host_test.h @@ -9,7 +9,7 @@ #define __CROS_EC_HOST_TEST_H /* Emulator exit codes */ -#define EXIT_CODE_HIBERNATE (1 << 7) +#define EXIT_CODE_HIBERNATE BIT(7) /* Get emulator executable name */ const char *__get_prog_name(void); diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c index 11435841c4..45e5f39fbd 100644 --- a/chip/ish/host_command_heci.c +++ b/chip/ish/host_command_heci.c @@ -114,7 +114,7 @@ static int heci_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = HECI_CROS_EC_LIMIT_PACKET_SIZE; r->max_response_packet_size = HECI_CROS_EC_RESPONSE_MAX; diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h index 463d3b38a6..ee26162518 100644 --- a/chip/ish/hpet.h +++ b/chip/ish/hpet.h @@ -48,9 +48,9 @@ * Use this register to see HPET timer are settled after a write. */ #define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) -#define HPET_T1_CMP_SETTLING (1 << 8) -#define HPET_T1_CAP_SETTLING (1 << 5) -#define HPET_MAIN_COUNTER_SETTLING (1 << 2) +#define HPET_T1_CMP_SETTLING BIT(8) +#define HPET_T1_CAP_SETTLING BIT(5) +#define HPET_MAIN_COUNTER_SETTLING BIT(2) #define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | \ HPET_T1_CMP_SETTLING) diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index 9574f38799..b7c471e802 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -58,25 +58,25 @@ #define MNG_ILLEGAL_CMD 0xFF /* Peripheral Interrupt Satus Register */ -#define IPC_PISR_HOST2ISH_BIT (1<<0) -#define IPC_PISR_PMC2ISH_BIT (1<<1) -#define IPC_PISR_CSME2ISH_BIT (1<<2) +#define IPC_PISR_HOST2ISH_BIT BIT(0) +#define IPC_PISR_PMC2ISH_BIT BIT(1) +#define IPC_PISR_CSME2ISH_BIT BIT(2) /* Peripheral Interrupt Mask Register */ -#define IPC_PIMR_HOST2ISH_BIT (1<<0) -#define IPC_PIMR_PMC2ISH_BIT (1<<1) -#define IPC_PIMR_CSME2ISH_BIT (1<<2) +#define IPC_PIMR_HOST2ISH_BIT BIT(0) +#define IPC_PIMR_PMC2ISH_BIT BIT(1) +#define IPC_PIMR_CSME2ISH_BIT BIT(2) -#define IPC_PIMR_ISH2HOST_CLR_BIT (1<<11) -#define IPC_PIMR_ISH2PMC_CLR_BIT (1<<12) -#define IPC_PIMR_ISH2CSME_CLR_BIT (1<<13) +#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) +#define IPC_PIMR_ISH2PMC_CLR_BIT BIT(12) +#define IPC_PIMR_ISH2CSME_CLR_BIT BIT(13) /* Peripheral Interrupt DB(DoorBell) Clear Status Register */ -#define IPC_DB_CLR_STS_ISH2HOST_BIT (1<<0) -#define IPC_DB_CLR_STS_ISH2ISP_BIT (1<<2) -#define IPC_DB_CLR_STS_ISH2AUDIO_BIT (1<<3) -#define IPC_DB_CLR_STS_ISH2PMC_BIT (1<<8) -#define IPC_DB_CLR_STS_ISH2CSME_BIT (1<<16) +#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) +#define IPC_DB_CLR_STS_ISH2ISP_BIT BIT(2) +#define IPC_DB_CLR_STS_ISH2AUDIO_BIT BIT(3) +#define IPC_DB_CLR_STS_ISH2PMC_BIT BIT(8) +#define IPC_DB_CLR_STS_ISH2CSME_BIT BIT(16) /* Doorbell */ #define IPC_DB_MSG_LENGTH_FIELD 0x3FF diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h index d981b545ae..2b88524fda 100644 --- a/chip/ish/ish_i2c.h +++ b/chip/ish/ish_i2c.h @@ -154,11 +154,11 @@ enum { TX_BUFFER_DEPTH_OFFSET = 16, RX_BUFFER_DEPTH_OFFSET = 8, /* IC_INTR_MASK VALUES */ - M_RX_FULL = (1 << 2), - M_TX_EMPTY = (1 << 4), - M_TX_ABRT = (1 << 6), - M_STOP_DET = (1 << 9), - M_START_DET = (1 << 10), + M_RX_FULL = BIT(2), + M_TX_EMPTY = BIT(4), + M_TX_ABRT = BIT(6), + M_STOP_DET = BIT(9), + M_START_DET = BIT(10), IC_INTR_WRITE_MASK_VAL = (M_STOP_DET | M_TX_ABRT), IC_INTR_READ_MASK_VAL = (M_RX_FULL | M_TX_ABRT), DISABLE_INT = 0, diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 63c16fcdb8..9106463356 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -122,15 +122,15 @@ enum ish_i2c_port { /* PMU Registers */ #define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) -#define VNN_REQ_IPC_HOST_WRITE (1 << 3) /* Power for IPC host write */ +#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ #define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) -#define PMU_VNN_REQ_ACK_STATUS (1 << 0) /* VNN req and ack status */ +#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ #define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) -#define PMU_RST_PREP_GET (1 << 0) -#define PMU_RST_PREP_AVAIL (1 << 1) -#define PMU_RST_PREP_INT_MASK (1 << 31) +#define PMU_RST_PREP_GET BIT(0) +#define PMU_RST_PREP_AVAIL BIT(1) +#define PMU_RST_PREP_INT_MASK BIT(31) /* CCU Registers */ #define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) @@ -163,7 +163,7 @@ enum ish_i2c_port { #define LAPIC_ISR_REG 0xFEE00170 #define LAPIC_IRR_REG (ISH_LAPIC_BASE + 0x200) #define LAPIC_ESR_REG (ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL (1 << 6) +#define LAPIC_ERR_RECV_ILLEGAL BIT(6) #define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300) #endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index 11ea17cb82..86c6748f06 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -150,20 +150,20 @@ /* UART config flag, send to sc_io_control if the current UART line has HW * flow control lines connected. */ -#define UART_CONFIG_HW_FLOW_CONTROL (1<<0) +#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is * raised only when the rx buffer is completely full. Otherwise, the event * is raised after a timeout is received on the UART line, * and all data received until now is provided. */ -#define UART_CONFIG_DELIVER_FULL_RX_BUF (1<<1) +#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted * is raised when all rx buffers that were added are full. Otherwise, no * event is raised. */ -#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF (1<<2) +#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) #define UART_INT_DEVICES 2 #define UART_EXT_DEVICES 8 diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 6b8361dbdb..71f92c44e9 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -222,8 +222,8 @@ static void adc_init(void) * NOTE: A sample time delay (60us) also need to be included in * conversion time, so the final result is ~= 121.6us. */ - IT83XX_ADC_ADCSTS &= ~(1 << 7); - IT83XX_ADC_ADCCFG &= ~(1 << 5); + IT83XX_ADC_ADCSTS &= ~BIT(7); + IT83XX_ADC_ADCCFG &= ~BIT(5); IT83XX_ADC_ADCCTL = 1; task_waiting = TASK_ID_INVALID; diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 75c4e1dbeb..fde5045389 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -62,11 +62,11 @@ struct clock_gate_ctrl { static void clock_module_disable(void) { /* bit0: FSPI interface tri-state */ - IT83XX_SMFI_FLHCTRL3R |= (1 << 0); + IT83XX_SMFI_FLHCTRL3R |= BIT(0); /* bit7: USB pad power-on disable */ - IT83XX_GCTRL_PMER2 &= ~(1 << 7); + IT83XX_GCTRL_PMER2 &= ~BIT(7); /* bit7: USB debug disable */ - IT83XX_GCTRL_MCCR &= ~(1 << 7); + IT83XX_GCTRL_MCCR &= ~BIT(7); clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0); clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB | CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE | @@ -146,7 +146,7 @@ void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode) void __ram_code clock_pll_changed(void) { - IT83XX_GCTRL_SSCR &= ~(1 << 0); + IT83XX_GCTRL_SSCR &= ~BIT(0); /* * Update PLL settings. * Writing data to this register doesn't change the @@ -199,7 +199,7 @@ static void clock_set_pll(enum pll_freq_idx idx) * We have to set chip select pin as input mode in order to * change PLL. */ - IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7); + IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7); #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED /* * On DX version, we have to disable eSPI pad before changing @@ -281,10 +281,10 @@ void clock_init(void) clock_module_disable(); #ifdef CONFIG_HOSTCMD_X86 - IT83XX_WUC_WUESR4 = (1 << 2); + IT83XX_WUC_WUESR4 = BIT(2); task_clear_pending_irq(IT83XX_IRQ_WKINTAD); /* bit2, wake-up enable for LPC access */ - IT83XX_WUC_WUENR4 |= (1 << 2); + IT83XX_WUC_WUENR4 |= BIT(2); #endif } @@ -349,7 +349,7 @@ void clock_refresh_console_in_use(void) static void clock_event_timer_clock_change(enum ext_timer_clock_source clock, uint32_t count) { - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0); + IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock; IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count; IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3; @@ -370,7 +370,7 @@ static void clock_htimer_enable(void) static int clock_allow_low_power_idle(void) { - if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0))) + if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0))) return 0; if (*et_ctrl_regs[EVENT_EXT_TIMER].isr & @@ -412,7 +412,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) chip_clear_pending_irq(i); } /* bit5: watchdog is disabled. */ - IT83XX_ETWD_ETWCTRL |= (1 << 5); + IT83XX_ETWD_ETWCTRL |= BIT(5); /* Setup GPIOs for hibernate */ if (board_hibernate_late) board_hibernate_late(); @@ -501,7 +501,7 @@ defined(CONFIG_HOSTCMD_ESPI) #ifdef CONFIG_HOSTCMD_X86 /* disable lpc access wui */ task_disable_irq(IT83XX_IRQ_WKINTAD); - IT83XX_WUC_WUESR4 = (1 << 2); + IT83XX_WUC_WUESR4 = BIT(2); task_clear_pending_irq(IT83XX_IRQ_WKINTAD); #endif /* disable uart wui */ @@ -534,7 +534,7 @@ void __idle(void) /* Check if the EC can enter deep doze mode or not */ if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) { /* reset low power mode hw timer */ - IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1); sleep_mode_t0 = get_time(); #ifdef CONFIG_HOSTCMD_X86 /* enable lpc access wui */ diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c index 38216592ad..2cdcb43f8a 100644 --- a/chip/it83xx/ec2i.c +++ b/chip/it83xx/ec2i.c @@ -160,9 +160,9 @@ enum ec2i_access { enum ec2i_status_mask { /* 1: EC read-access is still processing. */ - EC2I_STATUS_CRIB = (1 << 1), + EC2I_STATUS_CRIB = BIT(1), /* 1: EC write-access is still processing with IHD register. */ - EC2I_STATUS_CWIB = (1 << 2), + EC2I_STATUS_CWIB = BIT(2), EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB), }; @@ -179,7 +179,7 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data) int rv = EC_ERROR_UNKNOWN; /* bit1 : VCC power on */ - if (IT83XX_SWUC_SWCTL1 & (1 << 1)) { + if (IT83XX_SWUC_SWCTL1 & BIT(1)) { /* * Wait that both CRIB and CWIB bits in IBCTL register * are cleared. @@ -191,15 +191,15 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data) /* Write the data to IHD register */ IT83XX_EC2I_IHD = data; /* Enable EC access to the PNPCFG registers */ - IT83XX_EC2I_IBMAE |= (1 << 0); + IT83XX_EC2I_IBMAE |= BIT(0); /* bit0: EC to I-Bus access enabled. */ - IT83XX_EC2I_IBCTL |= (1 << 0); + IT83XX_EC2I_IBCTL |= BIT(0); /* Wait the CWIB bit in IBCTL cleared. */ rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB); /* Disable EC access to the PNPCFG registers. */ - IT83XX_EC2I_IBMAE &= ~(1 << 0); + IT83XX_EC2I_IBMAE &= ~BIT(0); /* Disable EC to I-Bus access. */ - IT83XX_EC2I_IBCTL &= ~(1 << 0); + IT83XX_EC2I_IBCTL &= ~BIT(0); } } @@ -212,7 +212,7 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel) uint8_t ihd = 0; /* bit1 : VCC power on */ - if (IT83XX_SWUC_SWCTL1 & (1 << 1)) { + if (IT83XX_SWUC_SWCTL1 & BIT(1)) { /* * Wait that both CRIB and CWIB bits in IBCTL register * are cleared. @@ -222,19 +222,19 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel) /* Set indirect host I/O offset. */ IT83XX_EC2I_IHIOA = sel; /* Enable EC access to the PNPCFG registers */ - IT83XX_EC2I_IBMAE |= (1 << 0); + IT83XX_EC2I_IBMAE |= BIT(0); /* bit1: a read-action */ - IT83XX_EC2I_IBCTL |= (1 << 1); + IT83XX_EC2I_IBCTL |= BIT(1); /* bit0: EC to I-Bus access enabled. */ - IT83XX_EC2I_IBCTL |= (1 << 0); + IT83XX_EC2I_IBCTL |= BIT(0); /* Wait the CRIB bit in IBCTL cleared. */ rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB); /* Read the data from IHD register */ ihd = IT83XX_EC2I_IHD; /* Disable EC access to the PNPCFG registers. */ - IT83XX_EC2I_IBMAE &= ~(1 << 0); + IT83XX_EC2I_IBMAE &= ~BIT(0); /* Disable EC to I-Bus access. */ - IT83XX_EC2I_IBCTL &= ~(1 << 0); + IT83XX_EC2I_IBCTL &= ~BIT(0); } } diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index 21e462596b..9e68eedf00 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -431,7 +431,7 @@ void __ram_code espi_fw_reset_module(void) * 01b: The VCC power status is treated as power-on. */ IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0); - IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | (1 << 6); + IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6); } #endif @@ -457,9 +457,9 @@ static int espi_get_reset_enable_config(void) * 10b: espi_reset# is enabled on GPD2. * 11b: reset is disabled. */ - if (espi_rst->port == GPIO_D && espi_rst->mask == (1 << 2)) { + if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) { config = IT83XX_GPIO_GCR_LPC_RST_D2; - } else if (espi_rst->port == GPIO_B && espi_rst->mask == (1 << 7)) { + } else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) { config = IT83XX_GPIO_GCR_LPC_RST_B7; } else { config = IT83XX_GPIO_GCR_LPC_RST_DISABLE; @@ -575,10 +575,10 @@ void espi_enable_pad(int enable) { if (enable) /* Enable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6); + IT83XX_ESPI_ESGCTRL2 &= ~BIT(6); else /* Disable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 |= (1 << 6); + IT83XX_ESPI_ESGCTRL2 |= BIT(6); } #endif @@ -593,7 +593,7 @@ void espi_init(void) * 100b: 66MHz */ #ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE - IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | (1 << 2); + IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2); #endif /* reset vw_index_flag at initialization */ espi_reset_vw_index_flags(); @@ -602,16 +602,16 @@ void espi_init(void) * bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH * register and WRST#. */ - IT83XX_GCTRL_RSTS &= ~(1 << 3); + IT83XX_GCTRL_RSTS &= ~BIT(3); task_clear_pending_irq(IT83XX_IRQ_ESPI_VW); /* bit7: VW interrupt enable */ - IT83XX_ESPI_VWCTRL0 |= (1 << 7); + IT83XX_ESPI_VWCTRL0 |= BIT(7); task_enable_irq(IT83XX_IRQ_ESPI_VW); /* bit7: eSPI interrupt enable */ - IT83XX_ESPI_ESGCTRL1 |= (1 << 7); + IT83XX_ESPI_ESGCTRL1 |= BIT(7); /* bit4: eSPI to WUC enable */ - IT83XX_ESPI_ESGCTRL2 |= (1 << 4); + IT83XX_ESPI_ESGCTRL2 |= BIT(4); task_enable_irq(IT83XX_IRQ_ESPI); /* enable interrupt and reset from eSPI_reset# */ diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index f89f791f11..5c390553ef 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -100,111 +100,111 @@ static const struct { uint8_t wuc_mask; } gpio_irqs[] = { /* irq gpio_port,gpio_mask,wuc_group,wuc_mask */ - [IT83XX_IRQ_WKO20] = {GPIO_D, (1<<0), 2, (1<<0)}, - [IT83XX_IRQ_WKO21] = {GPIO_D, (1<<1), 2, (1<<1)}, - [IT83XX_IRQ_WKO22] = {GPIO_C, (1<<4), 2, (1<<2)}, - [IT83XX_IRQ_WKO23] = {GPIO_C, (1<<6), 2, (1<<3)}, - [IT83XX_IRQ_WKO24] = {GPIO_D, (1<<2), 2, (1<<4)}, + [IT83XX_IRQ_WKO20] = {GPIO_D, BIT(0), 2, BIT(0)}, + [IT83XX_IRQ_WKO21] = {GPIO_D, BIT(1), 2, BIT(1)}, + [IT83XX_IRQ_WKO22] = {GPIO_C, BIT(4), 2, BIT(2)}, + [IT83XX_IRQ_WKO23] = {GPIO_C, BIT(6), 2, BIT(3)}, + [IT83XX_IRQ_WKO24] = {GPIO_D, BIT(2), 2, BIT(4)}, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO40] = {GPIO_E, (1<<5), 4, (1<<0)}, - [IT83XX_IRQ_WKO45] = {GPIO_E, (1<<6), 4, (1<<5)}, - [IT83XX_IRQ_WKO46] = {GPIO_E, (1<<7), 4, (1<<6)}, + [IT83XX_IRQ_WKO40] = {GPIO_E, BIT(5), 4, BIT(0)}, + [IT83XX_IRQ_WKO45] = {GPIO_E, BIT(6), 4, BIT(5)}, + [IT83XX_IRQ_WKO46] = {GPIO_E, BIT(7), 4, BIT(6)}, #endif - [IT83XX_IRQ_WKO50] = {GPIO_K, (1<<0), 5, (1<<0)}, - [IT83XX_IRQ_WKO51] = {GPIO_K, (1<<1), 5, (1<<1)}, - [IT83XX_IRQ_WKO52] = {GPIO_K, (1<<2), 5, (1<<2)}, - [IT83XX_IRQ_WKO53] = {GPIO_K, (1<<3), 5, (1<<3)}, - [IT83XX_IRQ_WKO54] = {GPIO_K, (1<<4), 5, (1<<4)}, - [IT83XX_IRQ_WKO55] = {GPIO_K, (1<<5), 5, (1<<5)}, - [IT83XX_IRQ_WKO56] = {GPIO_K, (1<<6), 5, (1<<6)}, - [IT83XX_IRQ_WKO57] = {GPIO_K, (1<<7), 5, (1<<7)}, - [IT83XX_IRQ_WKO60] = {GPIO_H, (1<<0), 6, (1<<0)}, - [IT83XX_IRQ_WKO61] = {GPIO_H, (1<<1), 6, (1<<1)}, - [IT83XX_IRQ_WKO62] = {GPIO_H, (1<<2), 6, (1<<2)}, - [IT83XX_IRQ_WKO63] = {GPIO_H, (1<<3), 6, (1<<3)}, - [IT83XX_IRQ_WKO64] = {GPIO_F, (1<<4), 6, (1<<4)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, (1<<5), 6, (1<<5)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, (1<<6), 6, (1<<6)}, - [IT83XX_IRQ_WKO67] = {GPIO_F, (1<<7), 6, (1<<7)}, - [IT83XX_IRQ_WKO70] = {GPIO_E, (1<<0), 7, (1<<0)}, - [IT83XX_IRQ_WKO71] = {GPIO_E, (1<<1), 7, (1<<1)}, - [IT83XX_IRQ_WKO72] = {GPIO_E, (1<<2), 7, (1<<2)}, - [IT83XX_IRQ_WKO73] = {GPIO_E, (1<<3), 7, (1<<3)}, - [IT83XX_IRQ_WKO74] = {GPIO_I, (1<<4), 7, (1<<4)}, - [IT83XX_IRQ_WKO75] = {GPIO_I, (1<<5), 7, (1<<5)}, - [IT83XX_IRQ_WKO76] = {GPIO_I, (1<<6), 7, (1<<6)}, - [IT83XX_IRQ_WKO77] = {GPIO_I, (1<<7), 7, (1<<7)}, - [IT83XX_IRQ_WKO80] = {GPIO_A, (1<<3), 8, (1<<0)}, - [IT83XX_IRQ_WKO81] = {GPIO_A, (1<<4), 8, (1<<1)}, - [IT83XX_IRQ_WKO82] = {GPIO_A, (1<<5), 8, (1<<2)}, - [IT83XX_IRQ_WKO83] = {GPIO_A, (1<<6), 8, (1<<3)}, - [IT83XX_IRQ_WKO84] = {GPIO_B, (1<<2), 8, (1<<4)}, - [IT83XX_IRQ_WKO85] = {GPIO_C, (1<<0), 8, (1<<5)}, - [IT83XX_IRQ_WKO86] = {GPIO_C, (1<<7), 8, (1<<6)}, - [IT83XX_IRQ_WKO87] = {GPIO_D, (1<<7), 8, (1<<7)}, - [IT83XX_IRQ_WKO88] = {GPIO_H, (1<<4), 9, (1<<0)}, - [IT83XX_IRQ_WKO89] = {GPIO_H, (1<<5), 9, (1<<1)}, - [IT83XX_IRQ_WKO90] = {GPIO_H, (1<<6), 9, (1<<2)}, - [IT83XX_IRQ_WKO91] = {GPIO_A, (1<<0), 9, (1<<3)}, - [IT83XX_IRQ_WKO92] = {GPIO_A, (1<<1), 9, (1<<4)}, - [IT83XX_IRQ_WKO93] = {GPIO_A, (1<<2), 9, (1<<5)}, - [IT83XX_IRQ_WKO94] = {GPIO_B, (1<<4), 9, (1<<6)}, - [IT83XX_IRQ_WKO95] = {GPIO_C, (1<<2), 9, (1<<7)}, - [IT83XX_IRQ_WKO96] = {GPIO_F, (1<<0), 10, (1<<0)}, - [IT83XX_IRQ_WKO97] = {GPIO_F, (1<<1), 10, (1<<1)}, - [IT83XX_IRQ_WKO98] = {GPIO_F, (1<<2), 10, (1<<2)}, - [IT83XX_IRQ_WKO99] = {GPIO_F, (1<<3), 10, (1<<3)}, - [IT83XX_IRQ_WKO100] = {GPIO_A, (1<<7), 10, (1<<4)}, - [IT83XX_IRQ_WKO101] = {GPIO_B, (1<<0), 10, (1<<5)}, - [IT83XX_IRQ_WKO102] = {GPIO_B, (1<<1), 10, (1<<6)}, - [IT83XX_IRQ_WKO103] = {GPIO_B, (1<<3), 10, (1<<7)}, - [IT83XX_IRQ_WKO104] = {GPIO_B, (1<<5), 11, (1<<0)}, - [IT83XX_IRQ_WKO105] = {GPIO_B, (1<<6), 11, (1<<1)}, - [IT83XX_IRQ_WKO106] = {GPIO_B, (1<<7), 11, (1<<2)}, - [IT83XX_IRQ_WKO107] = {GPIO_C, (1<<1), 11, (1<<3)}, - [IT83XX_IRQ_WKO108] = {GPIO_C, (1<<3), 11, (1<<4)}, - [IT83XX_IRQ_WKO109] = {GPIO_C, (1<<5), 11, (1<<5)}, - [IT83XX_IRQ_WKO110] = {GPIO_D, (1<<3), 11, (1<<6)}, - [IT83XX_IRQ_WKO111] = {GPIO_D, (1<<4), 11, (1<<7)}, - [IT83XX_IRQ_WKO112] = {GPIO_D, (1<<5), 12, (1<<0)}, - [IT83XX_IRQ_WKO113] = {GPIO_D, (1<<6), 12, (1<<1)}, - [IT83XX_IRQ_WKO114] = {GPIO_E, (1<<4), 12, (1<<2)}, - [IT83XX_IRQ_WKO115] = {GPIO_G, (1<<0), 12, (1<<3)}, - [IT83XX_IRQ_WKO116] = {GPIO_G, (1<<1), 12, (1<<4)}, - [IT83XX_IRQ_WKO117] = {GPIO_G, (1<<2), 12, (1<<5)}, - [IT83XX_IRQ_WKO118] = {GPIO_G, (1<<6), 12, (1<<6)}, - [IT83XX_IRQ_WKO119] = {GPIO_I, (1<<0), 12, (1<<7)}, - [IT83XX_IRQ_WKO120] = {GPIO_I, (1<<1), 13, (1<<0)}, - [IT83XX_IRQ_WKO121] = {GPIO_I, (1<<2), 13, (1<<1)}, - [IT83XX_IRQ_WKO122] = {GPIO_I, (1<<3), 13, (1<<2)}, + [IT83XX_IRQ_WKO50] = {GPIO_K, BIT(0), 5, BIT(0)}, + [IT83XX_IRQ_WKO51] = {GPIO_K, BIT(1), 5, BIT(1)}, + [IT83XX_IRQ_WKO52] = {GPIO_K, BIT(2), 5, BIT(2)}, + [IT83XX_IRQ_WKO53] = {GPIO_K, BIT(3), 5, BIT(3)}, + [IT83XX_IRQ_WKO54] = {GPIO_K, BIT(4), 5, BIT(4)}, + [IT83XX_IRQ_WKO55] = {GPIO_K, BIT(5), 5, BIT(5)}, + [IT83XX_IRQ_WKO56] = {GPIO_K, BIT(6), 5, BIT(6)}, + [IT83XX_IRQ_WKO57] = {GPIO_K, BIT(7), 5, BIT(7)}, + [IT83XX_IRQ_WKO60] = {GPIO_H, BIT(0), 6, BIT(0)}, + [IT83XX_IRQ_WKO61] = {GPIO_H, BIT(1), 6, BIT(1)}, + [IT83XX_IRQ_WKO62] = {GPIO_H, BIT(2), 6, BIT(2)}, + [IT83XX_IRQ_WKO63] = {GPIO_H, BIT(3), 6, BIT(3)}, + [IT83XX_IRQ_WKO64] = {GPIO_F, BIT(4), 6, BIT(4)}, + [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(5), 6, BIT(5)}, + [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(6), 6, BIT(6)}, + [IT83XX_IRQ_WKO67] = {GPIO_F, BIT(7), 6, BIT(7)}, + [IT83XX_IRQ_WKO70] = {GPIO_E, BIT(0), 7, BIT(0)}, + [IT83XX_IRQ_WKO71] = {GPIO_E, BIT(1), 7, BIT(1)}, + [IT83XX_IRQ_WKO72] = {GPIO_E, BIT(2), 7, BIT(2)}, + [IT83XX_IRQ_WKO73] = {GPIO_E, BIT(3), 7, BIT(3)}, + [IT83XX_IRQ_WKO74] = {GPIO_I, BIT(4), 7, BIT(4)}, + [IT83XX_IRQ_WKO75] = {GPIO_I, BIT(5), 7, BIT(5)}, + [IT83XX_IRQ_WKO76] = {GPIO_I, BIT(6), 7, BIT(6)}, + [IT83XX_IRQ_WKO77] = {GPIO_I, BIT(7), 7, BIT(7)}, + [IT83XX_IRQ_WKO80] = {GPIO_A, BIT(3), 8, BIT(0)}, + [IT83XX_IRQ_WKO81] = {GPIO_A, BIT(4), 8, BIT(1)}, + [IT83XX_IRQ_WKO82] = {GPIO_A, BIT(5), 8, BIT(2)}, + [IT83XX_IRQ_WKO83] = {GPIO_A, BIT(6), 8, BIT(3)}, + [IT83XX_IRQ_WKO84] = {GPIO_B, BIT(2), 8, BIT(4)}, + [IT83XX_IRQ_WKO85] = {GPIO_C, BIT(0), 8, BIT(5)}, + [IT83XX_IRQ_WKO86] = {GPIO_C, BIT(7), 8, BIT(6)}, + [IT83XX_IRQ_WKO87] = {GPIO_D, BIT(7), 8, BIT(7)}, + [IT83XX_IRQ_WKO88] = {GPIO_H, BIT(4), 9, BIT(0)}, + [IT83XX_IRQ_WKO89] = {GPIO_H, BIT(5), 9, BIT(1)}, + [IT83XX_IRQ_WKO90] = {GPIO_H, BIT(6), 9, BIT(2)}, + [IT83XX_IRQ_WKO91] = {GPIO_A, BIT(0), 9, BIT(3)}, + [IT83XX_IRQ_WKO92] = {GPIO_A, BIT(1), 9, BIT(4)}, + [IT83XX_IRQ_WKO93] = {GPIO_A, BIT(2), 9, BIT(5)}, + [IT83XX_IRQ_WKO94] = {GPIO_B, BIT(4), 9, BIT(6)}, + [IT83XX_IRQ_WKO95] = {GPIO_C, BIT(2), 9, BIT(7)}, + [IT83XX_IRQ_WKO96] = {GPIO_F, BIT(0), 10, BIT(0)}, + [IT83XX_IRQ_WKO97] = {GPIO_F, BIT(1), 10, BIT(1)}, + [IT83XX_IRQ_WKO98] = {GPIO_F, BIT(2), 10, BIT(2)}, + [IT83XX_IRQ_WKO99] = {GPIO_F, BIT(3), 10, BIT(3)}, + [IT83XX_IRQ_WKO100] = {GPIO_A, BIT(7), 10, BIT(4)}, + [IT83XX_IRQ_WKO101] = {GPIO_B, BIT(0), 10, BIT(5)}, + [IT83XX_IRQ_WKO102] = {GPIO_B, BIT(1), 10, BIT(6)}, + [IT83XX_IRQ_WKO103] = {GPIO_B, BIT(3), 10, BIT(7)}, + [IT83XX_IRQ_WKO104] = {GPIO_B, BIT(5), 11, BIT(0)}, + [IT83XX_IRQ_WKO105] = {GPIO_B, BIT(6), 11, BIT(1)}, + [IT83XX_IRQ_WKO106] = {GPIO_B, BIT(7), 11, BIT(2)}, + [IT83XX_IRQ_WKO107] = {GPIO_C, BIT(1), 11, BIT(3)}, + [IT83XX_IRQ_WKO108] = {GPIO_C, BIT(3), 11, BIT(4)}, + [IT83XX_IRQ_WKO109] = {GPIO_C, BIT(5), 11, BIT(5)}, + [IT83XX_IRQ_WKO110] = {GPIO_D, BIT(3), 11, BIT(6)}, + [IT83XX_IRQ_WKO111] = {GPIO_D, BIT(4), 11, BIT(7)}, + [IT83XX_IRQ_WKO112] = {GPIO_D, BIT(5), 12, BIT(0)}, + [IT83XX_IRQ_WKO113] = {GPIO_D, BIT(6), 12, BIT(1)}, + [IT83XX_IRQ_WKO114] = {GPIO_E, BIT(4), 12, BIT(2)}, + [IT83XX_IRQ_WKO115] = {GPIO_G, BIT(0), 12, BIT(3)}, + [IT83XX_IRQ_WKO116] = {GPIO_G, BIT(1), 12, BIT(4)}, + [IT83XX_IRQ_WKO117] = {GPIO_G, BIT(2), 12, BIT(5)}, + [IT83XX_IRQ_WKO118] = {GPIO_G, BIT(6), 12, BIT(6)}, + [IT83XX_IRQ_WKO119] = {GPIO_I, BIT(0), 12, BIT(7)}, + [IT83XX_IRQ_WKO120] = {GPIO_I, BIT(1), 13, BIT(0)}, + [IT83XX_IRQ_WKO121] = {GPIO_I, BIT(2), 13, BIT(1)}, + [IT83XX_IRQ_WKO122] = {GPIO_I, BIT(3), 13, BIT(2)}, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO123] = {GPIO_G, (1<<3), 13, (1<<3)}, - [IT83XX_IRQ_WKO124] = {GPIO_G, (1<<4), 13, (1<<4)}, - [IT83XX_IRQ_WKO125] = {GPIO_G, (1<<5), 13, (1<<5)}, - [IT83XX_IRQ_WKO126] = {GPIO_G, (1<<7), 13, (1<<6)}, + [IT83XX_IRQ_WKO123] = {GPIO_G, BIT(3), 13, BIT(3)}, + [IT83XX_IRQ_WKO124] = {GPIO_G, BIT(4), 13, BIT(4)}, + [IT83XX_IRQ_WKO125] = {GPIO_G, BIT(5), 13, BIT(5)}, + [IT83XX_IRQ_WKO126] = {GPIO_G, BIT(7), 13, BIT(6)}, #endif - [IT83XX_IRQ_WKO128] = {GPIO_J, (1<<0), 14, (1<<0)}, - [IT83XX_IRQ_WKO129] = {GPIO_J, (1<<1), 14, (1<<1)}, - [IT83XX_IRQ_WKO130] = {GPIO_J, (1<<2), 14, (1<<2)}, - [IT83XX_IRQ_WKO131] = {GPIO_J, (1<<3), 14, (1<<3)}, - [IT83XX_IRQ_WKO132] = {GPIO_J, (1<<4), 14, (1<<4)}, - [IT83XX_IRQ_WKO133] = {GPIO_J, (1<<5), 14, (1<<5)}, - [IT83XX_IRQ_WKO136] = {GPIO_L, (1<<0), 15, (1<<0)}, - [IT83XX_IRQ_WKO137] = {GPIO_L, (1<<1), 15, (1<<1)}, - [IT83XX_IRQ_WKO138] = {GPIO_L, (1<<2), 15, (1<<2)}, - [IT83XX_IRQ_WKO139] = {GPIO_L, (1<<3), 15, (1<<3)}, - [IT83XX_IRQ_WKO140] = {GPIO_L, (1<<4), 15, (1<<4)}, - [IT83XX_IRQ_WKO141] = {GPIO_L, (1<<5), 15, (1<<5)}, - [IT83XX_IRQ_WKO142] = {GPIO_L, (1<<6), 15, (1<<6)}, - [IT83XX_IRQ_WKO143] = {GPIO_L, (1<<7), 15, (1<<7)}, + [IT83XX_IRQ_WKO128] = {GPIO_J, BIT(0), 14, BIT(0)}, + [IT83XX_IRQ_WKO129] = {GPIO_J, BIT(1), 14, BIT(1)}, + [IT83XX_IRQ_WKO130] = {GPIO_J, BIT(2), 14, BIT(2)}, + [IT83XX_IRQ_WKO131] = {GPIO_J, BIT(3), 14, BIT(3)}, + [IT83XX_IRQ_WKO132] = {GPIO_J, BIT(4), 14, BIT(4)}, + [IT83XX_IRQ_WKO133] = {GPIO_J, BIT(5), 14, BIT(5)}, + [IT83XX_IRQ_WKO136] = {GPIO_L, BIT(0), 15, BIT(0)}, + [IT83XX_IRQ_WKO137] = {GPIO_L, BIT(1), 15, BIT(1)}, + [IT83XX_IRQ_WKO138] = {GPIO_L, BIT(2), 15, BIT(2)}, + [IT83XX_IRQ_WKO139] = {GPIO_L, BIT(3), 15, BIT(3)}, + [IT83XX_IRQ_WKO140] = {GPIO_L, BIT(4), 15, BIT(4)}, + [IT83XX_IRQ_WKO141] = {GPIO_L, BIT(5), 15, BIT(5)}, + [IT83XX_IRQ_WKO142] = {GPIO_L, BIT(6), 15, BIT(6)}, + [IT83XX_IRQ_WKO143] = {GPIO_L, BIT(7), 15, BIT(7)}, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO144] = {GPIO_M, (1<<0), 16, (1<<0)}, - [IT83XX_IRQ_WKO145] = {GPIO_M, (1<<1), 16, (1<<1)}, - [IT83XX_IRQ_WKO146] = {GPIO_M, (1<<2), 16, (1<<2)}, - [IT83XX_IRQ_WKO147] = {GPIO_M, (1<<3), 16, (1<<3)}, - [IT83XX_IRQ_WKO148] = {GPIO_M, (1<<4), 16, (1<<4)}, - [IT83XX_IRQ_WKO149] = {GPIO_M, (1<<5), 16, (1<<5)}, - [IT83XX_IRQ_WKO150] = {GPIO_M, (1<<6), 16, (1<<6)}, + [IT83XX_IRQ_WKO144] = {GPIO_M, BIT(0), 16, BIT(0)}, + [IT83XX_IRQ_WKO145] = {GPIO_M, BIT(1), 16, BIT(1)}, + [IT83XX_IRQ_WKO146] = {GPIO_M, BIT(2), 16, BIT(2)}, + [IT83XX_IRQ_WKO147] = {GPIO_M, BIT(3), 16, BIT(3)}, + [IT83XX_IRQ_WKO148] = {GPIO_M, BIT(4), 16, BIT(4)}, + [IT83XX_IRQ_WKO149] = {GPIO_M, BIT(5), 16, BIT(5)}, + [IT83XX_IRQ_WKO150] = {GPIO_M, BIT(6), 16, BIT(6)}, #endif [IT83XX_IRQ_COUNT-1] = {0, 0, 0, 0}, }; @@ -238,119 +238,119 @@ struct gpio_1p8v_t { static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = { #ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC24, (1 << 1)}, - [6] = {&IT83XX_GPIO_GRC24, (1 << 5)}, - [7] = {&IT83XX_GPIO_GRC24, (1 << 6)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC22, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC19, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC19, (1 << 6)}, - [7] = {&IT83XX_GPIO_GRC24, (1 << 4)} }, - [GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, (1 << 7)}, - [1] = {&IT83XX_GPIO_GRC19, (1 << 5)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 4)}, - [4] = {&IT83XX_GPIO_GRC24, (1 << 2)}, - [6] = {&IT83XX_GPIO_GRC24, (1 << 3)}, - [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC19, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 0)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 7)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 6)}, - [5] = {&IT83XX_GPIO_GRC22, (1 << 4)}, - [6] = {&IT83XX_GPIO_GRC22, (1 << 5)}, - [7] = {&IT83XX_GPIO_GRC22, (1 << 6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)}, - [1] = {&IT83XX_GPIO_GCR28, (1 << 6)}, - [2] = {&IT83XX_GPIO_GCR28, (1 << 7)}, - [4] = {&IT83XX_GPIO_GRC22, (1 << 2)}, - [5] = {&IT83XX_GPIO_GRC22, (1 << 3)}, - [6] = {&IT83XX_GPIO_GRC20, (1 << 4)}, - [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} }, - [GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 4)}, - [1] = {&IT83XX_GPIO_GCR28, (1 << 5)}, - [2] = {&IT83XX_GPIO_GRC20, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC21, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC21, (1 << 6)}, - [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} }, - [GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC21, (1 << 4)}, - [2] = {&IT83XX_GPIO_GCR28, (1 << 3)}, - [6] = {&IT83XX_GPIO_GRC21, (1 << 3)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC21, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC21, (1 << 0)}, - [5] = {&IT83XX_GPIO_GCR27, (1 << 7)}, - [6] = {&IT83XX_GPIO_GCR28, (1 << 0)} }, - [GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, (1 << 3)}, - [1] = {&IT83XX_GPIO_GRC23, (1 << 4)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 5)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 6)}, - [4] = {&IT83XX_GPIO_GRC23, (1 << 7)}, - [5] = {&IT83XX_GPIO_GCR27, (1 << 4)}, - [6] = {&IT83XX_GPIO_GCR27, (1 << 5)}, - [7] = {&IT83XX_GPIO_GCR27, (1 << 6)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)}, - [1] = {&IT83XX_GPIO_GRC23, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 3)}, - [4] = {&IT83XX_GPIO_GCR27, (1 << 0)}, - [5] = {&IT83XX_GPIO_GCR27, (1 << 1)}, - [6] = {&IT83XX_GPIO_GCR27, (1 << 2)} }, - [GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, (1 << 0)}, - [1] = {&IT83XX_GPIO_GCR26, (1 << 1)}, - [2] = {&IT83XX_GPIO_GCR26, (1 << 2)}, - [3] = {&IT83XX_GPIO_GCR26, (1 << 3)}, - [4] = {&IT83XX_GPIO_GCR26, (1 << 4)}, - [5] = {&IT83XX_GPIO_GCR26, (1 << 5)}, - [6] = {&IT83XX_GPIO_GCR26, (1 << 6)}, - [7] = {&IT83XX_GPIO_GCR26, (1 << 7)} }, - [GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, (1 << 0)}, - [1] = {&IT83XX_GPIO_GCR25, (1 << 1)}, - [2] = {&IT83XX_GPIO_GCR25, (1 << 2)}, - [3] = {&IT83XX_GPIO_GCR25, (1 << 3)}, - [4] = {&IT83XX_GPIO_GCR25, (1 << 4)}, - [5] = {&IT83XX_GPIO_GCR25, (1 << 5)}, - [6] = {&IT83XX_GPIO_GCR25, (1 << 6)}, - [7] = {&IT83XX_GPIO_GCR25, (1 << 7)} }, + [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC24, BIT(1)}, + [6] = {&IT83XX_GPIO_GRC24, BIT(5)}, + [7] = {&IT83XX_GPIO_GRC24, BIT(6)} }, + [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC19, BIT(6)}, + [7] = {&IT83XX_GPIO_GRC24, BIT(4)} }, + [GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)}, + [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, + [4] = {&IT83XX_GPIO_GRC24, BIT(2)}, + [6] = {&IT83XX_GPIO_GRC24, BIT(3)}, + [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, + [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(6)}, + [5] = {&IT83XX_GPIO_GRC22, BIT(4)}, + [6] = {&IT83XX_GPIO_GRC22, BIT(5)}, + [7] = {&IT83XX_GPIO_GRC22, BIT(6)} }, + [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, + [1] = {&IT83XX_GPIO_GCR28, BIT(6)}, + [2] = {&IT83XX_GPIO_GCR28, BIT(7)}, + [4] = {&IT83XX_GPIO_GRC22, BIT(2)}, + [5] = {&IT83XX_GPIO_GRC22, BIT(3)}, + [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, + [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, + [GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)}, + [1] = {&IT83XX_GPIO_GCR28, BIT(5)}, + [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, + [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, + [GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC21, BIT(4)}, + [2] = {&IT83XX_GPIO_GCR28, BIT(3)}, + [6] = {&IT83XX_GPIO_GRC21, BIT(3)} }, + [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC21, BIT(0)}, + [5] = {&IT83XX_GPIO_GCR27, BIT(7)}, + [6] = {&IT83XX_GPIO_GCR28, BIT(0)} }, + [GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)}, + [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, + [4] = {&IT83XX_GPIO_GRC23, BIT(7)}, + [5] = {&IT83XX_GPIO_GCR27, BIT(4)}, + [6] = {&IT83XX_GPIO_GCR27, BIT(5)}, + [7] = {&IT83XX_GPIO_GCR27, BIT(6)} }, + [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, + [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(3)}, + [4] = {&IT83XX_GPIO_GCR27, BIT(0)}, + [5] = {&IT83XX_GPIO_GCR27, BIT(1)}, + [6] = {&IT83XX_GPIO_GCR27, BIT(2)} }, + [GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)}, + [1] = {&IT83XX_GPIO_GCR26, BIT(1)}, + [2] = {&IT83XX_GPIO_GCR26, BIT(2)}, + [3] = {&IT83XX_GPIO_GCR26, BIT(3)}, + [4] = {&IT83XX_GPIO_GCR26, BIT(4)}, + [5] = {&IT83XX_GPIO_GCR26, BIT(5)}, + [6] = {&IT83XX_GPIO_GCR26, BIT(6)}, + [7] = {&IT83XX_GPIO_GCR26, BIT(7)} }, + [GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)}, + [1] = {&IT83XX_GPIO_GCR25, BIT(1)}, + [2] = {&IT83XX_GPIO_GCR25, BIT(2)}, + [3] = {&IT83XX_GPIO_GCR25, BIT(3)}, + [4] = {&IT83XX_GPIO_GCR25, BIT(4)}, + [5] = {&IT83XX_GPIO_GCR25, BIT(5)}, + [6] = {&IT83XX_GPIO_GCR25, BIT(6)}, + [7] = {&IT83XX_GPIO_GCR25, BIT(7)} }, #else - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC24, (1 << 1)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC22, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC19, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC19, (1 << 6)} }, - [GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, (1 << 5)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 4)}, - [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC19, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 0)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 7)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)}, - [6] = {&IT83XX_GPIO_GRC20, (1 << 4)}, - [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} }, - [GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC21, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC21, (1 << 6)}, - [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC21, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC21, (1 << 0)} }, - [GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, (1 << 4)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 5)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 6)}, - [4] = {&IT83XX_GPIO_GRC23, (1 << 7)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)}, - [1] = {&IT83XX_GPIO_GRC23, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 3)} }, + [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC24, BIT(1)} }, + [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC19, BIT(6)} }, + [GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, + [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, + [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(6)} }, + [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, + [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, + [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, + [GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, + [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, + [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC21, BIT(0)} }, + [GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, + [4] = {&IT83XX_GPIO_GRC23, BIT(7)} }, + [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, + [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(3)} }, #endif }; diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c index e65fea38fa..ecfbcf7be6 100644 --- a/chip/it83xx/hwtimer.c +++ b/chip/it83xx/hwtimer.c @@ -81,7 +81,7 @@ static void free_run_timer_overflow(void) /* set timer counter register */ IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff; /* bit[1], timer reset */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1); } /* w/c interrupt status */ task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq); @@ -114,14 +114,14 @@ void __hw_clock_source_set(uint32_t ts) /* counting down timer, microseconds to timer counter register */ IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts; /* bit[1], timer reset */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1); } void __hw_clock_event_set(uint32_t deadline) { uint32_t wait; /* bit0, disable event timer */ - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0); + IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); /* w/c interrupt status */ event_timer_clear_pending_isr(); /* microseconds to timer counter */ @@ -139,7 +139,7 @@ uint32_t __hw_clock_event_get(void) uint32_t next_event_us = __hw_clock_source_read(); /* bit0, event timer is enabled */ - if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)) { + if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) { /* timer counter observation value to microseconds */ next_event_us += EVENT_TIMER_COUNT_TO_US( #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES @@ -161,7 +161,7 @@ void __hw_clock_event_clear(void) int __hw_clock_source_init(uint32_t start_t) { /* bit3, timer 3 and timer 4 combinational mode */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 3); + IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3); /* init free running timer (timer 4, TIMER_H), clock source is 8mhz */ ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1); /* 1us counter setting (timer 3, TIMER_L) */ @@ -181,7 +181,7 @@ static void __hw_clock_source_irq(void) /* SW/HW interrupt of event timer. */ if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) { IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff; - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1); event_timer_clear_pending_isr(); process_timers(0); return; diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c index a88599b380..56f805b9f6 100644 --- a/chip/it83xx/i2c.c +++ b/chip/it83xx/i2c.c @@ -292,7 +292,7 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct, if (first_byte) { /* First byte must be slave address. */ IT83XX_I2C_DTR(p_ch) = - data | (direct == RX_DIRECT ? (1 << 0) : 0); + data | (direct == RX_DIRECT ? BIT(0) : 0); /* start or repeat start signal. */ IT83XX_I2C_CTR(p_ch) = E_START_ID; } else { @@ -457,7 +457,7 @@ static void enhanced_i2c_start(int p) */ IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT; /* bit1: Enable enhanced i2c module */ - IT83XX_I2C_CTR1(p_ch) = (1 << 1); + IT83XX_I2C_CTR1(p_ch) = BIT(1); } static int enhanced_i2c_tran_write(int p) diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c index 9c5d1028ae..d6d01e1247 100644 --- a/chip/it83xx/keyboard_raw.c +++ b/chip/it83xx/keyboard_raw.c @@ -31,7 +31,7 @@ void keyboard_raw_init(void) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* KSO[2] is high, others are low. */ - IT83XX_KBS_KSOL = (1 << 2); + IT83XX_KBS_KSOL = BIT(2); #else /* KSO[7:0] pins low. */ IT83XX_KBS_KSOL = 0x00; @@ -81,7 +81,7 @@ test_mockable void keyboard_raw_drive_column(int col) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* KSO[2] is inverted. */ - mask ^= (1 << 2); + mask ^= BIT(2); #endif IT83XX_KBS_KSOL = mask & 0xff; IT83XX_KBS_KSOH1 = (mask >> 8) & 0xff; diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index 5765788718..5ca7cf91b9 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -103,7 +103,7 @@ static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out) static void pm_clear_ibf(enum lpc_pm_ch ch) { /* bit7, write-1 clear IBF */ - IT83XX_PMC_PMIE(ch) |= (1 << 7); + IT83XX_PMC_PMIE(ch) |= BIT(7); } #ifdef CONFIG_KEYBOARD_IRQ_GPIO @@ -340,8 +340,8 @@ void lpc_keyboard_clear_buffer(void) uint32_t int_mask = get_int_mask(); interrupt_disable(); /* bit6, write-1 clear OBF */ - IT83XX_KBC_KBHICR |= (1 << 6); - IT83XX_KBC_KBHICR &= ~(1 << 6); + IT83XX_KBC_KBHICR |= BIT(6); + IT83XX_KBC_KBHICR &= ~BIT(6); set_int_mask(int_mask); } @@ -392,8 +392,8 @@ void lpc_kbc_ibf_interrupt(void) keyboard_host_write(IT83XX_KBC_KBHIDIR, (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0); /* bit7, write-1 clear IBF */ - IT83XX_KBC_KBHICR |= (1 << 7); - IT83XX_KBC_KBHICR &= ~(1 << 7); + IT83XX_KBC_KBHICR |= BIT(7); + IT83XX_KBC_KBHICR &= ~BIT(7); } task_clear_pending_irq(IT83XX_IRQ_KBC_IN); @@ -745,7 +745,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 8d2d8016bb..6414ec9d16 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1179,26 +1179,26 @@ enum i2c_channels { #define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port))) #define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0) -#define USBPD_REG_MASK_SW_RESET_BIT (1 << 7) -#define USBPD_REG_MASK_TYPE_C_DETECT_RESET (1 << 6) -#define USBPD_REG_MASK_BMC_PHY (1 << 4) -#define USBPD_REG_MASK_AUTO_SEND_SW_RESET (1 << 3) -#define USBPD_REG_MASK_AUTO_SEND_HW_RESET (1 << 2) -#define USBPD_REG_MASK_SNIFFER_MODE (1 << 1) -#define USBPD_REG_MASK_GLOBAL_ENABLE (1 << 0) +#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) +#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6) +#define USBPD_REG_MASK_BMC_PHY BIT(4) +#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3) +#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2) +#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) +#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0) #define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p)+0x01) -#define USBPD_REG_MASK_SOPPP_ENABLE (1 << 7) -#define USBPD_REG_MASK_SOPP_ENABLE (1 << 6) -#define USBPD_REG_MASK_SOP_ENABLE (1 << 5) +#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7) +#define USBPD_REG_MASK_SOPP_ENABLE BIT(6) +#define USBPD_REG_MASK_SOP_ENABLE BIT(5) #define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04) -#define USBPD_REG_MASK_DISABLE_CC (1 << 4) +#define USBPD_REG_MASK_DISABLE_CC BIT(4) #define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05) #ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT -#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT ((1 << 3) | (1 << 1)) -#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT ((1 << 7) | (1 << 5)) +#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (BIT(3) | BIT(1)) +#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (BIT(7) | BIT(5)) #else -#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (1 << 3) -#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (1 << 7) +#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT BIT(3) +#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT BIT(7) #endif #define USBPD_CC1_DISCONNECTED(p) \ ((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \ @@ -1208,35 +1208,35 @@ enum i2c_channels { ~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) #define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 (1 << 5) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 (1 << 1) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) #define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x08) #define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x09) #define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0C) #define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p)+0x14) -#define USBPD_REG_MASK_TYPE_C_DETECT (1 << 7) -#define USBPD_REG_MASK_CABLE_RESET_DETECT (1 << 6) -#define USBPD_REG_MASK_HARD_RESET_DETECT (1 << 5) -#define USBPD_REG_MASK_MSG_RX_DONE (1 << 4) -#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE (1 << 3) -#define USBPD_REG_MASK_HARD_RESET_TX_DONE (1 << 2) -#define USBPD_REG_MASK_MSG_TX_DONE (1 << 1) -#define USBPD_REG_MASK_TIMER_TIMEOUT (1 << 0) +#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7) +#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) +#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) +#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) +#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3) +#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(2) +#define USBPD_REG_MASK_MSG_TX_DONE BIT(1) +#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0) #define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15) #define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p)+0x18) -#define USBPD_REG_MASK_SW_RESET_TX_STAT (1 << 3) -#define USBPD_REG_MASK_TX_BUSY_STAT (1 << 2) -#define USBPD_REG_MASK_TX_DISCARD_STAT (1 << 2) -#define USBPD_REG_MASK_TX_ERR_STAT (1 << 1) -#define USBPD_REG_MASK_TX_START (1 << 0) +#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3) +#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2) +#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2) +#define USBPD_REG_MASK_TX_ERR_STAT BIT(1) +#define USBPD_REG_MASK_TX_START BIT(0) #define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x19) -#define USBPD_REG_MASK_CABLE_ENABLE (1 << 7) -#define USBPD_REG_MASK_SEND_HW_RESET (1 << 6) -#define USBPD_REG_MASK_SEND_BIST_MODE_2 (1 << 5) +#define USBPD_REG_MASK_CABLE_ENABLE BIT(7) +#define USBPD_REG_MASK_SEND_HW_RESET BIT(6) +#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5) #define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1A) #define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1B) #define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1C) -#define USBPD_REG_MASK_RX_MSG_VALID (1 << 0) +#define USBPD_REG_MASK_RX_MSG_VALID BIT(0) #define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p)+0x1D) #define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p)+0x1E) #define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p)+0x1F) @@ -1252,11 +1252,11 @@ enum i2c_channels { #define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p)+0x65) #ifdef IT83XX_INTC_PLUG_IN_SUPPORT #define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p)+0x67) -#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT (1 << 7) -#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR (1 << 4) -#define USBPD_REG_PLUG_IN_OUT_SELECT (1 << 3) -#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE (1 << 1) -#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT (1 << 0) +#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) +#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4) +#define USBPD_REG_PLUG_IN_OUT_SELECT BIT(3) +#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) +#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) #endif //IT83XX_INTC_PLUG_IN_SUPPORT enum usbpd_port { @@ -1283,55 +1283,55 @@ enum usbpd_port { #define VW_VALID_FIELD(f) ((f) << 4) #define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2 -#define VW_IDX_2_SLP_S3 (1 << 0) -#define VW_IDX_2_SLP_S4 (1 << 1) -#define VW_IDX_2_SLP_S5 (1 << 2) +#define VW_IDX_2_SLP_S3 BIT(0) +#define VW_IDX_2_SLP_S4 BIT(1) +#define VW_IDX_2_SLP_S5 BIT(2) #define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3 -#define VW_IDX_3_SUS_STAT (1 << 0) -#define VW_IDX_3_PLTRST (1 << 1) -#define VW_IDX_3_OOB_RST_WARN (1 << 2) +#define VW_IDX_3_SUS_STAT BIT(0) +#define VW_IDX_3_PLTRST BIT(1) +#define VW_IDX_3_OOB_RST_WARN BIT(2) #define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4 -#define VW_IDX_4_OOB_RST_ACK (1 << 0) -#define VW_IDX_4_WAKE (1 << 2) -#define VW_IDX_4_PME (1 << 3) +#define VW_IDX_4_OOB_RST_ACK BIT(0) +#define VW_IDX_4_WAKE BIT(2) +#define VW_IDX_4_PME BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5 -#define VW_IDX_5_SLAVE_BTLD_DONE (1 << 0) -#define VW_IDX_5_FATAL (1 << 1) -#define VW_IDX_5_NON_FATAL (1 << 2) -#define VW_IDX_5_SLAVE_BTLD_STATUS (1 << 3) +#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0) +#define VW_IDX_5_FATAL BIT(1) +#define VW_IDX_5_NON_FATAL BIT(2) +#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3) #define VW_IDX_5_BTLD_STATUS_DONE (VW_IDX_5_SLAVE_BTLD_DONE | \ VW_IDX_5_SLAVE_BTLD_STATUS) #define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6 -#define VW_IDX_6_SCI (1 << 0) -#define VW_IDX_6_SMI (1 << 1) -#define VW_IDX_6_RCIN (1 << 2) -#define VW_IDX_6_HOST_RST_ACK (1 << 3) +#define VW_IDX_6_SCI BIT(0) +#define VW_IDX_6_SMI BIT(1) +#define VW_IDX_6_RCIN BIT(2) +#define VW_IDX_6_HOST_RST_ACK BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7 -#define VW_IDX_7_HOST_RST_WARN (1 << 0) +#define VW_IDX_7_HOST_RST_WARN BIT(0) #define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40 -#define VW_IDX_40_SUS_ACK (1 << 0) +#define VW_IDX_40_SUS_ACK BIT(0) #define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41 -#define VW_IDX_41_SUS_WARN (1 << 0) -#define VW_IDX_41_SUS_PWRDN_ACK (1 << 1) -#define VW_IDX_41_SLP_A (1 << 3) +#define VW_IDX_41_SUS_WARN BIT(0) +#define VW_IDX_41_SUS_PWRDN_ACK BIT(1) +#define VW_IDX_41_SLP_A BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42 -#define VW_IDX_42_SLP_LAN (1 << 0) -#define VW_IDX_42_SLP_WLAN (1 << 1) +#define VW_IDX_42_SLP_LAN BIT(0) +#define VW_IDX_42_SLP_WLAN BIT(1) #define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43 #define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44 #define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47 #define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE+0x90) -#define ESPI_INTERRUPT_EVENT_PUT_PC (1 << 7) +#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7) #define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE+0x91) #define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE+0x92) @@ -1348,7 +1348,7 @@ enum usbpd_port { #define IT83XX_USB_BASE 0x00F02F00 #define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE+0xE4) -#define USB_DP_DM_PULL_DOWN_EN (1 << 4) +#define USB_DP_DM_PULL_DOWN_EN BIT(4) /* Wake pin definitions, defined at board-level */ extern const enum gpio_signal hibernate_wake_pins[]; diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 98bf0e092a..d4f1987d4d 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -118,7 +118,7 @@ int system_is_reboot_warm(void) void chip_pre_init(void) { /* bit4, enable debug mode through SMBus */ - IT83XX_SMB_SLVISELR &= ~(1 << 4); + IT83XX_SMB_SLVISELR &= ~BIT(4); } #define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */ @@ -189,12 +189,12 @@ void system_reset(int flags) * If we are in debug mode, we need disable it before triggering * a soft reset or reset will fail. */ - IT83XX_SMB_SLVISELR |= (1 << 4); + IT83XX_SMB_SLVISELR |= BIT(4); /* bit0: enable watchdog hardware reset. */ #ifdef IT83XX_ETWD_HW_RESET_SUPPORT if (flags & SYSTEM_RESET_HARD) - IT83XX_GCTRL_ETWDUARTCR |= (1 << 0); + IT83XX_GCTRL_ETWDUARTCR |= BIT(0); #endif /* * Writing invalid key to watchdog module triggers a soft or hardware diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c index 24dc2ec4c6..8cfbfdf466 100644 --- a/chip/it83xx/uart.c +++ b/chip/it83xx/uart.c @@ -209,10 +209,10 @@ void uart_init(void) * bit3: uart1 belongs to the EC side. * This is necessary for enabling eSPI module. */ - IT83XX_GCTRL_RSTDMMC |= (1 << 3); + IT83XX_GCTRL_RSTDMMC |= BIT(3); /* reset uart before config it */ - IT83XX_GCTRL_RSTC4 |= (1 << 1); + IT83XX_GCTRL_RSTC4 |= BIT(1); /* Waiting for when we can use the GPIO module to set pin muxing */ gpio_config_module(MODULE_UART, 1); @@ -229,9 +229,9 @@ void uart_init(void) #ifdef CONFIG_UART_HOST /* bit2, reset UART2 */ - IT83XX_GCTRL_RSTC4 |= (1 << 2); + IT83XX_GCTRL_RSTC4 |= BIT(2); /* SIN1/SOUT1 of UART 2 is enabled. */ - IT83XX_GPIO_GRC1 |= (1 << 2); + IT83XX_GPIO_GRC1 |= BIT(2); /* Config UART 2 */ host_uart_config(); #endif diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c index ee21170e34..c9641114ab 100644 --- a/chip/it83xx/watchdog.c +++ b/chip/it83xx/watchdog.c @@ -100,7 +100,7 @@ int watchdog_init(void) #ifdef CONFIG_HIBERNATE /* bit4: watchdog can be stopped. */ - IT83XX_ETWD_ETWCTRL |= (1 << 4); + IT83XX_ETWD_ETWCTRL |= BIT(4); #else /* Specify that watchdog cannot be stopped. */ IT83XX_ETWD_ETWCTRL = 0x00; diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c index 6f3efb700e..6a746fd9b5 100644 --- a/chip/lm4/i2c.c +++ b/chip/lm4/i2c.c @@ -21,22 +21,22 @@ #define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) /* Flags for writes to MCS */ -#define LM4_I2C_MCS_RUN (1 << 0) -#define LM4_I2C_MCS_START (1 << 1) -#define LM4_I2C_MCS_STOP (1 << 2) -#define LM4_I2C_MCS_ACK (1 << 3) -#define LM4_I2C_MCS_HS (1 << 4) -#define LM4_I2C_MCS_QCMD (1 << 5) +#define LM4_I2C_MCS_RUN BIT(0) +#define LM4_I2C_MCS_START BIT(1) +#define LM4_I2C_MCS_STOP BIT(2) +#define LM4_I2C_MCS_ACK BIT(3) +#define LM4_I2C_MCS_HS BIT(4) +#define LM4_I2C_MCS_QCMD BIT(5) /* Flags for reads from MCS */ -#define LM4_I2C_MCS_BUSY (1 << 0) -#define LM4_I2C_MCS_ERROR (1 << 1) -#define LM4_I2C_MCS_ADRACK (1 << 2) -#define LM4_I2C_MCS_DATACK (1 << 3) -#define LM4_I2C_MCS_ARBLST (1 << 4) -#define LM4_I2C_MCS_IDLE (1 << 5) -#define LM4_I2C_MCS_BUSBSY (1 << 6) -#define LM4_I2C_MCS_CLKTO (1 << 7) +#define LM4_I2C_MCS_BUSY BIT(0) +#define LM4_I2C_MCS_ERROR BIT(1) +#define LM4_I2C_MCS_ADRACK BIT(2) +#define LM4_I2C_MCS_DATACK BIT(3) +#define LM4_I2C_MCS_ARBLST BIT(4) +#define LM4_I2C_MCS_IDLE BIT(5) +#define LM4_I2C_MCS_BUSBSY BIT(6) +#define LM4_I2C_MCS_CLKTO BIT(7) /* * Minimum delay between resetting the port or sending a stop condition, and @@ -298,7 +298,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { - /* Conveniently, MBMON bit (1 << 1) is SDA and (1 << 0) is SCL. */ + /* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */ return LM4_I2C_MBMON(port) & 0x03; } diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c index 66d66de1fa..85042ce85e 100644 --- a/chip/lm4/keyboard_raw.c +++ b/chip/lm4/keyboard_raw.c @@ -34,7 +34,7 @@ void keyboard_raw_init(void) * When column 2 is inverted, the Silego has a pulldown instead of a * pullup. So drive it push-pull instead of open-drain. */ - LM4_GPIO_ODR(LM4_GPIO_P) &= ~(1 << 2); + LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2); #endif /* Set row inputs with pull-up */ @@ -72,7 +72,7 @@ test_mockable void keyboard_raw_drive_column(int col) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* Invert column 2 output */ - mask ^= (1 << 2); + mask ^= BIT(2); #endif LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff; diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index f2f1cb0549..745e5e5465 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -405,7 +405,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask) int lpc_get_pltrst_asserted(void) { - return (LM4_LPC_LPCSTS & (1<<10)) ? 1 : 0; + return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0; } /** @@ -594,8 +594,8 @@ void lpc_interrupt(void) #endif /* Debugging: print changes to LPC0RESET */ - if (mis & (1 << 31)) { - if (LM4_LPC_LPCSTS & (1 << 10)) { + if (mis & BIT(31)) { + if (LM4_LPC_LPCSTS & BIT(10)) { int i; /* Store port 80 reset event */ @@ -682,7 +682,7 @@ static void lpc_init(void) * data writes, pool bytes 0(data)/1(cmd) */ LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60; - LM4_LPC_CTL(LPC_CH_KEYBOARD) = (1 << 24/* IRQSEL1 */) | + LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) | (0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1)); LM4_LPC_ST(LPC_CH_KEYBOARD) = 0; /* Unmask interrupt for host command/data writes and data reads */ @@ -743,7 +743,7 @@ static void lpc_init(void) * Unmask LPC bus reset interrupt. This lets us monitor the PCH * PLTRST# signal for debugging. */ - LM4_LPC_LPCIM |= (1 << 31); + LM4_LPC_LPCIM |= BIT(31); /* Enable LPC channels */ LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 | @@ -820,7 +820,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 2) | (1 << 3); + r->protocol_versions = BIT(2) | BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index 15c91d1ca3..7fad67c181 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -41,11 +41,11 @@ static inline int lm4_spi_addr(int ch, int offset) #define LM4_SSI_CR1(ch) LM4SSIREG(ch, 0x004) #define LM4_SSI_DR(ch) LM4SSIREG(ch, 0x008) #define LM4_SSI_SR(ch) LM4SSIREG(ch, 0x00c) -#define LM4_SSI_SR_TFE (1 << 0) /* Transmit FIFO empty */ -#define LM4_SSI_SR_TNF (1 << 1) /* Transmit FIFO not full */ -#define LM4_SSI_SR_RNE (1 << 2) /* Receive FIFO not empty */ -#define LM4_SSI_SR_RFF (1 << 3) /* Receive FIFO full */ -#define LM4_SSI_SR_BSY (1 << 4) /* Busy */ +#define LM4_SSI_SR_TFE BIT(0) /* Transmit FIFO empty */ +#define LM4_SSI_SR_TNF BIT(1) /* Transmit FIFO not full */ +#define LM4_SSI_SR_RNE BIT(2) /* Receive FIFO not empty */ +#define LM4_SSI_SR_RFF BIT(3) /* Receive FIFO full */ +#define LM4_SSI_SR_BSY BIT(4) /* Busy */ #define LM4_SSI_CPSR(ch) LM4SSIREG(ch, 0x010) #define LM4_SSI_IM(ch) LM4SSIREG(ch, 0x014) #define LM4_SSI_RIS(ch) LM4SSIREG(ch, 0x018) @@ -85,7 +85,7 @@ static inline int lm4_adc_addr(int ss, int offset) #define LM4_ADC_SSEMUX(ss) LM4ADCREG(ss, 0x018) #define LM4_LPC_LPCCTL REG32(0x40080000) -#define LM4_LPC_SCI_START (1 << 9) /* Start a pulse on LPC0SCI signal */ +#define LM4_LPC_SCI_START BIT(9) /* Start a pulse on LPC0SCI signal */ #define LM4_LPC_SCI_CLK_1 (0 << 10) /* SCI asserted for 1 clock period */ #define LM4_LPC_SCI_CLK_2 (1 << 10) /* SCI asserted for 2 clock periods */ #define LM4_LPC_SCI_CLK_4 (2 << 10) /* SCI asserted for 4 clock periods */ @@ -115,13 +115,13 @@ static inline int lm4_lpc_addr(int ch, int offset) #define LM4LPCREG(ch, offset) REG32(lm4_lpc_addr(ch, offset)) #define LM4_LPC_CTL(ch) LM4LPCREG(ch, 0x000) #define LM4_LPC_ST(ch) LM4LPCREG(ch, 0x004) -#define LM4_LPC_ST_TOH (1 << 0) /* TO Host bit */ -#define LM4_LPC_ST_FRMH (1 << 1) /* FRoM Host bit */ -#define LM4_LPC_ST_CMD (1 << 3) /* Last from-host byte was command */ -#define LM4_LPC_ST_BURST (1 << 8) -#define LM4_LPC_ST_SCI (1 << 9) -#define LM4_LPC_ST_SMI (1 << 10) -#define LM4_LPC_ST_BUSY (1 << 12) +#define LM4_LPC_ST_TOH BIT(0) /* TO Host bit */ +#define LM4_LPC_ST_FRMH BIT(1) /* FRoM Host bit */ +#define LM4_LPC_ST_CMD BIT(3) /* Last from-host byte was command */ +#define LM4_LPC_ST_BURST BIT(8) +#define LM4_LPC_ST_SCI BIT(9) +#define LM4_LPC_ST_SMI BIT(10) +#define LM4_LPC_ST_BUSY BIT(12) #define LM4_LPC_ADR(ch) LM4LPCREG(ch, 0x008) #define LM4_LPC_POOL_BYTES 1024 /* Size of LPCPOOL in bytes */ #define LM4_LPC_LPCPOOL ((volatile unsigned char *)0x40080400) @@ -186,12 +186,12 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004) #define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c) #define LM4_HIBERNATE_HIBCTL REG32(0x400fc010) -#define LM4_HIBCTL_WRC (1 << 31) -#define LM4_HIBCTL_CLK32EN (1 << 6) -#define LM4_HIBCTL_PINWEN (1 << 4) -#define LM4_HIBCTL_RTCWEN (1 << 3) -#define LM4_HIBCTL_HIBREQ (1 << 1) -#define LM4_HIBCTL_RTCEN (1 << 0) +#define LM4_HIBCTL_WRC BIT(31) +#define LM4_HIBCTL_CLK32EN BIT(6) +#define LM4_HIBCTL_PINWEN BIT(4) +#define LM4_HIBCTL_RTCWEN BIT(3) +#define LM4_HIBCTL_HIBREQ BIT(1) +#define LM4_HIBCTL_RTCEN BIT(0) #define LM4_HIBERNATE_HIBIM REG32(0x400fc014) #define LM4_HIBERNATE_HIBRIS REG32(0x400fc018) #define LM4_HIBERNATE_HIBMIS REG32(0x400fc01c) @@ -228,22 +228,22 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_SYSTEM_MISC REG32(0x400fe058) #define LM4_SYSTEM_RESC REG32(0x400fe05c) #define LM4_SYSTEM_RCC REG32(0x400fe060) -#define LM4_SYSTEM_RCC_ACG (1 << 27) +#define LM4_SYSTEM_RCC_ACG BIT(27) #define LM4_SYSTEM_RCC_SYSDIV(x) (((x) & 0xf) << 23) -#define LM4_SYSTEM_RCC_USESYSDIV (1 << 22) -#define LM4_SYSTEM_RCC_PWRDN (1 << 13) -#define LM4_SYSTEM_RCC_BYPASS (1 << 11) +#define LM4_SYSTEM_RCC_USESYSDIV BIT(22) +#define LM4_SYSTEM_RCC_PWRDN BIT(13) +#define LM4_SYSTEM_RCC_BYPASS BIT(11) #define LM4_SYSTEM_RCC_XTAL(x) (((x) & 0x1f) << 6) #define LM4_SYSTEM_RCC_OSCSRC(x) (((x) & 0x3) << 4) -#define LM4_SYSTEM_RCC_IOSCDIS (1 << 1) -#define LM4_SYSTEM_RCC_MOSCDIS (1 << 0) +#define LM4_SYSTEM_RCC_IOSCDIS BIT(1) +#define LM4_SYSTEM_RCC_MOSCDIS BIT(0) #define LM4_SYSTEM_RCC2 REG32(0x400fe070) -#define LM4_SYSTEM_RCC2_USERCC2 (1 << 31) -#define LM4_SYSTEM_RCC2_DIV400 (1 << 30) +#define LM4_SYSTEM_RCC2_USERCC2 BIT(31) +#define LM4_SYSTEM_RCC2_DIV400 BIT(30) #define LM4_SYSTEM_RCC2_SYSDIV2(x) (((x) & 0x3f) << 23) -#define LM4_SYSTEM_RCC2_SYSDIV2LSB (1 << 22) -#define LM4_SYSTEM_RCC2_PWRDN2 (1 << 13) -#define LM4_SYSTEM_RCC2_BYPASS2 (1 << 11) +#define LM4_SYSTEM_RCC2_SYSDIV2LSB BIT(22) +#define LM4_SYSTEM_RCC2_PWRDN2 BIT(13) +#define LM4_SYSTEM_RCC2_BYPASS2 BIT(11) #define LM4_SYSTEM_RCC2_OSCSRC2(x) (((x) & 0x7) << 4) #define LM4_SYSTEM_MOSCCTL REG32(0x400fe07c) #define LM4_SYSTEM_DSLPCLKCFG REG32(0x400fe144) diff --git a/chip/lm4/system.c b/chip/lm4/system.c index 45f6b91809..ce3d353bed 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -30,9 +30,9 @@ enum hibdata_index { }; /* Flags for HIBDATA_INDEX_WAKE */ -#define HIBDATA_WAKE_RTC (1 << 0) /* RTC alarm */ -#define HIBDATA_WAKE_HARD_RESET (1 << 1) /* Hard reset via short RTC alarm */ -#define HIBDATA_WAKE_PIN (1 << 2) /* Wake pin */ +#define HIBDATA_WAKE_RTC BIT(0) /* RTC alarm */ +#define HIBDATA_WAKE_HARD_RESET BIT(1) /* Hard reset via short RTC alarm */ +#define HIBDATA_WAKE_PIN BIT(2) /* Wake pin */ /* * Time to hibernate to trigger a power-on reset. 50 ms is sufficient for the diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c index 583ace0582..e7ff5e2e83 100644 --- a/chip/lm4/watchdog.c +++ b/chip/lm4/watchdog.c @@ -101,7 +101,7 @@ int watchdog_init(void) LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD; /* De-activate the watchdog when the JTAG stops the CPU */ - LM4_WATCHDOG_TEST(0) |= 1 << 8; + LM4_WATCHDOG_TEST(0) |= BIT(8); /* Reset after 2 time-out, activate the watchdog and lock the control * register. */ diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c index 6278bc1ebd..e8ec10a0e5 100644 --- a/chip/mchp/adc.c +++ b/chip/mchp/adc.c @@ -50,14 +50,14 @@ static int start_single_and_wait(int timeout) /* clear all R/W1C channel status */ MCHP_ADC_STS = 0xffffu; /* clear R/W1C single done status */ - MCHP_ADC_CTRL |= (1 << 7); + MCHP_ADC_CTRL |= BIT(7); /* clear GIRQ single status */ MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; /* make sure all writes are issued before starting conversion */ asm volatile ("dsb"); /* Start conversion */ - MCHP_ADC_CTRL |= 1 << 1; + MCHP_ADC_CTRL |= BIT(1); MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; @@ -131,7 +131,7 @@ static void adc_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ADC); /* Activate ADC module */ - MCHP_ADC_CTRL |= 1 << 0; + MCHP_ADC_CTRL |= BIT(0); /* Enable interrupt */ task_waiting = TASK_ID_INVALID; @@ -148,7 +148,7 @@ void adc_interrupt(void) MCHP_ADC_STS = 0xffffu; /* Clear interrupt status bit */ - MCHP_ADC_CTRL |= 1 << 7; + MCHP_ADC_CTRL |= BIT(7); MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index 59731830cf..6046eee7fb 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -341,7 +341,7 @@ static void prepare_for_deep_sleep(void) /* Enable assertion of DeepSleep signals * from the core when core enters sleep. */ - CPU_SCB_SYSCTRL |= (1 << 2); + CPU_SCB_SYSCTRL |= BIT(2); /* Stop timers */ MCHP_TMR32_CTL(0) &= ~1; @@ -422,7 +422,7 @@ static void resume_from_deep_sleep(void) MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */ /* Disable assertion of DeepSleep signal when core executes WFI */ - CPU_SCB_SYSCTRL &= ~(1 << 2); + CPU_SCB_SYSCTRL &= ~BIT(2); #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG print_saved_regs(); @@ -483,7 +483,7 @@ static void resume_from_deep_sleep(void) #ifdef CONFIG_WATCHDOG #ifdef CONFIG_CHIPSET_DEBUG /* enable WDG stall on active JTAG and do not start */ - MCHP_WDG_CTL = (1 << 4); + MCHP_WDG_CTL = BIT(4); #else MCHP_WDG_CTL |= 1; #endif diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c index 6f89f06673..dc939bb58f 100644 --- a/chip/mchp/fan.c +++ b/chip/mchp/fan.c @@ -82,15 +82,15 @@ int fan_get_duty(int ch) int fan_get_rpm_mode(int ch) { - return !!(MCHP_FAN_CFG1(0) & (1 << 7)); + return !!(MCHP_FAN_CFG1(0) & BIT(7)); } void fan_set_rpm_mode(int ch, int rpm_mode) { if (rpm_mode) - MCHP_FAN_CFG1(0) |= 1 << 7; + MCHP_FAN_CFG1(0) |= BIT(7); else - MCHP_FAN_CFG1(0) &= ~(1 << 7); + MCHP_FAN_CFG1(0) &= ~BIT(7); clear_status(); } @@ -118,7 +118,7 @@ enum fan_status fan_get_status(int ch) { uint8_t sts = MCHP_FAN_STATUS(0); - if (sts & ((1 << 5) | (1 << 1))) + if (sts & (BIT(5) | BIT(1))) return FAN_STATUS_FRUSTRATED; if (fan_get_rpm_actual(ch) == 0) return FAN_STATUS_STOPPED; diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c index 282c643a95..aa95b8fb0d 100644 --- a/chip/mchp/gpio.c +++ b/chip/mchp/gpio.c @@ -57,7 +57,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) while (mask) { i = __builtin_ffs(mask) - 1; val = MCHP_GPIO_CTL(port, i); - val &= ~((1 << 12) | (1 << 13)); + val &= ~(BIT(12) | BIT(13)); /* mux_control = 0 indicates GPIO */ if (func > 0) val |= (func & 0x3) << 12; @@ -77,7 +77,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(mask); val = MCHP_GPIO_CTL(gpio_list[signal].port, i); - return (val & (1 << 24)) ? 1 : 0; + return (val & BIT(24)) ? 1 : 0; } void gpio_set_level(enum gpio_signal signal, int value) @@ -90,9 +90,9 @@ void gpio_set_level(enum gpio_signal signal, int value) i = GPIO_MASK_TO_NUM(mask); if (value) - MCHP_GPIO_CTL(gpio_list[signal].port, i) |= (1 << 16); + MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); else - MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~(1 << 16); + MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); } /* diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c index 1cb2b4fbcb..f8b556d389 100644 --- a/chip/mchp/gpspi.c +++ b/chip/mchp/gpspi.c @@ -109,7 +109,7 @@ int gpspi_transaction_async(const struct spi_device_t *spi_device, ctrl = gpspi_port_to_ctrl_id(hw_port); /* Disable auto read */ - MCHP_SPI_CR(ctrl) &= ~(1 << 5); + MCHP_SPI_CR(ctrl) &= ~BIT(5); if ((txdata != NULL) && (txdata != 0)) { #ifdef CONFIG_MCHP_GPSPI_TX_DMA @@ -151,7 +151,7 @@ int gpspi_transaction_async(const struct spi_device_t *spi_device, if (!cs_asserted) gpio_set_level(spi_device->gpio_cs, 0); /* Enable auto read */ - MCHP_SPI_CR(ctrl) |= 1 << 5; + MCHP_SPI_CR(ctrl) |= BIT(5); dma_start_rx(opdma, rxlen, rxdata); MCHP_SPI_TD(ctrl) = 0; ret = EC_SUCCESS; @@ -180,7 +180,7 @@ int gpspi_transaction_flush(const struct spi_device_t *spi_device) ret = dma_wait(chan); /* Disable auto read */ - MCHP_SPI_CR(ctrl) &= ~(1 << 5); + MCHP_SPI_CR(ctrl) &= ~BIT(5); deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; /* Wait for FIFO empty SPISR_TXBE */ diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c index fa68d09f18..a69fa4ab7e 100644 --- a/chip/mchp/hwtimer.c +++ b/chip/mchp/hwtimer.c @@ -18,7 +18,7 @@ void __hw_clock_event_set(uint32_t deadline) { MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - (0xffffffff - deadline); - MCHP_TMR32_CTL(1) |= (1 << 5); + MCHP_TMR32_CTL(1) |= BIT(5); } uint32_t __hw_clock_event_get(void) @@ -28,7 +28,7 @@ uint32_t __hw_clock_event_get(void) void __hw_clock_event_clear(void) { - MCHP_TMR32_CTL(1) &= ~(1 << 5); + MCHP_TMR32_CTL(1) &= ~BIT(5); } uint32_t __hw_clock_source_read(void) @@ -38,9 +38,9 @@ uint32_t __hw_clock_source_read(void) void __hw_clock_source_set(uint32_t ts) { - MCHP_TMR32_CTL(0) &= ~(1 << 5); + MCHP_TMR32_CTL(0) &= ~BIT(5); MCHP_TMR32_CNT(0) = 0xffffffff - ts; - MCHP_TMR32_CTL(0) |= (1 << 5); + MCHP_TMR32_CTL(0) |= BIT(5); } /* @@ -66,10 +66,10 @@ static void configure_timer(int timer_id) uint32_t val; /* Ensure timer is not running */ - MCHP_TMR32_CTL(timer_id) &= ~(1 << 5); + MCHP_TMR32_CTL(timer_id) &= ~BIT(5); /* Enable timer */ - MCHP_TMR32_CTL(timer_id) |= (1 << 0); + MCHP_TMR32_CTL(timer_id) |= BIT(0); val = MCHP_TMR32_CTL(timer_id); @@ -103,10 +103,10 @@ int __hw_clock_source_init(uint32_t start_t) MCHP_TMR32_CNT(0) = 0xffffffff - start_t; /* Auto restart */ - MCHP_TMR32_CTL(0) |= (1 << 3); + MCHP_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MCHP_TMR32_CTL(0) |= (1 << 5); + MCHP_TMR32_CTL(0) |= BIT(5); /* Enable interrupt */ task_enable_irq(MCHP_IRQ_TIMER32_0); diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c index bfe4890d4f..f47f209947 100644 --- a/chip/mchp/i2c.c +++ b/chip/mchp/i2c.c @@ -46,44 +46,44 @@ #define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul #define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul /* Status */ -#define STS_NBB (1 << 0) /* Bus busy */ -#define STS_LAB (1 << 1) /* Arbitration lost */ -#define STS_LRB (1 << 3) /* Last received bit */ -#define STS_BER (1 << 4) /* Bus error */ -#define STS_PIN (1 << 7) /* Pending interrupt */ +#define STS_NBB BIT(0) /* Bus busy */ +#define STS_LAB BIT(1) /* Arbitration lost */ +#define STS_LRB BIT(3) /* Last received bit */ +#define STS_BER BIT(4) /* Bus error */ +#define STS_PIN BIT(7) /* Pending interrupt */ /* Control */ -#define CTRL_ACK (1 << 0) /* Acknowledge */ -#define CTRL_STO (1 << 1) /* STOP */ -#define CTRL_STA (1 << 2) /* START */ -#define CTRL_ENI (1 << 3) /* Enable interrupt */ -#define CTRL_ESO (1 << 6) /* Enable serial output */ -#define CTRL_PIN (1 << 7) /* Pending interrupt not */ +#define CTRL_ACK BIT(0) /* Acknowledge */ +#define CTRL_STO BIT(1) /* STOP */ +#define CTRL_STA BIT(2) /* START */ +#define CTRL_ENI BIT(3) /* Enable interrupt */ +#define CTRL_ESO BIT(6) /* Enable serial output */ +#define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_DTEN (1 << 2) /* enable device timeouts */ -#define COMP_MCEN (1 << 3) /* enable master cumulative timeouts */ -#define COMP_SCEN (1 << 4) /* enable slave cumulative timeouts */ -#define COMP_BIDEN (1 << 5) /* enable Bus idle timeouts */ -#define COMP_IDLE (1 << 29) /* i2c bus is idle */ +#define COMP_DTEN BIT(2) /* enable device timeouts */ +#define COMP_MCEN BIT(3) /* enable master cumulative timeouts */ +#define COMP_SCEN BIT(4) /* enable slave cumulative timeouts */ +#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Configuration */ #define CFG_PORT_MASK (0x0F) /* port selection field */ -#define CFG_TCEN (1 << 4) /* Enable HW bus timeouts */ -#define CFG_FEN (1 << 8) /* enable input filtering */ -#define CFG_RESET (1 << 9) /* reset controller */ -#define CFG_ENABLE (1 << 10) /* enable controller */ -#define CFG_GC_DIS (1 << 14) /* disable general call address */ -#define CFG_ENIDI (1 << 29) /* Enable I2C idle interrupt */ +#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */ +#define CFG_FEN BIT(8) /* enable input filtering */ +#define CFG_RESET BIT(9) /* reset controller */ +#define CFG_ENABLE BIT(10) /* enable controller */ +#define CFG_GC_DIS BIT(14) /* disable general call address */ +#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */ /* Enable network layer master done interrupt */ -#define CFG_ENMI (1 << 30) +#define CFG_ENMI BIT(30) /* Enable network layer slave done interrupt */ -#define CFG_ENSI (1 << 31) +#define CFG_ENSI BIT(31) /* Master Command */ -#define MCMD_MRUN (1 << 0) -#define MCMD_MPROCEED (1 << 1) -#define MCMD_START0 (1 << 8) -#define MCMD_STARTN (1 << 9) -#define MCMD_STOP (1 << 10) -#define MCMD_READM (1 << 12) +#define MCMD_MRUN BIT(0) +#define MCMD_MPROCEED BIT(1) +#define MCMD_START0 BIT(8) +#define MCMD_STARTN BIT(9) +#define MCMD_STOP BIT(10) +#define MCMD_READM BIT(12) #define MCMD_WCNT_BITPOS (16) #define MCMD_WCNT_MASK0 (0xFF) #define MCMD_WCNT_MASK (0xFF << 16) @@ -342,9 +342,9 @@ static void reset_controller(int controller) int i; /* Reset asserted for at least one AHB clock */ - MCHP_I2C_CONFIG(controller) |= 1 << 9; + MCHP_I2C_CONFIG(controller) |= BIT(9); MCHP_EC_ID_RO = 0; - MCHP_I2C_CONFIG(controller) &= ~(1 << 9); + MCHP_I2C_CONFIG(controller) &= ~BIT(9); for (i = 0; i < i2c_ports_used; ++i) if (controller == i2c_port_to_controller(i2c_ports[i].port)) { @@ -464,9 +464,9 @@ static void select_port(int port, int controller) if ((MCHP_I2C_CONFIG(controller) & 0x0f) == port_sel) return; - MCHP_I2C_CONFIG(controller) |= 1 << 9; + MCHP_I2C_CONFIG(controller) |= BIT(9); MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */ - MCHP_I2C_CONFIG(controller) &= ~(1 << 9); + MCHP_I2C_CONFIG(controller) &= ~BIT(9); configure_controller(controller, port_sel, i2c_ports[port].kbps); } diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c index ef968c0eb8..946ea1ca90 100644 --- a/chip/mchp/keyboard_raw.c +++ b/chip/mchp/keyboard_raw.c @@ -39,19 +39,19 @@ void keyboard_raw_task_start(void) test_mockable void keyboard_raw_drive_column(int out) { if (out == KEYBOARD_COLUMN_ALL) { - MCHP_KS_KSO_SEL = 1 << 5; /* KSEN=0, KSALL=1 */ + MCHP_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 1); #endif } else if (out == KEYBOARD_COLUMN_NONE) { - MCHP_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 0); #endif } else { #ifdef CONFIG_KEYBOARD_COL2_INVERTED if (out == 2) { - MCHP_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */ gpio_set_level(GPIO_KBD_KSO2, 1); } else { MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; @@ -100,5 +100,5 @@ DECLARE_IRQ(MCHP_IRQ_KSC_INT, keyboard_raw_interrupt, 1); int keyboard_raw_is_input_low(int port, int id) { - return (MCHP_GPIO_CTL(port, id) & (1 << 24)) == 0; + return (MCHP_GPIO_CTL(port, id) & BIT(24)) == 0; } diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c index a9f923d5bb..111e753d3b 100644 --- a/chip/mchp/lfw/ec_lfw.c +++ b/chip/mchp/lfw/ec_lfw.c @@ -100,10 +100,10 @@ void timer_init(void) uint32_t val = 0; /* Ensure timer is not running */ - MCHP_TMR32_CTL(0) &= ~(1 << 5); + MCHP_TMR32_CTL(0) &= ~BIT(5); /* Enable timer */ - MCHP_TMR32_CTL(0) |= (1 << 0); + MCHP_TMR32_CTL(0) |= BIT(0); val = MCHP_TMR32_CTL(0); @@ -119,10 +119,10 @@ void timer_init(void) MCHP_TMR32_CNT(0) = 0xffffffff; /* Auto restart */ - MCHP_TMR32_CTL(0) |= (1 << 3); + MCHP_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MCHP_TMR32_CTL(0) |= (1 << 5); + MCHP_TMR32_CTL(0) |= BIT(5); } @@ -246,7 +246,7 @@ void uart_write_c(char c) uart_write_c('\r'); /* Wait for space in transmit FIFO. */ - while (!(MCHP_UART_LSR(0) & (1 << 5))) + while (!(MCHP_UART_LSR(0) & BIT(5))) ; MCHP_UART_TB(0) = c; } @@ -282,31 +282,31 @@ void jump_to_image(uintptr_t init_addr) void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MCHP_UART_CFG(0) &= ~(1 << 1); + MCHP_UART_CFG(0) &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MCHP_UART_CFG(0) &= ~(1 << 0); + MCHP_UART_CFG(0) &= ~BIT(0); /* Set DLAB = 1 */ - MCHP_UART_LCR(0) |= (1 << 7); + MCHP_UART_LCR(0) |= BIT(7); /* PBRG0/PBRG1 */ MCHP_UART_PBRG0(0) = 1; MCHP_UART_PBRG1(0) = 0; /* Set DLAB = 0 */ - MCHP_UART_LCR(0) &= ~(1 << 7); + MCHP_UART_LCR(0) &= ~BIT(7); /* Set word length to 8-bit */ - MCHP_UART_LCR(0) |= (1 << 0) | (1 << 1); + MCHP_UART_LCR(0) |= BIT(0) | BIT(1); /* Enable FIFO */ - MCHP_UART_FCR(0) = (1 << 0); + MCHP_UART_FCR(0) = BIT(0); /* Activate UART */ - MCHP_UART_ACT(0) |= (1 << 0); + MCHP_UART_ACT(0) |= BIT(0); gpio_config_module(MODULE_UART, 1); } diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index 96d68898c2..32e1c81c95 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -348,7 +348,7 @@ void chip_8042_config(uint32_t io_base) MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15); #endif /* Set up indication of Auxiliary sts */ - MCHP_8042_KB_CTRL |= 1 << 7; + MCHP_8042_KB_CTRL |= BIT(7); MCHP_8042_ACT |= 1; @@ -360,7 +360,7 @@ void chip_8042_config(uint32_t io_base) #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MCHP_8042_KB_CTRL |= (1 << 5); + MCHP_8042_KB_CTRL |= BIT(5); MCHP_LPC_SIRQ(1) = 0x01; #endif } @@ -464,7 +464,7 @@ static void setup_lpc(void) #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MCHP_8042_KB_CTRL |= (1 << 5); + MCHP_8042_KB_CTRL |= BIT(5); MCHP_LPC_SIRQ(1) = 0x01; #endif /* EMI0 at IO 0x800 */ @@ -815,7 +815,7 @@ void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) keyboard_host_write(MCHP_8042_H2E, - MCHP_8042_STS & (1 << 3)); + MCHP_8042_STS & BIT(3)); MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT; task_wake(TASK_ID_KEYPROTO); @@ -844,12 +844,12 @@ DECLARE_IRQ(MCHP_IRQ_8042EM_OBE, kb_obe_interrupt, 1); */ int lpc_keyboard_has_char(void) { - return (MCHP_8042_STS & (1 << 0)) ? 1 : 0; + return (MCHP_8042_STS & BIT(0)) ? 1 : 0; } int lpc_keyboard_input_pending(void) { - return (MCHP_8042_STS & (1 << 1)) ? 1 : 0; + return (MCHP_8042_STS & BIT(1)) ? 1 : 0; } /* @@ -944,7 +944,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) CPUTS("MEC1701 Handler EC_CMD_GET_PROTOCOL_INFO"); memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c index 54200c7890..53a8c15806 100644 --- a/chip/mchp/pwm.c +++ b/chip/mchp/pwm.c @@ -110,8 +110,8 @@ static void pwm_configure(int ch, int active_low, int clock_low) * clock_low=1 selects the 100kHz_Clk source */ MCHP_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? (1 << 2) : 0) | - (clock_low ? (1 << 1) : 0); + (active_low ? BIT(2) : 0) | + (clock_low ? BIT(1) : 0); } static const uint16_t pwm_pcr[MCHP_PWM_ID_MAX] = { diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h index 2fcbd9ab46..f7ef36e68c 100644 --- a/chip/mchp/registers.h +++ b/chip/mchp/registers.h @@ -90,64 +90,64 @@ #define MCHP_PCR_JTAG (0x0000) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN0_ISPI (1 << 2) -#define MCHP_PCR_SLP_EN0_EFUSE (1 << 1) -#define MCHP_PCR_SLP_EN0_JTAG (1 << 0) +#define MCHP_PCR_SLP_EN0_ISPI BIT(2) +#define MCHP_PCR_SLP_EN0_EFUSE BIT(1) +#define MCHP_PCR_SLP_EN0_JTAG BIT(0) #define MCHP_PCR_SLP_EN0_SLEEP 0x07ul /* Sleep Enable, Clock Required, Reset on Sleep 1 bits */ -#define MCHP_PCR_BTMR16_1 ((1 << 8) + 31) -#define MCHP_PCR_BTMR16_0 ((1 << 8) + 30) -#define MCHP_PCR_ECS ((1 << 8) + 29) -#define MCHP_PCR_PWM8 ((1 << 8) + 27) -#define MCHP_PCR_PWM7 ((1 << 8) + 26) -#define MCHP_PCR_PWM6 ((1 << 8) + 25) -#define MCHP_PCR_PWM5 ((1 << 8) + 24) -#define MCHP_PCR_PWM4 ((1 << 8) + 23) -#define MCHP_PCR_PWM3 ((1 << 8) + 22) -#define MCHP_PCR_PWM2 ((1 << 8) + 21) -#define MCHP_PCR_PWM1 ((1 << 8) + 20) -#define MCHP_PCR_TACH2 ((1 << 8) + 12) -#define MCHP_PCR_TACH1 ((1 << 8) + 11) -#define MCHP_PCR_I2C0 ((1 << 8) + 10) -#define MCHP_PCR_WDT ((1 << 8) + 9) -#define MCHP_PCR_CPU ((1 << 8) + 8) -#define MCHP_PCR_TFDP ((1 << 8) + 7) -#define MCHP_PCR_DMA ((1 << 8) + 6) -#define MCHP_PCR_PMC ((1 << 8) + 5) -#define MCHP_PCR_PWM0 ((1 << 8) + 4) -#define MCHP_PCR_TACH0 ((1 << 8) + 2) -#define MCHP_PCR_PECI ((1 << 8) + 1) -#define MCHP_PCR_ECIA ((1 << 8) + 0) +#define MCHP_PCR_BTMR16_1 (BIT(8) + 31) +#define MCHP_PCR_BTMR16_0 (BIT(8) + 30) +#define MCHP_PCR_ECS (BIT(8) + 29) +#define MCHP_PCR_PWM8 (BIT(8) + 27) +#define MCHP_PCR_PWM7 (BIT(8) + 26) +#define MCHP_PCR_PWM6 (BIT(8) + 25) +#define MCHP_PCR_PWM5 (BIT(8) + 24) +#define MCHP_PCR_PWM4 (BIT(8) + 23) +#define MCHP_PCR_PWM3 (BIT(8) + 22) +#define MCHP_PCR_PWM2 (BIT(8) + 21) +#define MCHP_PCR_PWM1 (BIT(8) + 20) +#define MCHP_PCR_TACH2 (BIT(8) + 12) +#define MCHP_PCR_TACH1 (BIT(8) + 11) +#define MCHP_PCR_I2C0 (BIT(8) + 10) +#define MCHP_PCR_WDT (BIT(8) + 9) +#define MCHP_PCR_CPU (BIT(8) + 8) +#define MCHP_PCR_TFDP (BIT(8) + 7) +#define MCHP_PCR_DMA (BIT(8) + 6) +#define MCHP_PCR_PMC (BIT(8) + 5) +#define MCHP_PCR_PWM0 (BIT(8) + 4) +#define MCHP_PCR_TACH0 (BIT(8) + 2) +#define MCHP_PCR_PECI (BIT(8) + 1) +#define MCHP_PCR_ECIA (BIT(8) + 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN1_BTMR16_1 (1 << 31) -#define MCHP_PCR_SLP_EN1_BTMR16_0 (1 << 30) -#define MCHP_PCR_SLP_EN1_ECS (1 << 29) +#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) +#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) +#define MCHP_PCR_SLP_EN1_ECS BIT(29) /* bit[28] reserved */ -#define MCHP_PCR_SLP_EN1_PWM_ALL ((1 << 4) + (0xff << 20)) -#define MCHP_PCR_SLP_EN1_PWM8 (1 << 27) -#define MCHP_PCR_SLP_EN1_PWM7 (1 << 26) -#define MCHP_PCR_SLP_EN1_PWM6 (1 << 25) -#define MCHP_PCR_SLP_EN1_PWM5 (1 << 24) -#define MCHP_PCR_SLP_EN1_PWM4 (1 << 23) -#define MCHP_PCR_SLP_EN1_PWM3 (1 << 22) -#define MCHP_PCR_SLP_EN1_PWM2 (1 << 21) -#define MCHP_PCR_SLP_EN1_PWM1 (1 << 20) +#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) +#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) +#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) +#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) +#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) +#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) +#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) +#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) +#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) /* bits[19:13] reserved */ -#define MCHP_PCR_SLP_EN1_TACH2 (1 << 12) -#define MCHP_PCR_SLP_EN1_TACH1 (1 << 11) -#define MCHP_PCR_SLP_EN1_I2C0 (1 << 10) -#define MCHP_PCR_SLP_EN1_WDT (1 << 9) -#define MCHP_PCR_SLP_EN1_CPU (1 << 8) -#define MCHP_PCR_SLP_EN1_TFDP (1 << 7) -#define MCHP_PCR_SLP_EN1_DMA (1 << 6) -#define MCHP_PCR_SLP_EN1_PMC (1 << 5) -#define MCHP_PCR_SLP_EN1_PWM0 (1 << 4) +#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) +#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) +#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) +#define MCHP_PCR_SLP_EN1_WDT BIT(9) +#define MCHP_PCR_SLP_EN1_CPU BIT(8) +#define MCHP_PCR_SLP_EN1_TFDP BIT(7) +#define MCHP_PCR_SLP_EN1_DMA BIT(6) +#define MCHP_PCR_SLP_EN1_PMC BIT(5) +#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) /* bit[3] reserved */ -#define MCHP_PCR_SLP_EN1_TACH0 (1 << 2) -#define MCHP_PCR_SLP_EN1_PECI (1 << 1) -#define MCHP_PCR_SLP_EN1_ECIA (1 << 0) +#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) +#define MCHP_PCR_SLP_EN1_PECI BIT(1) +#define MCHP_PCR_SLP_EN1_ECIA BIT(0) /* all sleep enable 1 bits */ #define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff /* @@ -176,25 +176,25 @@ /* Command all blocks to sleep */ /* bits[31:27] reserved */ -#define MCHP_PCR_SLP_EN2_P80CAP1 (1 << 26) -#define MCHP_PCR_SLP_EN2_P80CAP0 (1 << 25) +#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) +#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) /* bit[24] reserved */ -#define MCHP_PCR_SLP_EN2_ACPI_EC4 (1 << 23) -#define MCHP_PCR_SLP_EN2_ACPI_EC3 (1 << 22) -#define MCHP_PCR_SLP_EN2_ACPI_EC2 (1 << 21) +#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) +#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) +#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) /* bit[20] reserved */ -#define MCHP_PCR_SLP_EN2_ESPI (1 << 19) -#define MCHP_PCR_SLP_EN2_RTC (1 << 18) -#define MCHP_PCR_SLP_EN2_MAILBOX (1 << 17) -#define MCHP_PCR_SLP_EN2_MIF8042 (1 << 16) -#define MCHP_PCR_SLP_EN2_ACPI_PM1 (1 << 15) -#define MCHP_PCR_SLP_EN2_ACPI_EC1 (1 << 14) -#define MCHP_PCR_SLP_EN2_ACPI_EC0 (1 << 13) -#define MCHP_PCR_SLP_EN2_GCFG (1 << 12) +#define MCHP_PCR_SLP_EN2_ESPI BIT(19) +#define MCHP_PCR_SLP_EN2_RTC BIT(18) +#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) +#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) +#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) +#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) +#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) +#define MCHP_PCR_SLP_EN2_GCFG BIT(12) /* bits[11:3] reserved */ -#define MCHP_PCR_SLP_EN2_UART1 (1 << 2) -#define MCHP_PCR_SLP_EN2_UART0 (1 << 1) -#define MCHP_PCR_SLP_EN2_LPC (1 << 0) +#define MCHP_PCR_SLP_EN2_UART1 BIT(2) +#define MCHP_PCR_SLP_EN2_UART0 BIT(1) +#define MCHP_PCR_SLP_EN2_LPC BIT(0) /* all sleep enable 2 bits */ #define MCHP_PCR_SLP_EN2_SLEEP 0x07ffffff @@ -228,35 +228,35 @@ #define MCHP_PCR_ADC ((3 << 8) + 3) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN3_PWM9 (1 << 31) -#define MCHP_PCR_SLP_EN3_CCT0 (1 << 30) -#define MCHP_PCR_SLP_EN3_HTMR1 (1 << 29) -#define MCHP_PCR_SLP_EN3_AESHASH (1 << 28) -#define MCHP_PCR_SLP_EN3_RNG (1 << 27) -#define MCHP_PCR_SLP_EN3_PKE (1 << 26) -#define MCHP_PCR_SLP_EN3_LED3 (1 << 25) -#define MCHP_PCR_SLP_EN3_BTMR32_1 (1 << 24) -#define MCHP_PCR_SLP_EN3_BTMR32_0 (1 << 23) -#define MCHP_PCR_SLP_EN3_BTMR16_3 (1 << 22) -#define MCHP_PCR_SLP_EN3_BTMR16_2 (1 << 21) -#define MCHP_PCR_SLP_EN3_GPSPI1 (1 << 20) -#define MCHP_PCR_SLP_EN3_BCM0 (1 << 19) -#define MCHP_PCR_SLP_EN3_LED2 (1 << 18) -#define MCHP_PCR_SLP_EN3_LED1 (1 << 17) -#define MCHP_PCR_SLP_EN3_LED0 (1 << 16) -#define MCHP_PCR_SLP_EN3_I2C3 (1 << 15) -#define MCHP_PCR_SLP_EN3_I2C2 (1 << 14) -#define MCHP_PCR_SLP_EN3_I2C1 (1 << 13) -#define MCHP_PCR_SLP_EN3_RPMPWM0 (1 << 12) -#define MCHP_PCR_SLP_EN3_KEYSCAN (1 << 11) -#define MCHP_PCR_SLP_EN3_HTMR0 (1 << 10) -#define MCHP_PCR_SLP_EN3_GPSPI0 (1 << 9) +#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) +#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) +#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) +#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) +#define MCHP_PCR_SLP_EN3_RNG BIT(27) +#define MCHP_PCR_SLP_EN3_PKE BIT(26) +#define MCHP_PCR_SLP_EN3_LED3 BIT(25) +#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) +#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) +#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) +#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) +#define MCHP_PCR_SLP_EN3_GPSPI1 BIT(20) +#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) +#define MCHP_PCR_SLP_EN3_LED2 BIT(18) +#define MCHP_PCR_SLP_EN3_LED1 BIT(17) +#define MCHP_PCR_SLP_EN3_LED0 BIT(16) +#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) +#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) +#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) +#define MCHP_PCR_SLP_EN3_RPMPWM0 BIT(12) +#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) +#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) +#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) /* bit[8] reserved */ -#define MCHP_PCR_SLP_EN3_PS2_2 (1 << 7) -#define MCHP_PCR_SLP_EN3_PS2_1 (1 << 6) -#define MCHP_PCR_SLP_EN3_PS2_0 (1 << 5) +#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7) +#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) +#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) /* bit[4] reserved */ -#define MCHP_PCR_SLP_EN3_ADC (1 << 3) +#define MCHP_PCR_SLP_EN3_ADC BIT(3) /* bits[2:0] reserved */ /* all sleep enable 3 bits */ #define MCHP_PCR_SLP_EN3_SLEEP 0xfffffeed @@ -281,23 +281,23 @@ #define MCHP_PCR_PWM10 ((4 << 8) + 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN4_FJCL (1 << 15) -#define MCHP_PCR_SLP_EN4_PSPI (1 << 14) -#define MCHP_PCR_SLP_EN4_PROCHOT (1 << 13) -#define MCHP_PCR_SLP_EN4_RCID2 (1 << 12) -#define MCHP_PCR_SLP_EN4_RCID1 (1 << 11) -#define MCHP_PCR_SLP_EN4_RCID0 (1 << 10) -#define MCHP_PCR_SLP_EN4_BCM1 (1 << 9) -#define MCHP_PCR_SLP_EN4_QMSPI (1 << 8) -#define MCHP_PCR_SLP_EN4_RPMPWM1 (1 << 7) -#define MCHP_PCR_SLP_EN4_RTMR (1 << 6) -#define MCHP_PCR_SLP_EN4_CNT16_3 (1 << 5) -#define MCHP_PCR_SLP_EN4_CNT16_2 (1 << 4) -#define MCHP_PCR_SLP_EN4_CNT16_1 (1 << 3) -#define MCHP_PCR_SLP_EN4_CNT16_0 (1 << 2) +#define MCHP_PCR_SLP_EN4_FJCL BIT(15) +#define MCHP_PCR_SLP_EN4_PSPI BIT(14) +#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) +#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) +#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) +#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) +#define MCHP_PCR_SLP_EN4_BCM1 BIT(9) +#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) +#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) +#define MCHP_PCR_SLP_EN4_RTMR BIT(6) +#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) +#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) +#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) +#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) #define MCHP_PCR_SLP_EN4_PWM_ALL (3 << 0) -#define MCHP_PCR_SLP_EN4_PWM11 (1 << 1) -#define MCHP_PCR_SLP_EN4_PWM10 (1 << 0) +#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) +#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) /* all sleep enable 4 bits */ #define MCHP_PCR_SLP_EN4_SLEEP 0x0000ffff @@ -314,17 +314,17 @@ /* Bit definitions for MCHP_PCR_SLP_EN2/CLK_REQ2/RST_EN2 */ /* Bit definitions for MCHP_PCR_SLP_EN3/CLK_REQ3/RST_EN3 */ -#define MCHP_PCR_SLP_EN1_PKE (1 << 26) -#define MCHP_PCR_SLP_EN1_NDRNG (1 << 27) -#define MCHP_PCR_SLP_EN1_AES_SHA (1 << 28) +#define MCHP_PCR_SLP_EN1_PKE BIT(26) +#define MCHP_PCR_SLP_EN1_NDRNG BIT(27) +#define MCHP_PCR_SLP_EN1_AES_SHA BIT(28) #define MCHP_PCR_SLP_EN1_ALL_CRYPTO (0x07 << 26) /* Bit definitions for MCHP_PCR_SLP_EN4/CLK_REQ4/RST_EN4 */ /* Bit defines for MCHP_PCR_PWR_RST_STS */ -#define MCHP_PWR_RST_STS_VTR (1 << 6) -#define MCHP_PWR_RST_STS_VBAT (1 << 5) +#define MCHP_PWR_RST_STS_VTR BIT(6) +#define MCHP_PWR_RST_STS_VBAT BIT(5) /* Bit defines for MCHP_PCR_PWR_RST_CTL */ #define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 @@ -333,7 +333,7 @@ /* Bit defines for MCHP_PCR_SYS_RST */ -#define MCHP_PCR_SYS_SOFT_RESET (1 << 8) +#define MCHP_PCR_SYS_SOFT_RESET BIT(8) /* TFDP */ @@ -554,7 +554,7 @@ #define MCHP_UART_GIRQ_BIT(x) (1ul << (x)) /* Bit defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY (1 << 5) +#define MCHP_LSR_TX_EMPTY BIT(5) /* GPIO */ @@ -580,7 +580,7 @@ * Example: GPIO043, Control 1 register address = 0x4008108c * port/bank = 0x23 >> 5 = 1 * id = 0x23 & 0x1F = 0x03 - * Control 1 Address = 0x40081000 + (((1 << 5) + 0x03) << 2) = 0x4008108c + * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c * * Example: GPIO235, Control 1 register address = 0x40081274 * port/bank = 0x9d >> 5 = 4 @@ -641,7 +641,7 @@ #define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) #define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) #define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) -#define MCHP_GPIO_CTRL_OUT_LVL (1 << 16) +#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) /* GPIO Parallel Input and Output registers. * gpio_bank in [0, 5] @@ -705,11 +705,11 @@ #define MCHP_VBAT_VWIRE_BACKUP 30 /* Bit definition for MCHP_VBAT_STS */ -#define MCHP_VBAT_STS_SOFTRESET (1 << 2) -#define MCHP_VBAT_STS_RESETI (1 << 4) -#define MCHP_VBAT_STS_WDT (1 << 5) -#define MCHP_VBAT_STS_SYSRESETREQ (1 << 6) -#define MCHP_VBAT_STS_VBAT_RST (1 << 7) +#define MCHP_VBAT_STS_SOFTRESET BIT(2) +#define MCHP_VBAT_STS_RESETI BIT(4) +#define MCHP_VBAT_STS_WDT BIT(5) +#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) +#define MCHP_VBAT_STS_VBAT_RST BIT(7) #define MCHP_VBAT_STS_ANY_RST (0xF4u) /* Bit definitions for MCHP_VBAT_CE */ @@ -1326,9 +1326,9 @@ enum MCHP_i2c_port { ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17) /* Bits in MCHP_QMSPI0_EXE */ -#define MCHP_QMSPI_EXE_START (1 << 0) -#define MCHP_QMSPI_EXE_STOP (1 << 1) -#define MCHP_QMSPI_EXE_CLR_FIFOS (1 << 2) +#define MCHP_QMSPI_EXE_START BIT(0) +#define MCHP_QMSPI_EXE_STOP BIT(1) +#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2) /* MCHP QMSPI FIFO Sizes */ #define MCHP_QMSPI_TX_FIFO_LEN 8 @@ -1982,30 +1982,30 @@ enum dma_channel { /* Bits for DMA Main Control */ -#define MCHP_DMA_MAIN_CTRL_ACT (1 << 0) -#define MCHP_DMA_MAIN_CTRL_SRST (1 << 1) +#define MCHP_DMA_MAIN_CTRL_ACT BIT(0) +#define MCHP_DMA_MAIN_CTRL_SRST BIT(1) /* Bits for DMA channel regs */ -#define MCHP_DMA_ACT_EN (1 << 0) +#define MCHP_DMA_ACT_EN BIT(0) /* DMA Channel Control */ -#define MCHP_DMA_ABORT (1 << 25) -#define MCHP_DMA_SW_GO (1 << 24) +#define MCHP_DMA_ABORT BIT(25) +#define MCHP_DMA_SW_GO BIT(24) #define MCHP_DMA_XFER_SIZE_MASK (7ul << 20) #define MCHP_DMA_XFER_SIZE(x) ((x) << 20) -#define MCHP_DMA_DIS_HW_FLOW (1 << 19) -#define MCHP_DMA_INC_DEV (1 << 17) -#define MCHP_DMA_INC_MEM (1 << 16) +#define MCHP_DMA_DIS_HW_FLOW BIT(19) +#define MCHP_DMA_INC_DEV BIT(17) +#define MCHP_DMA_INC_MEM BIT(16) #define MCHP_DMA_DEV(x) ((x) << 9) #define MCHP_DMA_DEV_MASK0 (0x7f) #define MCHP_DMA_DEV_MASK (0x7f << 9) -#define MCHP_DMA_TO_DEV (1 << 8) -#define MCHP_DMA_DONE (1 << 2) -#define MCHP_DMA_RUN (1 << 0) +#define MCHP_DMA_TO_DEV BIT(8) +#define MCHP_DMA_DONE BIT(2) +#define MCHP_DMA_RUN BIT(0) /* DMA Channel Status */ -#define MCHP_DMA_STS_ALU_DONE (1 << 3) -#define MCHP_DMA_STS_DONE (1 << 2) -#define MCHP_DMA_STS_HWFL_ERR (1 << 1) -#define MCHP_DMA_STS_BUS_ERR (1 << 0) +#define MCHP_DMA_STS_ALU_DONE BIT(3) +#define MCHP_DMA_STS_DONE BIT(2) +#define MCHP_DMA_STS_HWFL_ERR BIT(1) +#define MCHP_DMA_STS_BUS_ERR BIT(0) /* * Peripheral device DMA Device ID's for bits [15:9] diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h index 7d273e5155..75973e4a78 100644 --- a/chip/mchp/spi_chip.h +++ b/chip/mchp/spi_chip.h @@ -36,7 +36,7 @@ #define GPSPI_CLASS0 1 #define QMSPI_CLASS (0 << 4) -#define GPSPI_CLASS (1 << 4) +#define GPSPI_CLASS BIT(4) #define QMSPI_CTRL0 0 #define GPSPI_CTRL0 0 diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c index adeea5a31c..0f8bd62db8 100644 --- a/chip/mchp/uart.c +++ b/chip/mchp/uart.c @@ -30,7 +30,7 @@ int uart_init_done(void) void uart_tx_start(void) { /* If interrupt is already enabled, nothing to do */ - if (MCHP_UART_IER(0) & (1 << 1)) + if (MCHP_UART_IER(0) & BIT(1)) return; /* Do not allow deep sleep while transmit in progress */ @@ -42,13 +42,13 @@ void uart_tx_start(void) * UART where the FIFO only triggers the interrupt when its * threshold is _crossed_, not just met. */ - MCHP_UART_IER(0) |= (1 << 1); + MCHP_UART_IER(0) |= BIT(1); task_trigger_irq(MCHP_IRQ_UART0); } void uart_tx_stop(void) { - MCHP_UART_IER(0) &= ~(1 << 1); + MCHP_UART_IER(0) &= ~BIT(1); /* Re-allow deep sleep */ enable_sleep(SLEEP_MASK_UART); @@ -79,7 +79,7 @@ int uart_tx_in_progress(void) int uart_rx_available(void) { - return MCHP_UART_LSR(0) & (1 << 0); + return MCHP_UART_LSR(0) & BIT(0); } void uart_write_char(char c) @@ -99,7 +99,7 @@ int uart_read_char(void) static void uart_clear_rx_fifo(int channel) { - MCHP_UART_FCR(0) = (1 << 0) | (1 << 1); + MCHP_UART_FCR(0) = BIT(0) | BIT(1); } void uart_disable_interrupt(void) @@ -131,31 +131,31 @@ void uart_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_UART0); /* Set UART to reset on VCC1_RESET instead of nSIO_RESET */ - MCHP_UART_CFG(0) &= ~(1 << 1); + MCHP_UART_CFG(0) &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MCHP_UART_CFG(0) &= ~(1 << 0); + MCHP_UART_CFG(0) &= ~BIT(0); /* Set DLAB = 1 */ - MCHP_UART_LCR(0) |= (1 << 7); + MCHP_UART_LCR(0) |= BIT(7); /* PBRG0/PBRG1 */ MCHP_UART_PBRG0(0) = 1; MCHP_UART_PBRG1(0) = 0; /* Set DLAB = 0 */ - MCHP_UART_LCR(0) &= ~(1 << 7); + MCHP_UART_LCR(0) &= ~BIT(7); /* Set word length to 8-bit */ - MCHP_UART_LCR(0) |= (1 << 0) | (1 << 1); + MCHP_UART_LCR(0) |= BIT(0) | BIT(1); /* Enable FIFO */ - MCHP_UART_FCR(0) = (1 << 0); + MCHP_UART_FCR(0) = BIT(0); /* Activate UART */ - MCHP_UART_ACT(0) |= (1 << 0); + MCHP_UART_ACT(0) |= BIT(0); gpio_config_module(MODULE_UART, 1); @@ -163,8 +163,8 @@ void uart_init(void) * Enable interrupts for UART0. */ uart_clear_rx_fifo(0); - MCHP_UART_IER(0) |= (1 << 0); - MCHP_UART_MCR(0) |= (1 << 3); + MCHP_UART_IER(0) |= BIT(0); + MCHP_UART_MCR(0) |= BIT(3); MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); task_enable_irq(MCHP_IRQ_UART0); @@ -185,13 +185,13 @@ void uart_enter_dsleep(void) gpio_reset(GPIO_UART0_RX); /* power-down/de-activate UART0 */ - MCHP_UART_ACT(0) &= ~(1 << 0); + MCHP_UART_ACT(0) &= ~BIT(0); /* clear interrupt enable for UART0 */ MCHP_INT_DISABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); /* Clear pending interrupts on GPIO_UART0_RX(GPIO105, girq=9, bit=5) */ - MCHP_INT_SOURCE(9) = (1 << 5); + MCHP_INT_SOURCE(9) = BIT(5); /* Enable GPIO interrupts on the UART0 RX pin. */ gpio_enable_interrupt(GPIO_UART0_RX); @@ -207,7 +207,7 @@ void uart_exit_dsleep(void) * Note: we can't disable this interrupt if it has already fired * because then the IRQ will not run at all. */ - if (!((1 << 5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */ + if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */ gpio_disable_interrupt(GPIO_UART0_RX); /* Configure UART0 pins for use in UART peripheral. */ @@ -220,7 +220,7 @@ void uart_exit_dsleep(void) task_enable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART = 40 */ /* power-up/activate UART0 */ - MCHP_UART_ACT(0) |= (1 << 0); + MCHP_UART_ACT(0) |= BIT(0); } void uart_deepsleep_interrupt(enum gpio_signal signal) diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c index 03edeb414e..0533155e08 100644 --- a/chip/mchp/watchdog.c +++ b/chip/mchp/watchdog.c @@ -17,9 +17,9 @@ void watchdog_reload(void) #ifdef CONFIG_WATCHDOG_HELP /* Reload the auxiliary timer */ - MCHP_TMR16_CTL(0) &= ~(1 << 5); + MCHP_TMR16_CTL(0) &= ~BIT(5); MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MCHP_TMR16_CTL(0) |= 1 << 5; + MCHP_TMR16_CTL(0) |= BIT(5); #endif } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); @@ -38,10 +38,10 @@ int watchdog_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0); /* Stop the auxiliary timer if it's running */ - MCHP_TMR16_CTL(0) &= ~(1 << 5); + MCHP_TMR16_CTL(0) &= ~BIT(5); /* Enable auxiliary timer */ - MCHP_TMR16_CTL(0) |= 1 << 0; + MCHP_TMR16_CTL(0) |= BIT(0); val = MCHP_TMR16_CTL(0); @@ -49,10 +49,10 @@ int watchdog_init(void) val = (val & 0xffff) | (47999 << 16); /* No auto restart */ - val &= ~(1 << 3); + val &= ~BIT(3); /* Count down */ - val &= ~(1 << 2); + val &= ~BIT(2); MCHP_TMR16_CTL(0) = val; @@ -63,7 +63,7 @@ int watchdog_init(void) /* Load and start the auxiliary timer */ MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MCHP_TMR16_CNT(0) |= 1 << 5; + MCHP_TMR16_CNT(0) |= BIT(5); #endif /* Clear WDT PCR sleep enable */ @@ -75,7 +75,7 @@ int watchdog_init(void) /* Start watchdog */ #ifdef CONFIG_CHIPSET_DEBUG /* WDT will not count if JTAG TRST# is pulled high by JTAG cable */ - MCHP_WDG_CTL = (1 << 4) | (1 << 0); + MCHP_WDG_CTL = BIT(4) | BIT(0); #else MCHP_WDG_CTL |= 1; #endif diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c index a1210fa274..9026cf8a2e 100644 --- a/chip/mec1322/adc.c +++ b/chip/mec1322/adc.c @@ -30,7 +30,7 @@ static int start_single_and_wait(int timeout) task_waiting = task_get_current(); /* Start conversion */ - MEC1322_ADC_CTRL |= 1 << 1; + MEC1322_ADC_CTRL |= BIT(1); /* Wait for interrupt */ event = task_wait_event(timeout); @@ -60,12 +60,12 @@ int adc_read_channel(enum adc_channel ch) static void adc_init(void) { /* Activate ADC module */ - MEC1322_ADC_CTRL |= 1 << 0; + MEC1322_ADC_CTRL |= BIT(0); /* Enable interrupt */ task_waiting = TASK_ID_INVALID; - MEC1322_INT_ENABLE(17) |= 1 << 10; - MEC1322_INT_BLK_EN |= 1 << 17; + MEC1322_INT_ENABLE(17) |= BIT(10); + MEC1322_INT_BLK_EN |= BIT(17); task_enable_irq(MEC1322_IRQ_ADC_SNGL); } DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); @@ -73,7 +73,7 @@ DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); void adc_interrupt(void) { /* Clear interrupt status bit */ - MEC1322_ADC_CTRL |= 1 << 7; + MEC1322_ADC_CTRL |= BIT(7); if (task_waiting != TASK_ID_INVALID) task_wake(task_waiting); diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index d86f1bc5a7..3f58ef086c 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -103,8 +103,8 @@ DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); */ static void htimer_init(void) { - MEC1322_INT_BLK_EN |= 1 << 17; - MEC1322_INT_ENABLE(17) |= 1 << 20; /* GIRQ=17, aggregator bit = 20 */ + MEC1322_INT_BLK_EN |= BIT(17); + MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ task_enable_irq(MEC1322_IRQ_HTIMER); diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c index b354fea2a4..34617c92bc 100644 --- a/chip/mec1322/dma.c +++ b/chip/mec1322/dma.c @@ -27,8 +27,8 @@ void dma_disable(enum dma_channel channel) { mec1322_dma_chan_t *chan = dma_get_channel(channel); - if (chan->ctrl & (1 << 0)) - chan->ctrl &= ~(1 << 0); + if (chan->ctrl & BIT(0)) + chan->ctrl &= ~BIT(0); if (chan->act == 1) chan->act = 0; @@ -42,9 +42,9 @@ void dma_disable_all(void) for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) { mec1322_dma_chan_t *chan = dma_get_channel(ch); /* Abort any current transfer. */ - chan->ctrl |= (1 << 25); + chan->ctrl |= BIT(25); /* Disable the channel. */ - chan->ctrl &= ~(1 << 0); + chan->ctrl &= ~BIT(0); chan->act = 0; } @@ -69,8 +69,8 @@ static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count, { int xfer_size = (flags >> 20) & 0x7; - if (chan->ctrl & (1 << 0)) - chan->ctrl &= ~(1 << 0); + if (chan->ctrl & BIT(0)) + chan->ctrl &= ~BIT(0); chan->act |= 0x1; chan->dev = (uint32_t)periph; diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c index 9636bc816e..0f40ba22be 100644 --- a/chip/mec1322/fan.c +++ b/chip/mec1322/fan.c @@ -81,15 +81,15 @@ int fan_get_duty(int ch) int fan_get_rpm_mode(int ch) { - return !!(MEC1322_FAN_CFG1 & (1 << 7)); + return !!(MEC1322_FAN_CFG1 & BIT(7)); } void fan_set_rpm_mode(int ch, int rpm_mode) { if (rpm_mode) - MEC1322_FAN_CFG1 |= 1 << 7; + MEC1322_FAN_CFG1 |= BIT(7); else - MEC1322_FAN_CFG1 &= ~(1 << 7); + MEC1322_FAN_CFG1 &= ~BIT(7); clear_status(); } @@ -117,7 +117,7 @@ enum fan_status fan_get_status(int ch) { uint8_t sts = MEC1322_FAN_STATUS; - if (sts & ((1 << 5) | (1 << 1))) + if (sts & (BIT(5) | BIT(1))) return FAN_STATUS_FRUSTRATED; if (fan_get_rpm_actual(ch) == 0) return FAN_STATUS_STOPPED; diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c index 4df46dd6d8..c3b62ad583 100644 --- a/chip/mec1322/gpio.c +++ b/chip/mec1322/gpio.c @@ -37,7 +37,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) while (mask) { i = __builtin_ffs(mask) - 1; val = MEC1322_GPIO_CTL(port, i); - val &= ~((1 << 12) | (1 << 13)); + val &= ~(BIT(12) | BIT(13)); /* mux_control = 0 indicates GPIO */ if (func > 0) val |= (func & 0x3) << 12; @@ -57,7 +57,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(mask); val = MEC1322_GPIO_CTL(gpio_list[signal].port, i); - return (val & (1 << 24)) ? 1 : 0; + return (val & BIT(24)) ? 1 : 0; } void gpio_set_level(enum gpio_signal signal, int value) @@ -70,9 +70,9 @@ void gpio_set_level(enum gpio_signal signal, int value) i = GPIO_MASK_TO_NUM(mask); if (value) - MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= (1 << 16); + MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); else - MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~(1 << 16); + MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); } void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) @@ -89,16 +89,16 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) * when changing the line to an output. */ if (flags & GPIO_OPEN_DRAIN) - val |= (1 << 8); + val |= BIT(8); else - val &= ~(1 << 8); + val &= ~BIT(8); if (flags & GPIO_OUTPUT) { - val |= (1 << 9); - val &= ~(1 << 10); + val |= BIT(9); + val &= ~BIT(10); } else { - val &= ~(1 << 9); - val |= (1 << 10); + val &= ~BIT(9); + val |= BIT(10); } /* Handle pullup / pulldown */ @@ -111,9 +111,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up interrupt */ if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - val |= (1 << 7); + val |= BIT(7); else - val &= ~(1 << 7); + val &= ~BIT(7); val &= ~(0x7 << 4); @@ -130,9 +130,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up level */ if (flags & GPIO_HIGH) - val |= (1 << 16); + val |= BIT(16); else if (flags & GPIO_LOW) - val &= ~(1 << 16); + val &= ~BIT(16); MEC1322_GPIO_CTL(port, i) = val; } diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c index be9ffac1ea..4adaa38516 100644 --- a/chip/mec1322/hwtimer.c +++ b/chip/mec1322/hwtimer.c @@ -17,7 +17,7 @@ void __hw_clock_event_set(uint32_t deadline) { MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - (0xffffffff - deadline); - MEC1322_TMR32_CTL(1) |= (1 << 5); + MEC1322_TMR32_CTL(1) |= BIT(5); } uint32_t __hw_clock_event_get(void) @@ -27,7 +27,7 @@ uint32_t __hw_clock_event_get(void) void __hw_clock_event_clear(void) { - MEC1322_TMR32_CTL(1) &= ~(1 << 5); + MEC1322_TMR32_CTL(1) &= ~BIT(5); } uint32_t __hw_clock_source_read(void) @@ -37,9 +37,9 @@ uint32_t __hw_clock_source_read(void) void __hw_clock_source_set(uint32_t ts) { - MEC1322_TMR32_CTL(0) &= ~(1 << 5); + MEC1322_TMR32_CTL(0) &= ~BIT(5); MEC1322_TMR32_CNT(0) = 0xffffffff - ts; - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); } static void __hw_clock_source_irq(int timer_id) @@ -60,10 +60,10 @@ static void configure_timer(int timer_id) uint32_t val; /* Ensure timer is not running */ - MEC1322_TMR32_CTL(timer_id) &= ~(1 << 5); + MEC1322_TMR32_CTL(timer_id) &= ~BIT(5); /* Enable timer */ - MEC1322_TMR32_CTL(timer_id) |= (1 << 0); + MEC1322_TMR32_CTL(timer_id) |= BIT(0); val = MEC1322_TMR32_CTL(timer_id); @@ -94,16 +94,16 @@ int __hw_clock_source_init(uint32_t start_t) MEC1322_TMR32_CNT(0) = 0xffffffff - start_t; /* Auto restart */ - MEC1322_TMR32_CTL(0) |= (1 << 3); + MEC1322_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); /* Enable interrupt */ task_enable_irq(MEC1322_IRQ_TIMER32_0); task_enable_irq(MEC1322_IRQ_TIMER32_1); - MEC1322_INT_ENABLE(23) |= (1 << 4) | (1 << 5); - MEC1322_INT_BLK_EN |= (1 << 23); + MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5); + MEC1322_INT_BLK_EN |= BIT(23); return MEC1322_IRQ_TIMER32_1; } diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index ce3e618c24..2c22256d81 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -21,22 +21,22 @@ #define I2C_CLOCK 16000000 /* 16 MHz */ /* Status */ -#define STS_NBB (1 << 0) /* Bus busy */ -#define STS_LAB (1 << 1) /* Arbitration lost */ -#define STS_LRB (1 << 3) /* Last received bit */ -#define STS_BER (1 << 4) /* Bus error */ -#define STS_PIN (1 << 7) /* Pending interrupt */ +#define STS_NBB BIT(0) /* Bus busy */ +#define STS_LAB BIT(1) /* Arbitration lost */ +#define STS_LRB BIT(3) /* Last received bit */ +#define STS_BER BIT(4) /* Bus error */ +#define STS_PIN BIT(7) /* Pending interrupt */ /* Control */ -#define CTRL_ACK (1 << 0) /* Acknowledge */ -#define CTRL_STO (1 << 1) /* STOP */ -#define CTRL_STA (1 << 2) /* START */ -#define CTRL_ENI (1 << 3) /* Enable interrupt */ -#define CTRL_ESO (1 << 6) /* Enable serial output */ -#define CTRL_PIN (1 << 7) /* Pending interrupt not */ +#define CTRL_ACK BIT(0) /* Acknowledge */ +#define CTRL_STO BIT(1) /* STOP */ +#define CTRL_STA BIT(2) /* START */ +#define CTRL_ENI BIT(3) /* Enable interrupt */ +#define CTRL_ESO BIT(6) /* Enable serial output */ +#define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_IDLE (1 << 29) /* i2c bus is idle */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Maximum transfer of a SMBUS block transfer */ @@ -116,21 +116,21 @@ static void configure_controller(int controller, int kbps) configure_controller_speed(controller, kbps); MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_ENI; - MEC1322_I2C_CONFIG(controller) |= 1 << 10; /* ENAB */ + MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */ /* Enable interrupt */ - MEC1322_I2C_CONFIG(controller) |= 1 << 29; /* ENIDI */ + MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */ MEC1322_INT_ENABLE(12) |= (1 << controller); - MEC1322_INT_BLK_EN |= 1 << 12; + MEC1322_INT_BLK_EN |= BIT(12); } static void reset_controller(int controller) { int i; - MEC1322_I2C_CONFIG(controller) |= 1 << 9; + MEC1322_I2C_CONFIG(controller) |= BIT(9); udelay(100); - MEC1322_I2C_CONFIG(controller) &= ~(1 << 9); + MEC1322_I2C_CONFIG(controller) &= ~BIT(9); for (i = 0; i < i2c_ports_used; ++i) if (controller == i2c_port_to_controller(i2c_ports[i].port)) { diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c index 3269af2cf9..a8a1e6b124 100644 --- a/chip/mec1322/keyboard_raw.c +++ b/chip/mec1322/keyboard_raw.c @@ -19,8 +19,8 @@ void keyboard_raw_init(void) gpio_config_module(MODULE_KEYBOARD_SCAN, 1); /* Enable keyboard scan interrupt */ - MEC1322_INT_ENABLE(17) |= 1 << 21; - MEC1322_INT_BLK_EN |= 1 << 17; + MEC1322_INT_ENABLE(17) |= BIT(21); + MEC1322_INT_BLK_EN |= BIT(17); MEC1322_KS_KSI_INT_EN = 0xff; } @@ -32,19 +32,19 @@ void keyboard_raw_task_start(void) test_mockable void keyboard_raw_drive_column(int out) { if (out == KEYBOARD_COLUMN_ALL) { - MEC1322_KS_KSO_SEL = 1 << 5; /* KSEN=0, KSALL=1 */ + MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 1); #endif } else if (out == KEYBOARD_COLUMN_NONE) { - MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 0); #endif } else { #ifdef CONFIG_KEYBOARD_COL2_INVERTED if (out == 2) { - MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ gpio_set_level(GPIO_KBD_KSO2, 1); } else { MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; @@ -84,5 +84,5 @@ DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1); int keyboard_raw_is_input_low(int port, int id) { - return (MEC1322_GPIO_CTL(port, id) & (1 << 24)) == 0; + return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0; } diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c index 86a4949e17..7dacfc3077 100644 --- a/chip/mec1322/lfw/ec_lfw.c +++ b/chip/mec1322/lfw/ec_lfw.c @@ -48,10 +48,10 @@ void timer_init() uint32_t val = 0; /* Ensure timer is not running */ - MEC1322_TMR32_CTL(0) &= ~(1 << 5); + MEC1322_TMR32_CTL(0) &= ~BIT(5); /* Enable timer */ - MEC1322_TMR32_CTL(0) |= (1 << 0); + MEC1322_TMR32_CTL(0) |= BIT(0); val = MEC1322_TMR32_CTL(0); @@ -67,10 +67,10 @@ void timer_init() MEC1322_TMR32_CNT(0) = 0xffffffff; /* Auto restart */ - MEC1322_TMR32_CTL(0) |= (1 << 3); + MEC1322_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); } @@ -146,7 +146,7 @@ void uart_write_c(char c) uart_write_c('\r'); /* Wait for space in transmit FIFO. */ - while (!(MEC1322_UART_LSR & (1 << 5))) + while (!(MEC1322_UART_LSR & BIT(5))) ; MEC1322_UART_TB = c; } @@ -181,31 +181,31 @@ void jump_to_image(uintptr_t init_addr) void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~(1 << 1); + MEC1322_UART_CFG &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~(1 << 0); + MEC1322_UART_CFG &= ~BIT(0); /* Set DLAB = 1 */ - MEC1322_UART_LCR |= (1 << 7); + MEC1322_UART_LCR |= BIT(7); /* PBRG0/PBRG1 */ MEC1322_UART_PBRG0 = 1; MEC1322_UART_PBRG1 = 0; /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~(1 << 7); + MEC1322_UART_LCR &= ~BIT(7); /* Set word length to 8-bit */ - MEC1322_UART_LCR |= (1 << 0) | (1 << 1); + MEC1322_UART_LCR |= BIT(0) | BIT(1); /* Enable FIFO */ - MEC1322_UART_FCR = (1 << 0); + MEC1322_UART_FCR = BIT(0); /* Activate UART */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); gpio_config_module(MODULE_UART, 1); } diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 5d2d57f834..829f91a85c 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -190,23 +190,23 @@ static void setup_lpc(void) gpio_config_module(MODULE_LPC, 1); /* Set up interrupt on LRESET# deassert */ - MEC1322_INT_SOURCE(19) = 1 << 1; - MEC1322_INT_ENABLE(19) |= 1 << 1; - MEC1322_INT_BLK_EN |= 1 << 19; + MEC1322_INT_SOURCE(19) = BIT(1); + MEC1322_INT_ENABLE(19) |= BIT(1); + MEC1322_INT_BLK_EN |= BIT(19); task_enable_irq(MEC1322_IRQ_GIRQ19); /* Set up ACPI0 for 0x62/0x66 */ MEC1322_LPC_ACPI_EC0_BAR = 0x00628304; - MEC1322_INT_ENABLE(15) |= 1 << 6; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(6); + MEC1322_INT_BLK_EN |= BIT(15); /* Clear STATUS_PROCESSING bit in case it was set during sysjump */ MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); /* Set up ACPI1 for 0x200/0x204 */ MEC1322_LPC_ACPI_EC1_BAR = 0x02008407; - MEC1322_INT_ENABLE(15) |= 1 << 8; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(8); + MEC1322_INT_BLK_EN |= BIT(15); MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF); @@ -214,24 +214,24 @@ static void setup_lpc(void) MEC1322_LPC_8042_BAR = 0x00608104; /* Set up indication of Auxiliary sts */ - MEC1322_8042_KB_CTRL |= 1 << 7; + MEC1322_8042_KB_CTRL |= BIT(7); MEC1322_8042_ACT |= 1; - MEC1322_INT_ENABLE(15) |= ((1 << 13) | (1 << 14)); - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14)); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_8042EM_IBF); task_enable_irq(MEC1322_IRQ_8042EM_OBF); #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MEC1322_8042_KB_CTRL |= (1 << 5); + MEC1322_8042_KB_CTRL |= BIT(5); MEC1322_LPC_SIRQ(1) = 0x01; #endif /* Set up EMI module for memory mapped region, base address 0x800 */ MEC1322_LPC_EMI_BAR = 0x0800800f; - MEC1322_INT_ENABLE(15) |= 1 << 2; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(2); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_EMI); /* Access data RAM through alias address */ @@ -295,7 +295,7 @@ DECLARE_DEFERRED(lpc_chipset_reset); void girq19_interrupt(void) { /* Check interrupt result for LRESET# trigger */ - if (MEC1322_INT_RESULT(19) & (1 << 1)) { + if (MEC1322_INT_RESULT(19) & BIT(1)) { /* Initialize LPC module when LRESET# is deasserted */ if (!lpc_get_pltrst_asserted()) { setup_lpc(); @@ -313,7 +313,7 @@ void girq19_interrupt(void) lpc_get_pltrst_asserted() ? "" : "de"); /* Clear interrupt source */ - MEC1322_INT_SOURCE(19) = 1 << 1; + MEC1322_INT_SOURCE(19) = BIT(1); } } DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1); @@ -423,7 +423,7 @@ void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) keyboard_host_write(MEC1322_8042_H2E, - MEC1322_8042_STS & (1 << 3)); + MEC1322_8042_STS & BIT(3)); task_wake(TASK_ID_KEYPROTO); } DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1); @@ -437,12 +437,12 @@ DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1); int lpc_keyboard_has_char(void) { - return (MEC1322_8042_STS & (1 << 0)) ? 1 : 0; + return (MEC1322_8042_STS & BIT(0)) ? 1 : 0; } int lpc_keyboard_input_pending(void) { - return (MEC1322_8042_STS & (1 << 1)) ? 1 : 0; + return (MEC1322_8042_STS & BIT(1)) ? 1 : 0; } void lpc_keyboard_put_char(uint8_t chr, int send_irq) @@ -506,7 +506,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c index fa4fd36a4f..df4583ed8b 100644 --- a/chip/mec1322/port80.c +++ b/chip/mec1322/port80.c @@ -31,7 +31,7 @@ static void port_80_interrupt_enable(void) /* Enable the interrupt. */ task_enable_irq(MEC1322_IRQ_TIMER16_1); /* Enable and start the timer. */ - MEC1322_TMR16_CTL(1) |= 1 | (1 << 5); + MEC1322_TMR16_CTL(1) |= 1 | BIT(5); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); @@ -61,9 +61,9 @@ static void port_80_interrupt_init(void) val = MEC1322_TMR16_CTL(1); val = (val & 0xFFFF) | (47 << 16); /* Automatically restart the timer. */ - val |= (1 << 3); + val |= BIT(3); /* The counter should decrement. */ - val &= ~(1 << 2); + val &= ~BIT(2); MEC1322_TMR16_CTL(1) = val; /* Set the reload value(us). */ @@ -73,12 +73,12 @@ static void port_80_interrupt_init(void) MEC1322_TMR16_STS(1) |= 1; /* Clear any pending interrupt. */ - MEC1322_INT_SOURCE(23) = (1 << 1); + MEC1322_INT_SOURCE(23) = BIT(1); /* Enable IRQ vector 23. */ - MEC1322_INT_BLK_EN |= (1 << 23); + MEC1322_INT_BLK_EN |= BIT(23); /* Enable the interrupt. */ MEC1322_TMR16_IEN(1) |= 1; - MEC1322_INT_ENABLE(23) = (1 << 1); + MEC1322_INT_ENABLE(23) = BIT(1); port_80_interrupt_enable(); } @@ -89,7 +89,7 @@ void port_80_interrupt(void) int data; MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */ - if ((1 << 1) & MEC1322_INT_RESULT(23)) { + if (BIT(1) & MEC1322_INT_RESULT(23)) { data = port_80_read(); if (data != PORT_80_IGNORE) { diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c index 64547490f4..314f92fb6a 100644 --- a/chip/mec1322/pwm.c +++ b/chip/mec1322/pwm.c @@ -67,8 +67,8 @@ static void pwm_configure(int ch, int active_low, int clock_low) * clock_low=1 selects the 100kHz_Clk source */ MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? (1 << 2) : 0) | - (clock_low ? (1 << 1) : 0); + (active_low ? BIT(2) : 0) | + (clock_low ? BIT(1) : 0); } static void pwm_init(void) diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index c36e72b089..877a48ff7a 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -28,10 +28,10 @@ /* Command all blocks to sleep */ #define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 #define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) -#define MEC1322_PCR_EC_SLP_EN_PWM3 (1 << 22) -#define MEC1322_PCR_EC_SLP_EN_PWM2 (1 << 21) -#define MEC1322_PCR_EC_SLP_EN_PWM1 (1 << 20) -#define MEC1322_PCR_EC_SLP_EN_PWM0 (1 << 4) +#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) +#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) +#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) +#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) /* Allow all blocks to request clocks */ #define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) #define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) @@ -59,8 +59,8 @@ #define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) /* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ -#define MEC1322_PWR_RST_STS_VCC1 (1 << 6) -#define MEC1322_PWR_RST_STS_VBAT (1 << 5) +#define MEC1322_PWR_RST_STS_VCC1 BIT(6) +#define MEC1322_PWR_RST_STS_VBAT BIT(5) /* EC Subsystem */ #define MEC1322_EC_BASE 0x4000fc00 @@ -106,7 +106,7 @@ #define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) /* Bit defines for MEC1322_UART_LSR */ -#define MEC1322_LSR_TX_EMPTY (1 << 5) +#define MEC1322_LSR_TX_EMPTY BIT(5) /* GPIO */ #define MEC1322_GPIO_BASE 0x40081000 @@ -152,7 +152,7 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) /* Bit definition for MEC1322_VBAT_STS */ -#define MEC1322_VBAT_STS_WDT (1 << 5) +#define MEC1322_VBAT_STS_WDT BIT(5) /* Miscellaneous firmware control fields * scratch pad index cannot be more than 16 as @@ -416,14 +416,14 @@ typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t; #define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE) /* Bits for DMA channel regs */ -#define MEC1322_DMA_ACT_EN (1 << 0) +#define MEC1322_DMA_ACT_EN BIT(0) #define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) -#define MEC1322_DMA_INC_DEV (1 << 17) -#define MEC1322_DMA_INC_MEM (1 << 16) +#define MEC1322_DMA_INC_DEV BIT(17) +#define MEC1322_DMA_INC_MEM BIT(16) #define MEC1322_DMA_DEV(x) ((x) << 9) -#define MEC1322_DMA_TO_DEV (1 << 8) -#define MEC1322_DMA_DONE (1 << 2) -#define MEC1322_DMA_RUN (1 << 0) +#define MEC1322_DMA_TO_DEV BIT(8) +#define MEC1322_DMA_DONE BIT(2) +#define MEC1322_DMA_RUN BIT(0) /* IRQ Numbers */ diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c index 705a95c44e..f7211f7289 100644 --- a/chip/mec1322/spi.c +++ b/chip/mec1322/spi.c @@ -83,14 +83,14 @@ int spi_transaction_async(const struct spi_device_t *spi_device, gpio_set_level(spi_device->gpio_cs, 0); /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~(1 << 5); + MEC1322_SPI_CR(port) &= ~BIT(5); ret = spi_tx(port, txdata, txlen); if (ret != EC_SUCCESS) return ret; /* Enable auto read */ - MEC1322_SPI_CR(port) |= 1 << 5; + MEC1322_SPI_CR(port) |= BIT(5); if (rxlen != 0) { dma_start_rx(&spi_rx_option[port], rxlen, rxdata); @@ -108,7 +108,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) timestamp_t deadline; /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~(1 << 5); + MEC1322_SPI_CR(port) &= ~BIT(5); deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; /* Wait for FIFO empty SPISR_TXBE */ diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c index 449d234343..4431ee6954 100644 --- a/chip/mec1322/system.c +++ b/chip/mec1322/system.c @@ -88,7 +88,7 @@ void system_pre_init(void) MEC1322_EC_TRACE_EN &= ~1; /* Deassert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL &= ~(1 << 0); + MEC1322_PCR_PWR_RST_CTL &= ~BIT(0); spi_enable(CONFIG_SPI_FLASH_PORT, 1); } @@ -323,8 +323,8 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) } if (seconds || microseconds) { - MEC1322_INT_BLK_EN |= 1 << 17; - MEC1322_INT_ENABLE(17) |= 1 << 20; + MEC1322_INT_BLK_EN |= BIT(17); + MEC1322_INT_ENABLE(17) |= BIT(20); interrupt_enable(); task_enable_irq(MEC1322_IRQ_HTIMER); if (seconds > 2) { diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c index ddbe113c7d..af4ccc5b46 100644 --- a/chip/mec1322/uart.c +++ b/chip/mec1322/uart.c @@ -29,7 +29,7 @@ int uart_init_done(void) void uart_tx_start(void) { /* If interrupt is already enabled, nothing to do */ - if (MEC1322_UART_IER & (1 << 1)) + if (MEC1322_UART_IER & BIT(1)) return; /* Do not allow deep sleep while transmit in progress */ @@ -41,13 +41,13 @@ void uart_tx_start(void) * UART where the FIFO only triggers the interrupt when its * threshold is _crossed_, not just met. */ - MEC1322_UART_IER |= (1 << 1); + MEC1322_UART_IER |= BIT(1); task_trigger_irq(MEC1322_IRQ_UART); } void uart_tx_stop(void) { - MEC1322_UART_IER &= ~(1 << 1); + MEC1322_UART_IER &= ~BIT(1); /* Re-allow deep sleep */ enable_sleep(SLEEP_MASK_UART); @@ -77,7 +77,7 @@ int uart_tx_in_progress(void) int uart_rx_available(void) { - return MEC1322_UART_LSR & (1 << 0); + return MEC1322_UART_LSR & BIT(0); } void uart_write_char(char c) @@ -97,7 +97,7 @@ int uart_read_char(void) static void uart_clear_rx_fifo(int channel) { - MEC1322_UART_FCR = (1 << 0) | (1 << 1); + MEC1322_UART_FCR = BIT(0) | BIT(1); } /** @@ -114,31 +114,31 @@ DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1); void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~(1 << 1); + MEC1322_UART_CFG &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~(1 << 0); + MEC1322_UART_CFG &= ~BIT(0); /* Set DLAB = 1 */ - MEC1322_UART_LCR |= (1 << 7); + MEC1322_UART_LCR |= BIT(7); /* PBRG0/PBRG1 */ MEC1322_UART_PBRG0 = 1; MEC1322_UART_PBRG1 = 0; /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~(1 << 7); + MEC1322_UART_LCR &= ~BIT(7); /* Set word length to 8-bit */ - MEC1322_UART_LCR |= (1 << 0) | (1 << 1); + MEC1322_UART_LCR |= BIT(0) | BIT(1); /* Enable FIFO */ - MEC1322_UART_FCR = (1 << 0); + MEC1322_UART_FCR = BIT(0); /* Activate UART */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); /* clock_enable_peripheral(CGC_OFFSET_UART, mask, @@ -150,10 +150,10 @@ void uart_init(void) * Enable interrupts for UART0. */ uart_clear_rx_fifo(0); - MEC1322_UART_IER |= (1 << 0); - MEC1322_UART_MCR |= (1 << 3); - MEC1322_INT_ENABLE(15) |= (1 << 0); - MEC1322_INT_BLK_EN |= (1 << 15); + MEC1322_UART_IER |= BIT(0); + MEC1322_UART_MCR |= BIT(3); + MEC1322_INT_ENABLE(15) |= BIT(0); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_UART); init_done = 1; @@ -172,7 +172,7 @@ void uart_enter_dsleep(void) gpio_reset(GPIO_UART0_RX); /* power-down/de-activate UART0 */ - MEC1322_UART_ACT &= ~(1 << 0); + MEC1322_UART_ACT &= ~BIT(0); /* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */ MEC1322_INT_SOURCE(8) = (1<<18); @@ -191,7 +191,7 @@ void uart_exit_dsleep(void) * Note: we can't disable this interrupt if it has already fired * because then the IRQ will not run at all. */ - if (!((1 << 18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ + if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ gpio_disable_interrupt(GPIO_UART0_RX); /* Configure UART0 pins for use in UART peripheral. */ @@ -202,7 +202,7 @@ void uart_exit_dsleep(void) task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */ /* power-up/activate UART0 */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); } void uart_deepsleep_interrupt(enum gpio_signal signal) diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c index a92b57f8a2..07724ca5ee 100644 --- a/chip/mec1322/watchdog.c +++ b/chip/mec1322/watchdog.c @@ -16,9 +16,9 @@ void watchdog_reload(void) #ifdef CONFIG_WATCHDOG_HELP /* Reload the auxiliary timer */ - MEC1322_TMR16_CTL(0) &= ~(1 << 5); + MEC1322_TMR16_CTL(0) &= ~BIT(5); MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CTL(0) |= 1 << 5; + MEC1322_TMR16_CTL(0) |= BIT(5); #endif } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); @@ -34,10 +34,10 @@ int watchdog_init(void) */ /* Stop the auxiliary timer if it's running */ - MEC1322_TMR16_CTL(0) &= ~(1 << 5); + MEC1322_TMR16_CTL(0) &= ~BIT(5); /* Enable auxiliary timer */ - MEC1322_TMR16_CTL(0) |= 1 << 0; + MEC1322_TMR16_CTL(0) |= BIT(0); val = MEC1322_TMR16_CTL(0); @@ -45,22 +45,22 @@ int watchdog_init(void) val = (val & 0xffff) | (47999 << 16); /* No auto restart */ - val &= ~(1 << 3); + val &= ~BIT(3); /* Count down */ - val &= ~(1 << 2); + val &= ~BIT(2); MEC1322_TMR16_CTL(0) = val; /* Enable interrupt from auxiliary timer */ MEC1322_TMR16_IEN(0) |= 1; task_enable_irq(MEC1322_IRQ_TIMER16_0); - MEC1322_INT_ENABLE(23) |= 1 << 0; - MEC1322_INT_BLK_EN |= 1 << 23; + MEC1322_INT_ENABLE(23) |= BIT(0); + MEC1322_INT_BLK_EN |= BIT(23); /* Load and start the auxiliary timer */ MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CNT(0) |= 1 << 5; + MEC1322_TMR16_CNT(0) |= BIT(5); #endif /* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */ diff --git a/chip/mt_scp/ipi.c b/chip/mt_scp/ipi.c index 20ce6d4586..d41b39f4d4 100644 --- a/chip/mt_scp/ipi.c +++ b/chip/mt_scp/ipi.c @@ -248,7 +248,7 @@ static int ipi_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions |= (1 << 3); + r->protocol_versions |= BIT(3); r->max_request_packet_size = IPI_MAX_REQUEST_SIZE; r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE; diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 2045f8ff30..07634562a9 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -76,8 +76,8 @@ /* SCP to SPM interrupt */ #define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20) -#define SPM_INT_A2SPM (1 << 0) -#define SPM_INT_B2SPM (1 << 1) +#define SPM_INT_A2SPM BIT(0) +#define SPM_INT_B2SPM BIT(1) #define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24) /* @@ -101,8 +101,8 @@ */ #define SCP_PWRON_STATE SCP_GPR[1] #define PWRON_DEFAULT 0xdee80000 -#define PWRON_WATCHDOG (1 << 0) -#define PWRON_RESET (1 << 1) +#define PWRON_WATCHDOG BIT(0) +#define PWRON_RESET BIT(1) /* AP defined features */ #define SCP_EXPECTED_FREQ SCP_GPR[3] #define SCP_CURRENT_FREQ SCP_GPR[4] @@ -119,17 +119,17 @@ #define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0) #define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4) #define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8) -#define P_CACHE_SLP_PROT_EN (1 << 3) -#define D_CACHE_SLP_PROT_EN (1 << 4) +#define P_CACHE_SLP_PROT_EN BIT(3) +#define D_CACHE_SLP_PROT_EN BIT(4) #define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC) #define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0) -#define ENABLE_SPM_MASK_VREQ (1 << 28) -#define DISABLE_REMAP (1 << 22) -#define DISABLE_JTAG (1 << 21) -#define DISABLE_AP_TCM (1 << 20) +#define ENABLE_SPM_MASK_VREQ BIT(28) +#define DISABLE_REMAP BIT(22) +#define DISABLE_JTAG BIT(21) +#define DISABLE_AP_TCM BIT(20) #define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4) -#define DDREN_FIX_VALUE (1 << 28) -#define AUTO_DDREN (1 << 18) +#define DDREN_FIX_VALUE BIT(28) +#define AUTO_DDREN BIT(18) /* Memory remap control */ /* @@ -191,7 +191,7 @@ #define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000) #define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE) #define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04) -#define IPC0_IRQ_EN (1 << 0) +#define IPC0_IRQ_EN BIT(0) #define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08) #define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C) #define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10) @@ -210,12 +210,12 @@ #define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04) #define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08) #define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C) -#define TIMER_IRQ_ENABLE (1 << 0) -#define TIMER_IRQ_STATUS (1 << 4) -#define TIMER_IRQ_CLEAR (1 << 5) +#define TIMER_IRQ_ENABLE BIT(0) +#define TIMER_IRQ_STATUS BIT(4) +#define TIMER_IRQ_CLEAR BIT(5) #define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40) #define TIMER_CLK_32K (0 << 4) -#define TIMER_CLK_26M (1 << 4) +#define TIMER_CLK_26M BIT(4) #define TIMER_CLK_BCLK (2 << 4) #define TIMER_CLK_PCLK (3 << 4) #define TIMER_CLK_MASK (3 << 4) @@ -228,9 +228,9 @@ #define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10) #define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14) #define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18) -#define OSTIMER_LATCH0_EN (1 << 5) -#define OSTIMER_LATCH1_EN (1 << 13) -#define OSTIMER_LATCH2_EN (1 << 21) +#define OSTIMER_LATCH0_EN BIT(5) +#define OSTIMER_LATCH1_EN BIT(13) +#define OSTIMER_LATCH2_EN BIT(21) #define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20) #define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24) #define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28) @@ -248,11 +248,11 @@ #define CLK_SEL_ULPOSC_2 3 #define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) -#define EN_CLK_SYS (1 << 0) /* System clock */ -#define EN_CLK_HIGH (1 << 1) /* ULPOSC */ -#define CG_CLK_HIGH (1 << 2) -#define EN_SYS_IRQ (1 << 16) -#define EN_HIGH_IRQ (1 << 17) +#define EN_CLK_SYS BIT(0) /* System clock */ +#define EN_CLK_HIGH BIT(1) /* ULPOSC */ +#define CG_CLK_HIGH BIT(2) +#define EN_SYS_IRQ BIT(16) +#define EN_HIGH_IRQ BIT(17) #define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08) #define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C) #define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10) @@ -283,43 +283,43 @@ * voltage after returning from sleep mode. */ #define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20) -#define EN_SLEEP_CTRL (1 << 0) +#define EN_SLEEP_CTRL BIT(0) #define VREQ_COUNTER_MASK 0xfe #define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK) -#define SPM_SLEEP_MODE (1 << 8) -#define SPM_SLEEP_MODE_CLK_AO (1 << 9) +#define SPM_SLEEP_MODE BIT(8) +#define SPM_SLEEP_MODE_CLK_AO BIT(9) #define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24) #define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28) #define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C) #define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30) -#define CG_TIMER_M (1 << 0) -#define CG_TIMER_B (1 << 1) -#define CG_MAD_M (1 << 2) -#define CG_I2C_M (1 << 3) -#define CG_I2C_B (1 << 4) -#define CG_GPIO_M (1 << 5) -#define CG_AP2P_M (1 << 6) -#define CG_UART_M (1 << 7) -#define CG_UART_B (1 << 8) -#define CG_UART_RSTN (1 << 9) -#define CG_UART1_M (1 << 10) -#define CG_UART1_B (1 << 11) -#define CG_UART1_RSTN (1 << 12) -#define CG_SPI0 (1 << 13) -#define CG_SPI1 (1 << 14) -#define CG_SPI2 (1 << 15) -#define CG_DMA_CH0 (1 << 16) -#define CG_DMA_CH1 (1 << 17) -#define CG_DMA_CH2 (1 << 18) -#define CG_DMA_CH3 (1 << 19) -#define CG_TWAM (1 << 20) -#define CG_CACHE_I_CTRL (1 << 21) -#define CG_CACHE_D_CTRL (1 << 22) +#define CG_TIMER_M BIT(0) +#define CG_TIMER_B BIT(1) +#define CG_MAD_M BIT(2) +#define CG_I2C_M BIT(3) +#define CG_I2C_B BIT(4) +#define CG_GPIO_M BIT(5) +#define CG_AP2P_M BIT(6) +#define CG_UART_M BIT(7) +#define CG_UART_B BIT(8) +#define CG_UART_RSTN BIT(9) +#define CG_UART1_M BIT(10) +#define CG_UART1_B BIT(11) +#define CG_UART1_RSTN BIT(12) +#define CG_SPI0 BIT(13) +#define CG_SPI1 BIT(14) +#define CG_SPI2 BIT(15) +#define CG_DMA_CH0 BIT(16) +#define CG_DMA_CH1 BIT(17) +#define CG_DMA_CH2 BIT(18) +#define CG_DMA_CH3 BIT(19) +#define CG_TWAM BIT(20) +#define CG_CACHE_I_CTRL BIT(21) +#define CG_CACHE_D_CTRL BIT(22) #define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34) -#define PMICW_SLEEP_REQ (1 << 0) -#define PMICW_SLEEP_ACK (1 << 4) -#define PMICW_CLK_MUX (1 << 8) -#define PMICW_DCM (1 << 9) +#define PMICW_SLEEP_REQ BIT(0) +#define PMICW_SLEEP_ACK BIT(4) +#define PMICW_CLK_MUX BIT(8) +#define PMICW_DCM BIT(9) #define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38) #define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C) #define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40) @@ -337,11 +337,11 @@ #define CLK_HIGH_CORE_CG (1 << 1) #define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64) #define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C) -#define HIGH_AO (1 << 0) -#define HIGH_CG_AO (1 << 2) -#define HIGH_CORE_AO (1 << 4) -#define HIGH_CORE_DIS_SUB (1 << 5) -#define HIGH_CORE_CG_AO (1 << 6) +#define HIGH_AO BIT(0) +#define HIGH_CG_AO BIT(2) +#define HIGH_CORE_AO BIT(4) +#define HIGH_CORE_DIS_SUB BIT(5) +#define HIGH_CORE_CG_AO BIT(6) #define HIGH_FINAL_VAL_MASK 0x1f00 #define HIGH_FINAL_VAL_DEFAULT 0x300 #define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80) @@ -402,9 +402,9 @@ #define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000) #define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000) #define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x)) -#define SCP_CACHE_CON_MCEN (1 << 0) -#define SCP_CACHE_CON_CNTEN0 (1 << 2) -#define SCP_CACHE_CON_CNTEN1 (1 << 3) +#define SCP_CACHE_CON_MCEN BIT(0) +#define SCP_CACHE_CON_CNTEN0 BIT(2) +#define SCP_CACHE_CON_CNTEN1 BIT(3) #define SCP_CACHE_CON_CACHESIZE_SHIFT 8 #define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) #define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT) @@ -413,7 +413,7 @@ #define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) #define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04) -#define SCP_CACHE_OP_EN (1 << 0) +#define SCP_CACHE_OP_EN BIT(0) #define SCP_CACHE_OP_OP_SHIFT 1 #define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT) @@ -445,12 +445,12 @@ #define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040) #define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + \ (reg)*4) -#define SCP_CACHE_ENTRY_C (1 << 8) +#define SCP_CACHE_ENTRY_C BIT(8) #define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12) /* ARMV7 regs */ #define ARM_SCB_SCR REG32(0xE000ED10) -#define SCR_DEEPSLEEP (1 << 2) +#define SCR_DEEPSLEEP BIT(2) /* AP regs */ #define AP_BASE 0xA0000000 @@ -530,11 +530,11 @@ #define OSC_IBAND_MASK (0x7f << 6) #define OSC_FBAND_MASK (0x0f << 13) #define OSC_DIV_MASK (0x1f << 17) -#define OSC_CP_EN (1 << 23) +#define OSC_CP_EN BIT(23) #define OSC_RESERVED_MASK (0xff << 24) /* AP_ULPOSC_CON[1,3] */ #define OSC_MOD_MASK (0x03 << 0) -#define OSC_DIV2_EN (1 << 2) +#define OSC_DIV2_EN BIT(2) #define DUMMY_GPIO_BANK 0 @@ -556,7 +556,7 @@ #define SCP_WDT_FREQ 33825 #define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ #define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000) -#define SCP_WDT_ENABLE (1 << 31) +#define SCP_WDT_ENABLE BIT(31) #define SCP_WDT_RELOAD SCP_WDT_REG(4) #define SCP_WDT_RELOAD_VALUE 1 diff --git a/chip/mt_scp/serial_reg.h b/chip/mt_scp/serial_reg.h index a23b19ded3..5344566272 100644 --- a/chip/mt_scp/serial_reg.h +++ b/chip/mt_scp/serial_reg.h @@ -22,13 +22,13 @@ #define UART_DATA(n) UART_REG(n, 0) /* (Write) Interrupt enable register */ #define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI (1 << 0) /* Recv data int */ -#define UART_IER_THRI (1 << 1) /* Xmit holding register int */ -#define UART_IER_RLSI (1 << 2) /* Rcvr line status int */ -#define UART_IER_MSI (1 << 3) /* Modem status int */ +#define UART_IER_RDI BIT(0) /* Recv data int */ +#define UART_IER_THRI BIT(1) /* Xmit holding register int */ +#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ +#define UART_IER_MSI BIT(3) /* Modem status int */ /* (Read) Interrupt ID register */ #define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT (1 << 0) /* No int pending */ +#define UART_IIR_NO_INT BIT(0) /* No int pending */ #define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ #define UART_IIR_MSI 0x00 #define UART_IIR_THRI 0x02 @@ -37,10 +37,10 @@ #define UART_IIR_BUSY 0x07 /* DW APB busy */ /* (Write) FIFO control register */ #define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO (1 << 0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR (1 << 1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT (1 << 2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT (1 << 3) +#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* FIFO trigger levels */ #define UART_FCR_T_TRIG_00 0x00 #define UART_FCR_T_TRIG_01 0x10 @@ -56,24 +56,24 @@ #define UART_LCR_WLEN6 1 #define UART_LCR_WLEN7 2 #define UART_LCR_WLEN8 3 -#define UART_LCR_STOP (1 << 2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY (1 << 3) /* Parity enable */ -#define UART_LCR_EPAR (1 << 4) /* Even parity */ -#define UART_LCR_SPAR (1 << 5) /* Stick parity */ -#define UART_LCR_SBC (1 << 6) /* Set break control */ -#define UART_LCR_DLAB (1 << 7) /* Divisor latch access */ +#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* Parity enable */ +#define UART_LCR_EPAR BIT(4) /* Even parity */ +#define UART_LCR_SPAR BIT(5) /* Stick parity */ +#define UART_LCR_SBC BIT(6) /* Set break control */ +#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ /* (Write) Modem control register */ #define UART_MCR(n) UART_REG(n, 4) /* (Read) Line status register */ #define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR (1 << 0) /* Data ready */ -#define UART_LSR_OE (1 << 1) /* Overrun error */ -#define UART_LSR_PE (1 << 2) /* Parity error */ -#define UART_LSR_FE (1 << 3) /* Frame error */ -#define UART_LSR_BI (1 << 4) /* Break interrupt */ -#define UART_LSR_THRE (1 << 5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT (1 << 6) /* Xmit empty */ -#define UART_LSR_FIFOE (1 << 7) /* FIFO error */ +#define UART_LSR_DR BIT(0) /* Data ready */ +#define UART_LSR_OE BIT(1) /* Overrun error */ +#define UART_LSR_PE BIT(2) /* Parity error */ +#define UART_LSR_FE BIT(3) /* Frame error */ +#define UART_LSR_BI BIT(4) /* Break interrupt */ +#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ +#define UART_LSR_TEMT BIT(6) /* Xmit empty */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* DLAB == 1 */ diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c index ea016805c0..d996695dfc 100644 --- a/chip/npcx/cec.c +++ b/chip/npcx/cec.c @@ -34,7 +34,7 @@ #endif /* Notification from interrupt to CEC task that data has been received */ -#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM(1 << 0) +#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM(BIT(0)) /* CEC broadcast address. Also the highest possible CEC address */ #define CEC_BROADCAST_ADDR 15 diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index ecd48197b2..178f398434 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -160,7 +160,7 @@ void clock_turbo(void) * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. */ NPCX_HFCGP = 0x01; - NPCX_HFCBCD = (1 << 4); + NPCX_HFCBCD = BIT(4); } void clock_normal(void) diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c index e6280c97db..381be8a018 100644 --- a/chip/npcx/fan.c +++ b/chip/npcx/fan.c @@ -89,7 +89,7 @@ static int rpm_pre[FAN_CH_COUNT]; ((fan_status[ch].mft_freq * 60 / PULSES_ROUND) / MAX((tach), 1)) /* MFT TCNT default count */ -#define TACHO_MAX_CNT ((1 << 16) - 1) +#define TACHO_MAX_CNT (BIT(16) - 1) /* Margin of target rpm */ #define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100) diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index a86a5879ba..971512ec72 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -1041,7 +1041,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3db1c79190..7c812e5da2 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -480,14 +480,14 @@ enum { }; enum { - MASK_PIN0 = (1<<0), - MASK_PIN1 = (1<<1), - MASK_PIN2 = (1<<2), - MASK_PIN3 = (1<<3), - MASK_PIN4 = (1<<4), - MASK_PIN5 = (1<<5), - MASK_PIN6 = (1<<6), - MASK_PIN7 = (1<<7), + MASK_PIN0 = BIT(0), + MASK_PIN1 = BIT(1), + MASK_PIN2 = BIT(2), + MASK_PIN3 = BIT(3), + MASK_PIN4 = BIT(4), + MASK_PIN5 = BIT(5), + MASK_PIN6 = BIT(6), + MASK_PIN7 = BIT(7), }; /* Chip-independent aliases for port base group */ @@ -1863,21 +1863,21 @@ enum { /* * Status registers for the W25Q16CV SPI flash */ -#define SPI_FLASH_SR2_SUS (1 << 7) -#define SPI_FLASH_SR2_CMP (1 << 6) -#define SPI_FLASH_SR2_LB3 (1 << 5) -#define SPI_FLASH_SR2_LB2 (1 << 4) -#define SPI_FLASH_SR2_LB1 (1 << 3) -#define SPI_FLASH_SR2_QE (1 << 1) -#define SPI_FLASH_SR2_SRP1 (1 << 0) -#define SPI_FLASH_SR1_SRP0 (1 << 7) -#define SPI_FLASH_SR1_SEC (1 << 6) -#define SPI_FLASH_SR1_TB (1 << 5) -#define SPI_FLASH_SR1_BP2 (1 << 4) -#define SPI_FLASH_SR1_BP1 (1 << 3) -#define SPI_FLASH_SR1_BP0 (1 << 2) -#define SPI_FLASH_SR1_WEL (1 << 1) -#define SPI_FLASH_SR1_BUSY (1 << 0) +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 464ad9db5f..2e061ad2c2 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -1055,7 +1055,7 @@ static int shi_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = SHI_MAX_REQUEST_SIZE; r->max_response_packet_size = SHI_MAX_RESPONSE_SIZE; r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 726aa30350..b9d3367d91 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -25,7 +25,7 @@ /* Delay after writing TTC for value to latch */ #define MTC_TTC_LOAD_DELAY_US 250 -#define MTC_ALARM_MASK ((1 << 25) - 1) +#define MTC_ALARM_MASK (BIT(25) - 1) #define MTC_WUI_GROUP MIWU_GROUP_4 #define MTC_WUI_MASK MASK_PIN7 @@ -266,7 +266,7 @@ void system_set_rtc(uint32_t seconds) #define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16) #define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20) -#define BKUP_PANIC_DATA_VALID (1 << 0) +#define BKUP_PANIC_DATA_VALID BIT(0) void chip_panic_data_backup(void) { diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index da400f79bb..5700143e2a 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -9,8 +9,8 @@ #define __CROS_EC_SYSTEM_CHIP_H /* Flags for BBRM_DATA_INDEX_WAKE */ -#define HIBERNATE_WAKE_MTC (1 << 0) /* MTC alarm */ -#define HIBERNATE_WAKE_PIN (1 << 1) /* Wake pin */ +#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ +#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ /* Indices for battery-backed ram (BBRAM) data position */ enum bbram_data_index { diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c index 2d0574ff01..3bbeee90a0 100644 --- a/chip/npcx/wov.c +++ b/chip/npcx/wov.c @@ -1743,12 +1743,12 @@ void wov_set_i2s_bclk(uint32_t i2s_clock) * first bit (MSB) of channel 1 (right channel). * If channel 1 is not used set this field to -1. * - * @param flags - WOV_TDM_ADJACENT_TO_CH0 = (1 << 0). There is a + * @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a * channel adjacent to channel 0, so float SDAT when * driving the last bit (LSB) of the channel during the * second half of the clock cycle to avoid bus contention. * - * WOV_TDM_ADJACENT_TO_CH1 = (1 << 1). There is a channel + * WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel * adjacent to channel 1. * * @return EC error code. diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h index 96bc03c2b8..dce534c501 100644 --- a/chip/npcx/wov_chip.h +++ b/chip/npcx/wov_chip.h @@ -427,12 +427,12 @@ void wov_set_i2s_bclk(uint32_t i2s_clock); * first bit (MSB) of channel 1 (right channel). * If channel 1 is not used set this field to -1. * - * @param flags - WOV_TDM_ADJACENT_TO_CH0 = (1 << 0). There is a + * @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a * channel adjacent to channel 0, so float SDAT when * driving the last bit (LSB) of the channel during the * second half of the clock cycle to avoid bus contention. * - * WOV_TDM_ADJACENT_TO_CH1 = (1 << 1). There is a channel + * WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel * adjacent to channel 1. * * @return EC error code. diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c index bcad7466e9..5afb30425b 100644 --- a/chip/nrf51/radio_test.c +++ b/chip/nrf51/radio_test.c @@ -111,7 +111,7 @@ static int ble_test_init(int chan) if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL) return HCI_ERR_Invalid_HCI_Command_Parameters; - NRF51_RADIO_CRCCNF = 3 | (1 << 8); /* 3-byte, skip address */ + NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */ /* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */ /* 0x1_0000_0000_0000_0110_0101_1011 */ NRF51_RADIO_CRCPOLY = 0x100065B; diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h index e9d2003f33..c92c66dde9 100644 --- a/chip/nrf51/registers.h +++ b/chip/nrf51/registers.h @@ -361,7 +361,7 @@ #define NRF51_RADIO_TXADD_MAX 8 /* OVERRIDE4 */ -#define NRF51_RADIO_OVERRIDE_EN (1 << 31) +#define NRF51_RADIO_OVERRIDE_EN BIT(31) /* @@ -433,8 +433,8 @@ #define NRF51_TWI_ENABLE_VAL 0x5 #define NRF51_TWI_DISABLE_VAL 0x0 -#define NRF51_TWI_ERRORSRC_ANACK (1<<1) /* Address NACK */ -#define NRF51_TWI_ERRORSRC_DNACK (1<<2) /* Data NACK */ +#define NRF51_TWI_ERRORSRC_ANACK BIT(1) /* Address NACK */ +#define NRF51_TWI_ERRORSRC_DNACK BIT(2) /* Data NACK */ /* * TWI (I2C) Instance 0 @@ -526,14 +526,14 @@ #define NRF51_GPIOTE_PORT_BIT 31 /* For GPIOTE.CONFIG */ #define NRF51_GPIOTE_MODE_DISABLED (0<<0) -#define NRF51_GPIOTE_MODE_EVENT (1<<0) +#define NRF51_GPIOTE_MODE_EVENT BIT(0) #define NRF51_GPIOTE_MODE_TASK (3<<0) #define NRF51_GPIOTE_PSEL_POS (8) -#define NRF51_GPIOTE_POLARITY_LOTOHI (1<<16) +#define NRF51_GPIOTE_POLARITY_LOTOHI BIT(16) #define NRF51_GPIOTE_POLARITY_HITOLO (2<<16) #define NRF51_GPIOTE_POLARITY_TOGGLE (3<<16) #define NRF51_GPIOTE_OUTINIT_LOW (0<<20) -#define NRF51_GPIOTE_OUTINIT_HIGH (1<<20) +#define NRF51_GPIOTE_OUTINIT_HIGH BIT(20) /* * Timer / Counter @@ -590,9 +590,9 @@ #define NRF51_RNG_CONFIG REG32(NRF51_RNG_BASE + 0x504) #define NRF51_RNG_VALUE REG32(NRF51_RNG_BASE + 0x508) /* For RNG Shortcuts */ -#define NRF51_RNG_SHORTS_VALRDY_STOP (1 << 0) +#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0) /* For RNG Config */ -#define NRF51_RNG_DERCEN (1 << 0) +#define NRF51_RNG_DERCEN BIT(0) /* @@ -620,7 +620,7 @@ #define NRF51_WDT_CONFIG_SLEEP_PAUSE 0 #define NRF51_WDT_CONFIG_SLEEP_RUN 1 #define NRF51_WDT_CONFIG_HALT_PAUSE (0<<4) -#define NRF51_WDT_CONFIG_HALT_RUN (1<<4) +#define NRF51_WDT_CONFIG_HALT_RUN BIT(4) #define NRF51_WDT_RELOAD_VAL 0x6E524635 @@ -644,16 +644,16 @@ #define NRF51_PIN_CNF_DIR_INPUT (0) #define NRF51_PIN_CNF_DIR_OUTPUT (1) #define NRF51_PIN_CNF_INPUT_CONNECT (0<<1) -#define NRF51_PIN_CNF_INPUT_DISCONNECT (1<<1) +#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1) #define NRF51_PIN_CNF_PULL_DISABLED (0<<2) -#define NRF51_PIN_CNF_PULLDOWN (1<<2) +#define NRF51_PIN_CNF_PULLDOWN BIT(2) #define NRF51_PIN_CNF_PULLUP (3<<2) /* * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect * for example, S0D1 = Standard drive 0, disconnect on 1 */ #define NRF51_PIN_CNF_DRIVE_S0S1 (0<<8) -#define NRF51_PIN_CNF_DRIVE_H0S1 (1<<8) +#define NRF51_PIN_CNF_DRIVE_H0S1 BIT(8) #define NRF51_PIN_CNF_DRIVE_S0H1 (2<<8) #define NRF51_PIN_CNF_DRIVE_H0H1 (3<<8) #define NRF51_PIN_CNF_DRIVE_D0S1 (4<<8) diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index 0f31e3b286..3836767d1f 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -75,7 +75,7 @@ static void adc_init(void) * If clock is already enabled, and ADC module is enabled * then this is a warm reboot and ADC is already initialized. */ - if (STM32_RCC_APB2ENR & (1 << 9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN)) + if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN)) return; /* Enable ADC clock */ @@ -107,7 +107,7 @@ static void adc_init(void) static void adc_configure(int ain_id) { /* Select channel to convert */ - STM32_ADC_CHSELR = 1 << ain_id; + STM32_ADC_CHSELR = BIT(ain_id); /* Disable DMA */ STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN; @@ -126,16 +126,16 @@ static void adc_continuous_read(int ain_id) STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT; /* Start continuous conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ } static void adc_continuous_stop(void) { /* Stop on-going conversion */ - STM32_ADC_CR |= 1 << 4; /* ADSTP */ + STM32_ADC_CR |= BIT(4); /* ADSTP */ /* Wait for conversion to stop */ - while (STM32_ADC_CR & (1 << 4)) + while (STM32_ADC_CR & BIT(4)) ; /* CONT=0 -> continuous mode off */ @@ -173,7 +173,7 @@ static void adc_interval_read(int ain_id, int interval_ms) STM32_TIM_CR1(TIM_ADC) |= 1; /* Start ADC conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ } static void adc_interval_stop(void) @@ -182,10 +182,10 @@ static void adc_interval_stop(void) STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK; /* Set ADSTP to clear ADSTART */ - STM32_ADC_CR |= 1 << 4; /* ADSTP */ + STM32_ADC_CR |= BIT(4); /* ADSTP */ /* Wait for conversion to stop */ - while (STM32_ADC_CR & (1 << 4)) + while (STM32_ADC_CR & BIT(4)) ; /* Stop the timer */ @@ -307,10 +307,10 @@ int adc_read_channel(enum adc_channel ch) STM32_ADC_ISR = 0xe; /* Start conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ /* Wait for end of conversion */ - while (!(STM32_ADC_ISR & (1 << 2))) + while (!(STM32_ADC_ISR & BIT(2))) ; /* read converted value */ value = STM32_ADC_DR; diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 6e22c49ac3..7bee47c319 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -59,10 +59,10 @@ static void adc_configure(int ain_id) adc_set_channel(0, ain_id); /* Disable DMA */ - STM32_ADC_CR2 &= ~(1 << 8); + STM32_ADC_CR2 &= ~BIT(8); /* Disable scan mode */ - STM32_ADC_CR1 &= ~(1 << 8); + STM32_ADC_CR1 &= ~BIT(8); } static void __attribute__((unused)) adc_configure_all(void) @@ -75,25 +75,25 @@ static void __attribute__((unused)) adc_configure_all(void) adc_set_channel(i, adc_channels[i].channel); /* Enable DMA */ - STM32_ADC_CR2 |= (1 << 8); + STM32_ADC_CR2 |= BIT(8); /* Enable scan mode */ - STM32_ADC_CR1 |= (1 << 8); + STM32_ADC_CR1 |= BIT(8); } static inline int adc_powered(void) { - return STM32_ADC_CR2 & (1 << 0); + return STM32_ADC_CR2 & BIT(0); } static inline int adc_conversion_ended(void) { - return STM32_ADC_SR & (1 << 1); + return STM32_ADC_SR & BIT(1); } static int adc_watchdog_enabled(void) { - return STM32_ADC_CR1 & (1 << 23); + return STM32_ADC_CR1 & BIT(23); } static int adc_enable_watchdog_no_lock(void) @@ -111,16 +111,16 @@ static int adc_enable_watchdog_no_lock(void) STM32_ADC_SR &= ~0x1; /* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */ - STM32_ADC_CR1 |= (1 << 9) | (1 << 8) | (1 << 6) | (1 << 23); + STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23); /* Disable DMA */ - STM32_ADC_CR2 &= ~(1 << 8); + STM32_ADC_CR2 &= ~BIT(8); /* CONT=1 */ - STM32_ADC_CR2 |= (1 << 1); + STM32_ADC_CR2 |= BIT(1); /* Start conversion */ - STM32_ADC_CR2 |= (1 << 0); + STM32_ADC_CR2 |= BIT(0); return EC_SUCCESS; } @@ -152,10 +152,10 @@ static int adc_disable_watchdog_no_lock(void) return EC_ERROR_UNKNOWN; /* AWDEN=0, AWDIE=0 */ - STM32_ADC_CR1 &= ~(1 << 23) & ~(1 << 6); + STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6); /* CONT=0 */ - STM32_ADC_CR2 &= ~(1 << 1); + STM32_ADC_CR2 &= ~BIT(1); return EC_SUCCESS; } @@ -193,7 +193,7 @@ int adc_read_channel(enum adc_channel ch) adc_configure(adc->channel); /* Clear EOC bit */ - STM32_ADC_SR &= ~(1 << 1); + STM32_ADC_SR &= ~BIT(1); /* Start conversion (Note: For now only confirmed on F4) */ #if defined(CHIP_FAMILY_STM32F4) diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c index 270d953252..69cacb0d0e 100644 --- a/chip/stm32/adc-stm32l.c +++ b/chip/stm32/adc-stm32l.c @@ -42,10 +42,10 @@ static void adc_configure(int ain_id) adc_set_channel(0, ain_id); /* Disable DMA */ - STM32_ADC_CR2 &= ~(1 << 8); + STM32_ADC_CR2 &= ~BIT(8); /* Disable scan mode */ - STM32_ADC_CR1 &= ~(1 << 8); + STM32_ADC_CR1 &= ~BIT(8); } static void adc_configure_all(void) @@ -58,22 +58,22 @@ static void adc_configure_all(void) adc_set_channel(i, adc_channels[i].channel); /* Enable DMA */ - STM32_ADC_CR2 |= (1 << 8); + STM32_ADC_CR2 |= BIT(8); /* Enable scan mode */ - STM32_ADC_CR1 |= (1 << 8); + STM32_ADC_CR1 |= BIT(8); } static inline int adc_powered(void) { - return STM32_ADC_SR & (1 << 6); /* ADONS */ + return STM32_ADC_SR & BIT(6); /* ADONS */ } static void adc_enable_clock(void) { - STM32_RCC_APB2ENR |= (1 << 9); + STM32_RCC_APB2ENR |= BIT(9); /* ADCCLK = HSI / 2 = 8MHz*/ - STM32_ADC_CCR |= (1 << 16); + STM32_ADC_CCR |= BIT(16); } static void adc_init(void) @@ -92,10 +92,10 @@ static void adc_init(void) if (!adc_powered()) /* Power on ADC module */ - STM32_ADC_CR2 |= (1 << 0); /* ADON */ + STM32_ADC_CR2 |= BIT(0); /* ADON */ /* Set right alignment */ - STM32_ADC_CR2 &= ~(1 << 11); + STM32_ADC_CR2 &= ~BIT(11); /* * Set sample time of all channels to 16 cycles. @@ -132,7 +132,7 @@ static void adc_release(void) static inline int adc_conversion_ended(void) { - return STM32_ADC_SR & (1 << 1); + return STM32_ADC_SR & BIT(1); } int adc_read_channel(enum adc_channel ch) @@ -148,10 +148,10 @@ int adc_read_channel(enum adc_channel ch) adc_configure(adc->channel); /* Clear EOC bit */ - STM32_ADC_SR &= ~(1 << 1); + STM32_ADC_SR &= ~BIT(1); /* Start conversion */ - STM32_ADC_CR2 |= (1 << 30); /* SWSTART */ + STM32_ADC_CR2 |= BIT(30); /* SWSTART */ /* Wait for EOC bit set */ deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 26188d97fd..24da104c3d 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -113,11 +113,11 @@ void config_hispeed_clock(void) { #ifdef CHIP_FAMILY_STM32F3 /* Ensure that HSE is ON */ - if (!(STM32_RCC_CR & (1 << 17))) { + if (!(STM32_RCC_CR & BIT(17))) { /* Enable HSE */ - STM32_RCC_CR |= 1 << 16; + STM32_RCC_CR |= BIT(16); /* Wait for HSE to be ready */ - while (!(STM32_RCC_CR & (1 << 17))) + while (!(STM32_RCC_CR & BIT(17))) ; } @@ -186,11 +186,11 @@ defined(CHIP_VARIANT_STM32F070) ; #else /* Ensure that HSI48 is ON */ - if (!(STM32_RCC_CR2 & (1 << 17))) { + if (!(STM32_RCC_CR2 & BIT(17))) { /* Enable HSI */ - STM32_RCC_CR2 |= 1 << 16; + STM32_RCC_CR2 |= BIT(16); /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR2 & (1 << 17))) + while (!(STM32_RCC_CR2 & BIT(17))) ; } diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 95d9b1e96c..30faa0035a 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -249,8 +249,8 @@ static void low_power_init(void) task_enable_irq(STM32_IRQ_LPTIM1); /* Wake-up interrupts from EXTI for USART and LPTIM */ - STM32_EXTI_CPUIMR1 |= 1 << 26; /* [26] wkup26: USART1 wake-up */ - STM32_EXTI_CPUIMR2 |= 1 << 15; /* [15] wkup47: LPTIM1 wake-up */ + STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */ + STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */ /* optimize power vs latency in STOP mode */ STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index 93706c7019..b0903b5cb1 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -33,8 +33,8 @@ static int fake_hibernate; * because it's the lowest clock rate we can still run 115200 baud serial * for the debug console. */ -#define MSI_2MHZ_CLOCK (1 << 21) -#define MSI_1MHZ_CLOCK (1 << 20) +#define MSI_2MHZ_CLOCK BIT(21) +#define MSI_1MHZ_CLOCK BIT(20) enum clock_osc { OSC_INIT = 0, /* Uninitialized */ diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h index d6959310d6..038dc76f7c 100644 --- a/chip/stm32/crc_hw.h +++ b/chip/stm32/crc_hw.h @@ -13,7 +13,7 @@ static inline void crc32_init(void) { /* switch on CRC controller */ - STM32_RCC_AHBENR |= 1 << 6; /* switch on CRC controller */ + STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */ /* Delay 1 AHB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_AHB, 1); /* reset CRC state */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index fcd4b19e12..dd248e62f8 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -414,7 +414,7 @@ void hwtimer_setup_watchdog(void) * Timer configuration : Down counter, counter disabled, update * event only on overflow. */ - timer->cr1 = 0x0014 | (1 << 7); + timer->cr1 = 0x0014 | BIT(7); /* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */ timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4); @@ -426,7 +426,7 @@ void hwtimer_setup_watchdog(void) * to obtain the number of times TIM_CLOCK_LSB can overflow before we * generate an interrupt. */ - timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / (1 << 16); + timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16); /* count on every TIM_CLOCK_LSB overflow */ timer->psc = 0; diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index ce2f8636f6..45d489a8c0 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -69,9 +69,9 @@ static void pwm_configure(enum pwm_channel ch) /* Output, PWM mode 1, preload enable */ if (pwm->channel & 0x1) - *ccmr = (6 << 4) | (1 << 3); + *ccmr = (6 << 4) | BIT(3); else - *ccmr = (6 << 12) | (1 << 11); + *ccmr = (6 << 12) | BIT(11); /* Output enable. Set active high/low. */ if (pwm->flags & PWM_CONFIG_ACTIVE_LOW) @@ -90,13 +90,13 @@ static void pwm_configure(enum pwm_channel ch) * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't * harmful on STM32L. */ - tim->bdtr |= (1 << 15); + tim->bdtr |= BIT(15); /* Generate update event to force loading of shadow registers */ tim->egr |= 1; /* Enable auto-reload preload, start counting */ - tim->cr1 |= (1 << 7) | (1 << 0); + tim->cr1 |= BIT(7) | BIT(0); atomic_or(&using_pwm, 1 << ch); @@ -113,7 +113,7 @@ static void pwm_disable(enum pwm_channel ch) return; /* Main output disable */ - tim->bdtr &= ~(1 << 15); + tim->bdtr &= ~BIT(15); /* Disable counter */ tim->cr1 &= ~0x1; diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index de10176c77..eda4e0960f 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -715,9 +715,9 @@ static int spi_get_protocol_info(struct host_cmd_handler_args *args) memset(r, 0, sizeof(*r)); #ifdef CONFIG_SPI_PROTOCOL_V2 - r->protocol_versions |= (1 << 2); + r->protocol_versions |= BIT(2); #endif - r->protocol_versions |= (1 << 3); + r->protocol_versions |= BIT(3); r->max_request_packet_size = SPI_MAX_REQUEST_SIZE; r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE; r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; diff --git a/chip/stm32/system.c b/chip/stm32/system.c index c7ff4f23d9..5f6124657e 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -285,24 +285,24 @@ void system_pre_init(void) STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN; #elif defined(CHIP_FAMILY_STM32H7) /* enable backup registers */ - STM32_RCC_AHB4ENR |= 1 << 28; + STM32_RCC_AHB4ENR |= BIT(28); #else /* enable backup registers */ - STM32_RCC_APB1ENR |= 1 << 27; + STM32_RCC_APB1ENR |= BIT(27); #endif /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* Enable access to RCC CSR register and RTC backup registers */ - STM32_PWR_CR |= 1 << 8; + STM32_PWR_CR |= BIT(8); #ifdef CHIP_VARIANT_STM32L476 /* Enable Vddio2 */ - STM32_PWR_CR2 |= 1 << 9; + STM32_PWR_CR2 |= BIT(9); #endif /* switch on LSI */ - STM32_RCC_CSR |= 1 << 0; + STM32_RCC_CSR |= BIT(0); /* Wait for LSI to be ready */ - while (!(STM32_RCC_CSR & (1 << 1))) + while (!(STM32_RCC_CSR & BIT(1))) ; /* re-configure RTC if needed */ #ifdef CHIP_FAMILY_STM32L diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index 0ef357466c..4d3ea20b8c 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -47,12 +47,12 @@ void usart_init(struct usart_config const *config) #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ defined(CHIP_FAMILY_STM32L4) if (config->flags & USART_CONFIG_FLAG_RX_INV) - cr2 |= (1 << 16); + cr2 |= BIT(16); if (config->flags & USART_CONFIG_FLAG_TX_INV) - cr2 |= (1 << 17); + cr2 |= BIT(17); #endif if (config->flags & USART_CONFIG_FLAG_HDSEL) - cr3 |= (1 << 3); + cr3 |= BIT(3); STM32_USART_CR1(base) = 0x0000; STM32_USART_CR2(base) = cr2; diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h index 53b13762e9..771c0ccfde 100644 --- a/chip/stm32/usart.h +++ b/chip/stm32/usart.h @@ -134,9 +134,9 @@ struct usart_config { int baud; /* Other flags (rx/tx inversion, half-duplex). */ -#define USART_CONFIG_FLAG_RX_INV (1 << 0) -#define USART_CONFIG_FLAG_TX_INV (1 << 1) -#define USART_CONFIG_FLAG_HDSEL (1 << 2) +#define USART_CONFIG_FLAG_RX_INV BIT(0) +#define USART_CONFIG_FLAG_TX_INV BIT(1) +#define USART_CONFIG_FLAG_HDSEL BIT(2) unsigned int flags; struct consumer consumer; diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c index 97bb93cafd..de755f2fdd 100644 --- a/chip/stm32/usb-stm32f0.c +++ b/chip/stm32/usb-stm32f0.c @@ -14,13 +14,13 @@ void usb_connect(void) /* USB is in use */ disable_sleep(SLEEP_MASK_USB_DEVICE); - STM32_USB_BCDR |= (1 << 15) /* DPPU */; + STM32_USB_BCDR |= BIT(15) /* DPPU */; } void usb_disconnect(void) { /* disable pull-up on DP to disconnect */ - STM32_USB_BCDR &= ~(1 << 15) /* DPPU */; + STM32_USB_BCDR &= ~BIT(15) /* DPPU */; /* USB is off, so sleep whenever */ enable_sleep(SLEEP_MASK_USB_DEVICE); diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index c8768823d7..82b418707a 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -351,7 +351,7 @@ static void ep0_event(enum usb_ep_event evt) if (evt != USB_EVENT_RESET) return; - STM32_USB_EP(0) = (1 << 9) /* control EP */ | + STM32_USB_EP(0) = BIT(9) /* control EP */ | (2 << 4) /* TX NAK */ | (3 << 12) /* RX VALID */; @@ -673,8 +673,8 @@ void usb_init(void) STM32_USB_BTABLE = 0; /* EXTI18 is USB wake up interrupt */ - /* STM32_EXTI_RTSR |= 1 << 18; */ - /* STM32_EXTI_IMR |= 1 << 18; */ + /* STM32_EXTI_RTSR |= BIT(18); */ + /* STM32_EXTI_IMR |= BIT(18); */ /* Enable interrupt handlers */ task_enable_irq(STM32_IRQ_USB_LP); diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h index 9d656df22d..f8b90c1d1f 100644 --- a/chip/stm32/usb_dwc_registers.h +++ b/chip/stm32/usb_dwc_registers.h @@ -131,8 +131,8 @@ extern struct dwc_usb usb_ctl; #define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) /*#define GR_USB_GGPIO GR_USB_REG(GC_USB_GGPIO_OFFSET)*/ #define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) -#define GCCFG_VBDEN (1 << 21) -#define GCCFG_PWRDWN (1 << 16) +#define GCCFG_VBDEN BIT(21) +#define GCCFG_PWRDWN BIT(16) #define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) #define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) @@ -156,9 +156,9 @@ extern struct dwc_usb usb_ctl; #define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) #define DTHRCTL_TXTHRLEN_6 (0x40 << 2) #define DTHRCTL_RXTHRLEN_6 (0x40 << 17) -#define DTHRCTL_RXTHREN (1 << 16) -#define DTHRCTL_ISOTHREN (1 << 1) -#define DTHRCTL_NONISOTHREN (1 << 0) +#define DTHRCTL_RXTHREN BIT(16) +#define DTHRCTL_ISOTHREN BIT(1) +#define DTHRCTL_NONISOTHREN BIT(0) #define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) #define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n) * 0x20 + (off)) @@ -176,7 +176,7 @@ extern struct dwc_usb usb_ctl; #define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) #define GOTGCTL_BVALOEN (1 << GC_USB_GOTGCTL_BVALIDOVEN_LSB) -#define GOTGCTL_BVALOVAL (1 << 7) +#define GOTGCTL_BVALOVAL BIT(7) /* Bit 5 */ #define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) @@ -187,7 +187,7 @@ extern struct dwc_usb usb_ctl; /* Bit 7 */ #define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) #define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL -#define GAHBCFG_PTXFELVL (1 << 8) +#define GAHBCFG_PTXFELVL BIT(8) #define GUSBCFG_TOUTCAL(n) (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \ & GC_USB_GUSBCFG_TOUTCAL_MASK) @@ -195,19 +195,19 @@ extern struct dwc_usb usb_ctl; & GC_USB_GUSBCFG_USBTRDTIM_MASK) /* Force device mode */ #define GUSBCFG_FDMOD (1 << GC_USB_GUSBCFG_FDMOD_LSB) -#define GUSBCFG_PHYSEL (1 << 6) -#define GUSBCFG_SRPCAP (1 << 8) -#define GUSBCFG_HNPCAP (1 << 9) -#define GUSBCFG_ULPIFSLS (1 << 17) -#define GUSBCFG_ULPIAR (1 << 18) -#define GUSBCFG_ULPICSM (1 << 19) -#define GUSBCFG_ULPIEVBUSD (1 << 20) -#define GUSBCFG_ULPIEVBUSI (1 << 21) -#define GUSBCFG_TSDPS (1 << 22) -#define GUSBCFG_PCCI (1 << 23) -#define GUSBCFG_PTCI (1 << 24) -#define GUSBCFG_ULPIIPD (1 << 25) -#define GUSBCFG_TSDPS (1 << 22) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_ULPIFSLS BIT(17) +#define GUSBCFG_ULPIAR BIT(18) +#define GUSBCFG_ULPICSM BIT(19) +#define GUSBCFG_ULPIEVBUSD BIT(20) +#define GUSBCFG_ULPIEVBUSI BIT(21) +#define GUSBCFG_TSDPS BIT(22) +#define GUSBCFG_PCCI BIT(23) +#define GUSBCFG_PTCI BIT(24) +#define GUSBCFG_ULPIIPD BIT(25) +#define GUSBCFG_TSDPS BIT(22) #define GRSTCTL_CSFTRST (1 << GC_USB_GRSTCTL_CSFTRST_LSB) @@ -313,12 +313,12 @@ extern struct dwc_usb usb_ctl; #define DOEPDMA_BS_HOST_BSY (3 << 30) #define DOEPDMA_BS_MASK (3 << 30) #define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST (1 << 27) -#define DOEPDMA_SP (1 << 26) -#define DOEPDMA_IOC (1 << 25) -#define DOEPDMA_SR (1 << 24) -#define DOEPDMA_MTRF (1 << 23) -#define DOEPDMA_NAK (1 << 16) +#define DOEPDMA_LAST BIT(27) +#define DOEPDMA_SP BIT(26) +#define DOEPDMA_IOC BIT(25) +#define DOEPDMA_SR BIT(24) +#define DOEPDMA_MTRF BIT(23) +#define DOEPDMA_NAK BIT(16) #define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) #define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) @@ -328,9 +328,9 @@ extern struct dwc_usb usb_ctl; #define DIEPDMA_BS_HOST_BSY (3 << 30) #define DIEPDMA_BS_MASK (3 << 30) #define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST (1 << 27) -#define DIEPDMA_SP (1 << 26) -#define DIEPDMA_IOC (1 << 25) +#define DIEPDMA_LAST BIT(27) +#define DIEPDMA_SP BIT(26) +#define DIEPDMA_IOC BIT(25) #define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) #define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) @@ -942,31 +942,31 @@ extern struct dwc_usb usb_ctl; #define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc #define GC_USB_GUSBCFG_PCCI_LSB 23 -#define GC_USB_GUSBCFG_PCCI_MASK (1 << 23) +#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) #define GC_USB_GUSBCFG_PCCI_SIZE 0x1 #define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 #define GC_USB_GUSBCFG_PCCI_OFFSET 0xc #define GC_USB_GUSBCFG_PTCI_LSB 24 -#define GC_USB_GUSBCFG_PTCI_MASK (1 << 24) +#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) #define GC_USB_GUSBCFG_PTCI_SIZE 0x1 #define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 #define GC_USB_GUSBCFG_PTCI_OFFSET 0xc #define GC_USB_GUSBCFG_ULPIIPD_LSB 25 -#define GC_USB_GUSBCFG_ULPIIPD_MASK (1 << 25) +#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) #define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 #define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 #define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc #define GC_USB_GUSBCFG_FHMOD_LSB 29 -#define GC_USB_GUSBCFG_FHMOD_MASK (1 << 29) +#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) #define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 #define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 #define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc #define GC_USB_GUSBCFG_FDMOD_LSB 30 -#define GC_USB_GUSBCFG_FDMOD_MASK (1 << 30) +#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) #define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 #define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 #define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index 8c6ecca110..92656a1582 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -176,7 +176,7 @@ int pd_find_preamble(int port) } } cnt = vals[bit] - vals[bit-1]; - all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? 1 << 31 : 0); + all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0); if (all == 0x36db6db6) return bit - 1; /* should be SYNC-1 */ if (all == 0xF33F3F3F) @@ -557,7 +557,7 @@ void pd_hw_init_rx(int port) /* --- DAC configuration for comparator at 850mV --- */ #ifdef CONFIG_PD_USE_DAC_AS_REF /* Enable DAC interface clock. */ - STM32_RCC_APB1ENR |= (1 << 29); + STM32_RCC_APB1ENR |= BIT(29); /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* set voltage Vout=0.850V (Vref = 3.0V) */ @@ -570,7 +570,7 @@ void pd_hw_init_rx(int port) #ifdef CONFIG_USB_PD_INTERNAL_COMP #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) /* turn on COMP/SYSCFG */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */ @@ -583,12 +583,12 @@ void pd_hw_init_rx(int port) CMP2OUTSEL | STM32_COMP_CMP2HYST_HI; #elif defined(CHIP_FAMILY_STM32L) - STM32_RCC_APB1ENR |= 1 << 31; /* turn on COMP */ + STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */ STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1 | STM32_COMP_SPEED_FAST; /* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */ - STM32_RI_ASCR2 |= 1 << 4; + STM32_RI_ASCR2 |= BIT(4); #else #error Unsupported chip family #endif @@ -641,7 +641,7 @@ void pd_hw_init(int port, int role) /* 50% duty cycle on the output */ phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2; /* Timer channel output configuration */ - val = (6 << 4) | (1 << 3); + val = (6 << 4) | BIT(3); if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */ val <<= 8; if (TIM_TX_CCR_IDX(port) <= 2) diff --git a/common/button.c b/common/button.c index 4ca1dac852..3caa4383b5 100644 --- a/common/button.c +++ b/common/button.c @@ -437,9 +437,9 @@ enum debug_state { STATE_WARM_RESET_EXEC, }; -#define DEBUG_BTN_POWER (1 << 0) -#define DEBUG_BTN_VOL_UP (1 << 1) -#define DEBUG_BTN_VOL_DN (1 << 2) +#define DEBUG_BTN_POWER BIT(0) +#define DEBUG_BTN_VOL_UP BIT(1) +#define DEBUG_BTN_VOL_DN BIT(2) #define DEBUG_TIMEOUT (10 * SECOND) static enum debug_state curr_debug_state = STATE_DEBUG_NONE; diff --git a/common/curve25519-generic.c b/common/curve25519-generic.c index 4bc1114546..5374110a85 100644 --- a/common/curve25519-generic.c +++ b/common/curve25519-generic.c @@ -75,17 +75,17 @@ static void fe_frombytes(fe h, const uint8_t *s) { int64_t carry8; int64_t carry9; - carry9 = h9 + (1 << 24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; - carry1 = h1 + (1 << 24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; - carry3 = h3 + (1 << 24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; - carry5 = h5 + (1 << 24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; - carry7 = h7 + (1 << 24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; - - carry0 = h0 + (1 << 25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; - carry2 = h2 + (1 << 25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; - carry4 = h4 + (1 << 25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; - carry6 = h6 + (1 << 25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; - carry8 = h8 + (1 << 25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; + carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; + carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; + carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; + carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; + carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; + + carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; + carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; + carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; + carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; + carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; h[0] = h0; h[1] = h1; @@ -435,46 +435,46 @@ static void fe_mul(fe h, const fe f, const fe g) { * |h1| <= (1.65*1.65*2^51*(1+1+19+19+19+19+19+19+19+19)) * i.e. |h1| <= 1.7*2^59; narrower ranges for h3, h5, h7, h9 */ - carry0 = h0 + (1 << 25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; - carry4 = h4 + (1 << 25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; + carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; + carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; /* |h0| <= 2^25 */ /* |h4| <= 2^25 */ /* |h1| <= 1.71*2^59 */ /* |h5| <= 1.71*2^59 */ - carry1 = h1 + (1 << 24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; - carry5 = h5 + (1 << 24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; + carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; + carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; /* |h1| <= 2^24; from now on fits into int32 */ /* |h5| <= 2^24; from now on fits into int32 */ /* |h2| <= 1.41*2^60 */ /* |h6| <= 1.41*2^60 */ - carry2 = h2 + (1 << 25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; - carry6 = h6 + (1 << 25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; + carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; + carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; /* |h2| <= 2^25; from now on fits into int32 unchanged */ /* |h6| <= 2^25; from now on fits into int32 unchanged */ /* |h3| <= 1.71*2^59 */ /* |h7| <= 1.71*2^59 */ - carry3 = h3 + (1 << 24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; - carry7 = h7 + (1 << 24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; + carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; + carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; /* |h3| <= 2^24; from now on fits into int32 unchanged */ /* |h7| <= 2^24; from now on fits into int32 unchanged */ /* |h4| <= 1.72*2^34 */ /* |h8| <= 1.41*2^60 */ - carry4 = h4 + (1 << 25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; - carry8 = h8 + (1 << 25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; + carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; + carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; /* |h4| <= 2^25; from now on fits into int32 unchanged */ /* |h8| <= 2^25; from now on fits into int32 unchanged */ /* |h5| <= 1.01*2^24 */ /* |h9| <= 1.71*2^59 */ - carry9 = h9 + (1 << 24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; + carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; /* |h9| <= 2^24; from now on fits into int32 unchanged */ /* |h0| <= 1.1*2^39 */ - carry0 = h0 + (1 << 25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; + carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; /* |h0| <= 2^25; from now on fits into int32 unchanged */ /* |h1| <= 1.01*2^24 */ @@ -600,24 +600,24 @@ static void fe_sq(fe h, const fe f) { int64_t carry8; int64_t carry9; - carry0 = h0 + (1 << 25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; - carry4 = h4 + (1 << 25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; + carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; + carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; - carry1 = h1 + (1 << 24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; - carry5 = h5 + (1 << 24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; + carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; + carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; - carry2 = h2 + (1 << 25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; - carry6 = h6 + (1 << 25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; + carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; + carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; - carry3 = h3 + (1 << 24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; - carry7 = h7 + (1 << 24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; + carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; + carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; - carry4 = h4 + (1 << 25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; - carry8 = h8 + (1 << 25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; + carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; + carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; - carry9 = h9 + (1 << 24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; + carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; - carry0 = h0 + (1 << 25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; + carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; h[0] = h0; h[1] = h1; @@ -744,17 +744,17 @@ static void fe_mul121666(fe h, fe f) { int64_t carry8; int64_t carry9; - carry9 = h9 + (1 << 24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; - carry1 = h1 + (1 << 24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; - carry3 = h3 + (1 << 24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; - carry5 = h5 + (1 << 24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; - carry7 = h7 + (1 << 24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; - - carry0 = h0 + (1 << 25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; - carry2 = h2 + (1 << 25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; - carry4 = h4 + (1 << 25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; - carry6 = h6 + (1 << 25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; - carry8 = h8 + (1 << 25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; + carry9 = h9 + BIT(24); h0 += (carry9 >> 25) * 19; h9 -= carry9 & kTop39Bits; + carry1 = h1 + BIT(24); h2 += carry1 >> 25; h1 -= carry1 & kTop39Bits; + carry3 = h3 + BIT(24); h4 += carry3 >> 25; h3 -= carry3 & kTop39Bits; + carry5 = h5 + BIT(24); h6 += carry5 >> 25; h5 -= carry5 & kTop39Bits; + carry7 = h7 + BIT(24); h8 += carry7 >> 25; h7 -= carry7 & kTop39Bits; + + carry0 = h0 + BIT(25); h1 += carry0 >> 26; h0 -= carry0 & kTop38Bits; + carry2 = h2 + BIT(25); h3 += carry2 >> 26; h2 -= carry2 & kTop38Bits; + carry4 = h4 + BIT(25); h5 += carry4 >> 26; h4 -= carry4 & kTop38Bits; + carry6 = h6 + BIT(25); h7 += carry6 >> 26; h6 -= carry6 & kTop38Bits; + carry8 = h8 + BIT(25); h9 += carry8 >> 26; h8 -= carry8 & kTop38Bits; h[0] = h0; h[1] = h1; diff --git a/common/fan.c b/common/fan.c index f9d32d6820..2a5ef34e89 100644 --- a/common/fan.c +++ b/common/fan.c @@ -464,8 +464,8 @@ struct pwm_fan_state { }; /* For struct pwm_fan_state.flag */ -#define FAN_STATE_FLAG_ENABLED (1 << 0) -#define FAN_STATE_FLAG_THERMAL (1 << 1) +#define FAN_STATE_FLAG_ENABLED BIT(0) +#define FAN_STATE_FLAG_THERMAL BIT(1) static void pwm_fan_init(void) { diff --git a/common/flash.c b/common/flash.c index f98bf95a1e..2eb5f265aa 100644 --- a/common/flash.c +++ b/common/flash.c @@ -45,8 +45,8 @@ /* Flags for persist_state.flags */ /* Protect persist state and RO firmware at boot */ #define PERSIST_FLAG_PROTECT_RO 0x02 -#define PSTATE_VALID_FLAGS (1 << 0) -#define PSTATE_VALID_SERIALNO (1 << 1) +#define PSTATE_VALID_FLAGS BIT(0) +#define PSTATE_VALID_SERIALNO BIT(1) struct persist_state { uint8_t version; /* Version of this struct */ diff --git a/common/fmap.c b/common/fmap.c index 8b2087d7fe..8b5ecf94f3 100644 --- a/common/fmap.c +++ b/common/fmap.c @@ -51,9 +51,9 @@ struct fmap_header { uint16_t fmap_nareas; } __packed; -#define FMAP_AREA_STATIC (1 << 0) /* can be checksummed */ -#define FMAP_AREA_COMPRESSED (1 << 1) /* may be compressed */ -#define FMAP_AREA_RO (1 << 2) /* writes may fail */ +#define FMAP_AREA_STATIC BIT(0) /* can be checksummed */ +#define FMAP_AREA_COMPRESSED BIT(1) /* may be compressed */ +#define FMAP_AREA_RO BIT(2) /* writes may fail */ struct fmap_area_header { uint32_t area_offset; diff --git a/common/i2c_slave.c b/common/i2c_slave.c index 3dbb7d1036..e0b975246a 100644 --- a/common/i2c_slave.c +++ b/common/i2c_slave.c @@ -14,7 +14,7 @@ int i2c_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = I2C_MAX_HOST_PACKET_SIZE; r->max_response_packet_size = I2C_MAX_HOST_PACKET_SIZE; r->flags = 0; diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c index f45b84d465..660bd3970e 100644 --- a/common/keyboard_8042.c +++ b/common/keyboard_8042.c @@ -126,7 +126,7 @@ static enum scancode_set_list scancode_set = SCANCODE_SET_2; * the inter-char delay = (2 ** B) * (D + 8) / 240 (sec) * Default: 500ms delay, 10.9 chars/sec. */ -#define DEFAULT_TYPEMATIC_VALUE ((1 << 5) | (1 << 3) | (3 << 0)) +#define DEFAULT_TYPEMATIC_VALUE (BIT(5) | BIT(3) | (3 << 0)) static uint8_t typematic_value_from_host; static int typematic_first_delay; static int typematic_inter_delay; @@ -531,7 +531,7 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output) case STATE_WRITE_OUTPUT_PORT: CPRINTS5("KB eaten by STATE_WRITE_OUTPUT_PORT: 0x%02x", data); - A20_status = (data & (1 << 1)) ? 1 : 0; + A20_status = (data & BIT(1)) ? 1 : 0; data_port_state = STATE_NORMAL; break; @@ -696,9 +696,9 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output) case I8042_READ_OUTPUT_PORT: output[out_len++] = - (lpc_keyboard_input_pending() ? (1 << 5) : 0) | - (lpc_keyboard_has_char() ? (1 << 4) : 0) | - (A20_status ? (1 << 1) : 0) | + (lpc_keyboard_input_pending() ? BIT(5) : 0) | + (lpc_keyboard_has_char() ? BIT(4) : 0) | + (A20_status ? BIT(1) : 0) | 1; /* Main processor in normal mode */ break; @@ -756,7 +756,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output) * b0=0 to reset CPU, see I8042_SYSTEM_RESET above * b1=0 to disable A20 line */ - A20_status = command & (1 << 1) ? 1 : 0; + A20_status = command & BIT(1) ? 1 : 0; } else { CPRINTS("KB unsupported cmd: 0x%02x", command); reset_rate_and_delay(); diff --git a/common/printf.c b/common/printf.c index 37a0f42058..72272e6e6f 100644 --- a/common/printf.c +++ b/common/printf.c @@ -45,10 +45,10 @@ static int hexdigit(int c) } /* Flags for vfnprintf() flags */ -#define PF_LEFT (1 << 0) /* Left-justify */ -#define PF_PADZERO (1 << 1) /* Pad with 0's not spaces */ -#define PF_SIGN (1 << 2) /* Add sign (+) for a positive number */ -#define PF_64BIT (1 << 3) /* Number is 64-bit */ +#define PF_LEFT BIT(0) /* Left-justify */ +#define PF_PADZERO BIT(1) /* Pad with 0's not spaces */ +#define PF_SIGN BIT(2) /* Add sign (+) for a positive number */ +#define PF_64BIT BIT(3) /* Number is 64-bit */ int vfnprintf(int (*addchar)(void *context, int c), void *context, const char *format, va_list args) diff --git a/common/shmalloc.c b/common/shmalloc.c index 071930b649..c1cebaaf7c 100644 --- a/common/shmalloc.c +++ b/common/shmalloc.c @@ -62,10 +62,10 @@ static void do_release(struct shm_buffer *ptr) /* Take the buffer out of the allocated buffers chain. */ if (ptr == allocced_buf_chain) { if (ptr->next_buffer) { - set_map_bit(1 << 20); + set_map_bit(BIT(20)); ptr->next_buffer->prev_buffer = NULL; } else { - set_map_bit(1 << 21); + set_map_bit(BIT(21)); } allocced_buf_chain = ptr->next_buffer; } else { @@ -83,10 +83,10 @@ static void do_release(struct shm_buffer *ptr) ptr->prev_buffer->next_buffer = ptr->next_buffer; if (ptr->next_buffer) { - set_map_bit(1 << 22); + set_map_bit(BIT(22)); ptr->next_buffer->prev_buffer = ptr->prev_buffer; } else { - set_map_bit(1 << 23); + set_map_bit(BIT(23)); } } @@ -100,7 +100,7 @@ static void do_release(struct shm_buffer *ptr) * All memory had been allocated - this buffer is going to be * the only available free space. */ - set_map_bit(1 << 0); + set_map_bit(BIT(0)); free_buf_chain = ptr; free_buf_chain->buffer_size = released_size; free_buf_chain->next_buffer = NULL; @@ -115,23 +115,23 @@ static void do_release(struct shm_buffer *ptr) */ pfb = (struct shm_buffer *)((uintptr_t)ptr + released_size); if (pfb == free_buf_chain) { - set_map_bit(1 << 1); + set_map_bit(BIT(1)); /* Merge the two buffers. */ ptr->buffer_size = free_buf_chain->buffer_size + released_size; ptr->next_buffer = free_buf_chain->next_buffer; } else { - set_map_bit(1 << 2); + set_map_bit(BIT(2)); ptr->buffer_size = released_size; ptr->next_buffer = free_buf_chain; free_buf_chain->prev_buffer = ptr; } if (ptr->next_buffer) { - set_map_bit(1 << 3); + set_map_bit(BIT(3)); ptr->next_buffer->prev_buffer = ptr; } else { - set_map_bit(1 << 4); + set_map_bit(BIT(4)); } ptr->prev_buffer = NULL; free_buf_chain = ptr; @@ -166,10 +166,10 @@ static void do_release(struct shm_buffer *ptr) pfb->next_buffer = pfb->next_buffer->next_buffer; if (pfb->next_buffer) { - set_map_bit(1 << 5); + set_map_bit(BIT(5)); pfb->next_buffer->prev_buffer = pfb; } else { - set_map_bit(1 << 6); + set_map_bit(BIT(6)); } } return; @@ -178,23 +178,23 @@ static void do_release(struct shm_buffer *ptr) top = (struct shm_buffer *)((uintptr_t)ptr + released_size); if (top == pfb->next_buffer) { /* The new buffer is adjacent with the one right above it. */ - set_map_bit(1 << 7); + set_map_bit(BIT(7)); ptr->buffer_size = released_size + pfb->next_buffer->buffer_size; ptr->next_buffer = pfb->next_buffer->next_buffer; } else { /* Just include the new free buffer into the chain. */ - set_map_bit(1 << 8); + set_map_bit(BIT(8)); ptr->next_buffer = pfb->next_buffer; ptr->buffer_size = released_size; } ptr->prev_buffer = pfb; pfb->next_buffer = ptr; if (ptr->next_buffer) { - set_map_bit(1 << 9); + set_map_bit(BIT(9)); ptr->next_buffer->prev_buffer = ptr; } else { - set_map_bit(1 << 10); + set_map_bit(BIT(10)); } } @@ -223,7 +223,7 @@ static int do_acquire(int size, struct shm_buffer **dest_ptr) } if (!candidate) { - set_map_bit(1 << 11); + set_map_bit(BIT(11)); return EC_ERROR_BUSY; } @@ -242,20 +242,20 @@ static int do_acquire(int size, struct shm_buffer **dest_ptr) */ free_buf_chain = candidate->next_buffer; if (free_buf_chain) { - set_map_bit(1 << 12); + set_map_bit(BIT(12)); free_buf_chain->prev_buffer = 0; } else { - set_map_bit(1 << 13); + set_map_bit(BIT(13)); } } else { candidate->prev_buffer->next_buffer = candidate->next_buffer; if (candidate->next_buffer) { - set_map_bit(1 << 14); + set_map_bit(BIT(14)); candidate->next_buffer->prev_buffer = candidate->prev_buffer; } else { - set_map_bit(1 << 15); + set_map_bit(BIT(15)); } } return EC_SUCCESS; @@ -270,17 +270,17 @@ static int do_acquire(int size, struct shm_buffer **dest_ptr) pfb->prev_buffer = candidate->prev_buffer; if (pfb->next_buffer) { - set_map_bit(1 << 16); + set_map_bit(BIT(16)); pfb->next_buffer->prev_buffer = pfb; } else { - set_map_bit(1 << 17); + set_map_bit(BIT(17)); } if (candidate == free_buf_chain) { - set_map_bit(1 << 18); + set_map_bit(BIT(18)); free_buf_chain = pfb; } else { - set_map_bit(1 << 19); + set_map_bit(BIT(19)); pfb->prev_buffer->next_buffer = pfb; } return EC_SUCCESS; diff --git a/common/tpm_registers.c b/common/tpm_registers.c index 823f9c7513..fe6ffffc75 100644 --- a/common/tpm_registers.c +++ b/common/tpm_registers.c @@ -118,27 +118,27 @@ static struct { /* Bit definitions for some TPM registers. */ enum tpm_access_bits { - tpm_reg_valid_sts = (1 << 7), - active_locality = (1 << 5), - request_use = (1 << 1), - tpm_establishment = (1 << 0), + tpm_reg_valid_sts = BIT(7), + active_locality = BIT(5), + request_use = BIT(1), + tpm_establishment = BIT(0), }; enum tpm_sts_bits { tpm_family_shift = 26, - tpm_family_mask = ((1 << 2) - 1), /* 2 bits wide */ + tpm_family_mask = (BIT(2) - 1), /* 2 bits wide */ tpm_family_tpm2 = 1, - reset_establishment_bit = (1 << 25), - command_cancel = (1 << 24), + reset_establishment_bit = BIT(25), + command_cancel = BIT(24), burst_count_shift = 8, - burst_count_mask = ((1 << 16) - 1), /* 16 bits wide */ - sts_valid = (1 << 7), - command_ready = (1 << 6), - tpm_go = (1 << 5), - data_avail = (1 << 4), - expect = (1 << 3), - self_test_done = (1 << 2), - response_retry = (1 << 1), + burst_count_mask = (BIT(16) - 1), /* 16 bits wide */ + sts_valid = BIT(7), + command_ready = BIT(6), + tpm_go = BIT(5), + data_avail = BIT(4), + expect = BIT(3), + self_test_done = BIT(2), + response_retry = BIT(1), }; /* Used to count bytes read in version string */ @@ -676,9 +676,9 @@ static void call_extension_command(struct tpm_cmd_header *tpmh, * Events used on the TPM task context. Make sure there is no collision with * event(s) defined in chip/g/dcrypto/dcrypto_runtime.c */ -#define TPM_EVENT_RESET TASK_EVENT_CUSTOM(1 << 1) -#define TPM_EVENT_COMMIT TASK_EVENT_CUSTOM(1 << 2) -#define TPM_EVENT_ALT_EXTENSION TASK_EVENT_CUSTOM(1 << 3) +#define TPM_EVENT_RESET TASK_EVENT_CUSTOM(BIT(1)) +#define TPM_EVENT_COMMIT TASK_EVENT_CUSTOM(BIT(2)) +#define TPM_EVENT_ALT_EXTENSION TASK_EVENT_CUSTOM(BIT(3)) /* * Result of executing of the TPM command on the alternative path, could have diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c index 34e91ae2f7..ebac69b209 100644 --- a/common/usb_pd_protocol.c +++ b/common/usb_pd_protocol.c @@ -2577,7 +2577,7 @@ static int pd_restart_tcpc(int port) #define HAS_DEFFERED_INTERRUPT_HANDLER /* Events for pd_interrupt_handler_task */ -#define PD_PROCESS_INTERRUPT (1<<0) +#define PD_PROCESS_INTERRUPT BIT(0) static uint8_t pd_int_task_id[CONFIG_USB_PD_PORT_COUNT]; diff --git a/common/util.c b/common/util.c index e93eeebb16..1261def58f 100644 --- a/common/util.c +++ b/common/util.c @@ -515,9 +515,9 @@ int get_next_bit(uint32_t *mask) /* stateful conditional stuff */ enum cond_internal_bits { - COND_CURR_MASK = (1 << 0), /* current value */ - COND_RISE_MASK = (1 << 1), /* set if 0->1 */ - COND_FALL_MASK = (1 << 2), /* set if 1->0 */ + COND_CURR_MASK = BIT(0), /* current value */ + COND_RISE_MASK = BIT(1), /* set if 0->1 */ + COND_FALL_MASK = BIT(2), /* set if 1->0 */ }; void cond_init(cond_t *c, int val) diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index 87e0631787..21de5bebf4 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -9,15 +9,16 @@ #define __CROS_EC_CPU_H #include <stdint.h> +#include "compile_time_macros.h" /* Macro to access 32-bit registers */ #define CPUREG(addr) (*(volatile uint32_t*)(addr)) #define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) -#define ST_ENABLE (1 << 0) -#define ST_TICKINT (1 << 1) -#define ST_CLKSOURCE (1 << 2) -#define ST_COUNTFLAG (1 << 16) +#define ST_ENABLE BIT(0) +#define ST_TICKINT BIT(1) +#define ST_CLKSOURCE BIT(2) +#define ST_COUNTFLAG BIT(16) /* Nested Vectored Interrupt Controller */ #define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) @@ -38,21 +39,21 @@ #define CPU_NVIC_BFAR CPUREG(0xe000ed38) enum { - CPU_NVIC_MMFS_BFARVALID = 1 << 15, - CPU_NVIC_MMFS_MFARVALID = 1 << 7, + CPU_NVIC_MMFS_BFARVALID = BIT(15), + CPU_NVIC_MMFS_MFARVALID = BIT(7), - CPU_NVIC_CCR_ICACHE = 1 << 17, - CPU_NVIC_CCR_DCACHE = 1 << 16, - CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4, - CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3, + CPU_NVIC_CCR_ICACHE = BIT(17), + CPU_NVIC_CCR_DCACHE = BIT(16), + CPU_NVIC_CCR_DIV_0_TRAP = BIT(4), + CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3), CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, - CPU_NVIC_HFSR_FORCED = 1 << 30, - CPU_NVIC_HFSR_VECTTBL = 1 << 1, + CPU_NVIC_HFSR_FORCED = BIT(30), + CPU_NVIC_HFSR_VECTTBL = BIT(1), - CPU_NVIC_SHCSR_MEMFAULTENA = 1 << 16, - CPU_NVIC_SHCSR_BUSFAULTENA = 1 << 17, - CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18, + CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16), + CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17), + CPU_NVIC_SHCSR_USGFAULTENA = BIT(18), }; /* System Control Block: cache registers */ diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h index 2dcf8be660..84a82bb3f8 100644 --- a/core/cortex-m/include/mpu.h +++ b/core/cortex-m/include/mpu.h @@ -45,16 +45,16 @@ enum mpu_region { #define MPU_TYPE_UNIFIED_MASK 0x00FF0001 #define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF) -#define MPU_CTRL_PRIVDEFEN (1 << 2) -#define MPU_CTRL_HFNMIENA (1 << 1) -#define MPU_CTRL_ENABLE (1 << 0) +#define MPU_CTRL_PRIVDEFEN BIT(2) +#define MPU_CTRL_HFNMIENA BIT(1) +#define MPU_CTRL_ENABLE BIT(0) /* * XN (execute never) bit. It's bit 12 if accessed by halfword. * 0: XN off * 1: XN on */ -#define MPU_ATTR_XN (1 << 12) +#define MPU_ATTR_XN BIT(12) /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */ #define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */ diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c index 7daedbf7ab..f5a8f23c5c 100644 --- a/core/cortex-m/panic.c +++ b/core/cortex-m/panic.c @@ -199,13 +199,13 @@ static uint32_t get_exception_frame_size(const struct panic_data *pdata) /* CPU uses xPSR[9] to indicate whether it padded the stack for * alignment or not. */ - if (pdata->cm.frame[7] & (1 << 9)) + if (pdata->cm.frame[7] & BIT(9)) frame_size += sizeof(uint32_t); #ifdef CONFIG_FPU /* CPU uses EXC_RETURN[4] to indicate whether it stored extended * frame for FPU or not. */ - if (!(pdata->cm.regs[11] & (1 << 4))) + if (!(pdata->cm.regs[11] & BIT(4))) frame_size += 18 * sizeof(uint32_t); #endif diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index ef579339d1..5ab3272141 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -142,8 +142,8 @@ static const struct { static task_ tasks[TASK_ID_COUNT]; /* Reset constants and state for all tasks */ -#define TASK_RESET_SUPPORTED (1 << 31) -#define TASK_RESET_LOCK (1 << 30) +#define TASK_RESET_SUPPORTED BIT(31) +#define TASK_RESET_LOCK BIT(30) #define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) #define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK #define TASK_RESET_UNSUPPORTED 0 diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index 8df6fa5d27..f4f8e424df 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -9,6 +9,7 @@ #define __CROS_EC_CPU_H #include <stdint.h> +#include "compile_time_macros.h" /* Macro to access 32-bit registers */ #define CPUREG(addr) (*(volatile uint32_t*)(addr)) @@ -31,7 +32,7 @@ #define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c) #define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20) -#define CPU_NVIC_CCR_UNALIGN_TRAP (1 << 3) +#define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3) /* Set up the cpu to detect faults */ void cpu_init(void); diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index 32dabcaf19..9b3f8ce0ed 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -371,7 +371,7 @@ uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait) * Trigger the scheduler when there's * no other irqs happening. */ - CPU_SCB_ICSR = (1 << 28); + CPU_SCB_ICSR = BIT(28); } } else { if (wait) { diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h index f5e4353cc3..f81bbbdc03 100644 --- a/core/nds32/cpu.h +++ b/core/nds32/cpu.h @@ -11,7 +11,7 @@ #include <stdint.h> /* Process Status Word bits */ -#define PSW_GIE (1 << 0) /* Global Interrupt Enable */ +#define PSW_GIE BIT(0) /* Global Interrupt Enable */ #define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */ #define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT) diff --git a/core/nds32/panic.c b/core/nds32/panic.c index 4c855b5c06..3dabc1d2f0 100644 --- a/core/nds32/panic.c +++ b/core/nds32/panic.c @@ -174,7 +174,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype, panic_printf("Exception type: General exception [%s]\n", itype_exc_type[(itype & 0xf)]); panic_printf("Exception is caused by %s\n", - itype_inst[(itype & (1 << 4))]); + itype_inst[(itype & BIT(4))]); } #endif } diff --git a/core/nds32/task.c b/core/nds32/task.c index f713c52442..7cd9049733 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -214,7 +214,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id) void __ram_code interrupt_disable(void) { /* Mask all interrupts, only keep division by zero exception */ - uint32_t val = (1 << 30); + uint32_t val = BIT(30); asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); asm volatile ("dsb"); } @@ -222,7 +222,7 @@ void __ram_code interrupt_disable(void) void __ram_code interrupt_enable(void) { /* Enable HW2 ~ HW15 and division by zero exception interrupts */ - uint32_t val = ((1 << 30) | 0xFFFC); + uint32_t val = (BIT(30) | 0xFFFC); asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); } @@ -600,7 +600,7 @@ static void ivic_init_irqs(void) * bit0 @ INT_CTRL = 0, * Interrupts still keep programmable priority level. */ - set_int_ctrl((get_int_ctrl() & ~(1 << 0))); + set_int_ctrl((get_int_ctrl() & ~BIT(0))); /* * Re-enable global interrupts in case they're disabled. On a reboot, diff --git a/driver/accel_kx022.h b/driver/accel_kx022.h index 1d3e817f64..f7f2f848a8 100644 --- a/driver/accel_kx022.h +++ b/driver/accel_kx022.h @@ -75,34 +75,34 @@ #define KX022_INTERNAL 0x7f -#define KX022_CNTL1_PC1 (1 << 7) -#define KX022_CNTL1_WUFE (1 << 1) -#define KX022_CNTL1_TPE (1 << 0) +#define KX022_CNTL1_PC1 BIT(7) +#define KX022_CNTL1_WUFE BIT(1) +#define KX022_CNTL1_TPE BIT(0) /* TSCP orientations */ -#define KX022_ORIENT_PORTRAIT (1 << 2) -#define KX022_ORIENT_INVERT_PORTRAIT (1 << 3) -#define KX022_ORIENT_LANDSCAPE (1 << 4) -#define KX022_ORIENT_INVERT_LANDSCAPE (1 << 5) +#define KX022_ORIENT_PORTRAIT BIT(2) +#define KX022_ORIENT_INVERT_PORTRAIT BIT(3) +#define KX022_ORIENT_LANDSCAPE BIT(4) +#define KX022_ORIENT_INVERT_LANDSCAPE BIT(5) #define KX022_ORIENT_MASK (KX022_ORIENT_PORTRAIT | \ KX022_ORIENT_INVERT_PORTRAIT | \ KX022_ORIENT_LANDSCAPE | \ KX022_ORIENT_INVERT_LANDSCAPE) -#define KX022_CNTL2_SRST (1 << 7) +#define KX022_CNTL2_SRST BIT(7) #define KX022_CNTL3_OWUF_FIELD 7 -#define KX022_INC1_IEA (1 << 4) -#define KX022_INC1_IEN (1 << 5) +#define KX022_INC1_IEA BIT(4) +#define KX022_INC1_IEN BIT(5) #define KX022_GSEL_2G (0 << 3) -#define KX022_GSEL_4G (1 << 3) +#define KX022_GSEL_4G BIT(3) #define KX022_GSEL_8G (2 << 3) #define KX022_GSEL_FIELD (3 << 3) #define KX022_RES_8BIT (0 << 6) -#define KX022_RES_16BIT (1 << 6) +#define KX022_RES_16BIT BIT(6) #define KX022_OSA_0_781HZ 8 #define KX022_OSA_1_563HZ 9 @@ -127,12 +127,12 @@ #define KX022_OWUF_50_00HZ 6 #define KX022_OWUF_100_0HZ 7 -#define KX022_INC2_ZPWUE (1 << 0) -#define KX022_INC2_ZNWUE (1 << 1) -#define KX022_INC2_YPWUE (1 << 2) -#define KX022_INC2_YNWUE (1 << 3) -#define KX022_INC2_XPWUE (1 << 4) -#define KX022_INC2_XNWUE (1 << 5) +#define KX022_INC2_ZPWUE BIT(0) +#define KX022_INC2_ZNWUE BIT(1) +#define KX022_INC2_YPWUE BIT(2) +#define KX022_INC2_YNWUE BIT(3) +#define KX022_INC2_XPWUE BIT(4) +#define KX022_INC2_XNWUE BIT(5) /* Min and Max sampling frequency in mHz */ #define KX022_ACCEL_MIN_FREQ 781 diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h index e36119ccc1..823ef5dc39 100644 --- a/driver/accel_kxcj9.h +++ b/driver/accel_kxcj9.h @@ -40,34 +40,34 @@ #define KXCJ9_SELF_TEST 0x3a #define KXCJ9_WAKEUP_THRESHOLD 0x6a -#define KXCJ9_INT_SRC1_WUFS (1 << 1) -#define KXCJ9_INT_SRC1_DRDY (1 << 4) +#define KXCJ9_INT_SRC1_WUFS BIT(1) +#define KXCJ9_INT_SRC1_DRDY BIT(4) -#define KXCJ9_INT_SRC2_ZPWU (1 << 0) -#define KXCJ9_INT_SRC2_ZNWU (1 << 1) -#define KXCJ9_INT_SRC2_YPWU (1 << 2) -#define KXCJ9_INT_SRC2_YNWU (1 << 3) -#define KXCJ9_INT_SRC2_XPWU (1 << 4) -#define KXCJ9_INT_SRC2_XNWU (1 << 5) +#define KXCJ9_INT_SRC2_ZPWU BIT(0) +#define KXCJ9_INT_SRC2_ZNWU BIT(1) +#define KXCJ9_INT_SRC2_YPWU BIT(2) +#define KXCJ9_INT_SRC2_YNWU BIT(3) +#define KXCJ9_INT_SRC2_XPWU BIT(4) +#define KXCJ9_INT_SRC2_XNWU BIT(5) -#define KXCJ9_STATUS_INT (1 << 4) +#define KXCJ9_STATUS_INT BIT(4) -#define KXCJ9_CTRL1_WUFE (1 << 1) -#define KXCJ9_CTRL1_DRDYE (1 << 5) -#define KXCJ9_CTRL1_PC1 (1 << 7) +#define KXCJ9_CTRL1_WUFE BIT(1) +#define KXCJ9_CTRL1_DRDYE BIT(5) +#define KXCJ9_CTRL1_PC1 BIT(7) #define KXCJ9_GSEL_2G (0 << 3) -#define KXCJ9_GSEL_4G (1 << 3) +#define KXCJ9_GSEL_4G BIT(3) #define KXCJ9_GSEL_8G (2 << 3) #define KXCJ9_GSEL_8G_14BIT (3 << 3) #define KXCJ9_GSEL_ALL (3 << 3) #define KXCJ9_RES_8BIT (0 << 6) -#define KXCJ9_RES_12BIT (1 << 6) +#define KXCJ9_RES_12BIT BIT(6) #define KXCJ9_CTRL2_OWUF (7 << 0) -#define KXCJ9_CTRL2_DCST (1 << 4) -#define KXCJ9_CTRL2_SRST (1 << 7) +#define KXCJ9_CTRL2_DCST BIT(4) +#define KXCJ9_CTRL2_SRST BIT(7) #define KXCJ9_OWUF_0_781HZ 0 #define KXCJ9_OWUF_1_563HZ 1 @@ -78,16 +78,16 @@ #define KXCJ9_OWUF_50_00HZ 6 #define KXCJ9_OWUF_100_0HZ 7 -#define KXCJ9_INT_CTRL1_IEL (1 << 3) -#define KXCJ9_INT_CTRL1_IEA (1 << 4) -#define KXCJ9_INT_CTRL1_IEN (1 << 5) +#define KXCJ9_INT_CTRL1_IEL BIT(3) +#define KXCJ9_INT_CTRL1_IEA BIT(4) +#define KXCJ9_INT_CTRL1_IEN BIT(5) -#define KXCJ9_INT_CTRL2_ZPWUE (1 << 0) -#define KXCJ9_INT_CTRL2_ZNWUE (1 << 1) -#define KXCJ9_INT_CTRL2_YPWUE (1 << 2) -#define KXCJ9_INT_CTRL2_YNWUE (1 << 3) -#define KXCJ9_INT_CTRL2_XPWUE (1 << 4) -#define KXCJ9_INT_CTRL2_XNWUE (1 << 5) +#define KXCJ9_INT_CTRL2_ZPWUE BIT(0) +#define KXCJ9_INT_CTRL2_ZNWUE BIT(1) +#define KXCJ9_INT_CTRL2_YPWUE BIT(2) +#define KXCJ9_INT_CTRL2_YNWUE BIT(3) +#define KXCJ9_INT_CTRL2_XPWUE BIT(4) +#define KXCJ9_INT_CTRL2_XNWUE BIT(5) #define KXCJ9_OSA_0_000HZ 0 #define KXCJ9_OSA_0_781HZ 8 diff --git a/driver/accelgyro_bmi160.h b/driver/accelgyro_bmi160.h index 5b934b57a2..db6179be3e 100644 --- a/driver/accelgyro_bmi160.h +++ b/driver/accelgyro_bmi160.h @@ -78,30 +78,30 @@ #define BMI160_SENSORTIME_2 0x1a #define BMI160_STATUS 0x1b -#define BMI160_POR_DETECTED (1 << 0) -#define BMI160_GYR_SLF_TST (1 << 1) -#define BMI160_MAG_MAN_OP (1 << 2) -#define BMI160_FOC_RDY (1 << 3) -#define BMI160_NVM_RDY (1 << 4) -#define BMI160_DRDY_MAG (1 << 5) -#define BMI160_DRDY_GYR (1 << 6) -#define BMI160_DRDY_ACC (1 << 7) +#define BMI160_POR_DETECTED BIT(0) +#define BMI160_GYR_SLF_TST BIT(1) +#define BMI160_MAG_MAN_OP BIT(2) +#define BMI160_FOC_RDY BIT(3) +#define BMI160_NVM_RDY BIT(4) +#define BMI160_DRDY_MAG BIT(5) +#define BMI160_DRDY_GYR BIT(6) +#define BMI160_DRDY_ACC BIT(7) #define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) #define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) /* first 2 bytes are the interrupt reasons, next 2 some qualifier */ #define BMI160_INT_STATUS_0 0x1c -#define BMI160_STEP_INT (1 << 0) -#define BMI160_SIGMOT_INT (1 << 1) -#define BMI160_ANYM_INT (1 << 2) -#define BMI160_PMU_TRIGGER_INT (1 << 3) -#define BMI160_D_TAP_INT (1 << 4) -#define BMI160_S_TAP_INT (1 << 5) -#define BMI160_ORIENT_INT (1 << 6) -#define BMI160_FLAT_INT (1 << 7) +#define BMI160_STEP_INT BIT(0) +#define BMI160_SIGMOT_INT BIT(1) +#define BMI160_ANYM_INT BIT(2) +#define BMI160_PMU_TRIGGER_INT BIT(3) +#define BMI160_D_TAP_INT BIT(4) +#define BMI160_S_TAP_INT BIT(5) +#define BMI160_ORIENT_INT BIT(6) +#define BMI160_FLAT_INT BIT(7) #define BMI160_ORIENT_XY_MASK 0x30 #define BMI160_ORIENT_PORTRAIT (0 << 4) -#define BMI160_ORIENT_PORTRAIT_INVERT (1 << 4) +#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) #define BMI160_ORIENT_LANDSCAPE (2 << 4) #define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) @@ -138,7 +138,7 @@ #define BMI160_FIFO_LENGTH_0 0x22 #define BMI160_FIFO_LENGTH_1 0x23 -#define BMI160_FIFO_LENGTH_MASK ((1 << 11) - 1) +#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) #define BMI160_FIFO_DATA 0x24 enum fifo_header { BMI160_EMPTY = 0x80, @@ -200,13 +200,13 @@ enum fifo_header { #define BMI160_FIFO_DOWNS 0x45 #define BMI160_FIFO_CONFIG_0 0x46 #define BMI160_FIFO_CONFIG_1 0x47 -#define BMI160_FIFO_TAG_TIME_EN (1 << 1) -#define BMI160_FIFO_TAG_INT2_EN (1 << 2) -#define BMI160_FIFO_TAG_INT1_EN (1 << 3) -#define BMI160_FIFO_HEADER_EN (1 << 4) -#define BMI160_FIFO_MAG_EN (1 << 5) -#define BMI160_FIFO_ACC_EN (1 << 6) -#define BMI160_FIFO_GYR_EN (1 << 7) +#define BMI160_FIFO_TAG_TIME_EN BIT(1) +#define BMI160_FIFO_TAG_INT2_EN BIT(2) +#define BMI160_FIFO_TAG_INT1_EN BIT(3) +#define BMI160_FIFO_HEADER_EN BIT(4) +#define BMI160_FIFO_MAG_EN BIT(5) +#define BMI160_FIFO_ACC_EN BIT(6) +#define BMI160_FIFO_GYR_EN BIT(7) #define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) #define BMI160_FIFO_SENSOR_EN(_sensor) \ ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \ @@ -224,7 +224,7 @@ enum fifo_header { #define BMI160_MAG_READ_BURST_8 3 #define BMI160_MAG_OFFSET_OFF 3 #define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) -#define BMI160_MAG_MANUAL_EN (1 << 7) +#define BMI160_MAG_MANUAL_EN BIT(7) #define BMI160_MAG_IF_2 0x4d #define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 @@ -235,60 +235,60 @@ enum fifo_header { #define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G #define BMI160_INT_EN_0 0x50 -#define BMI160_INT_ANYMO_X_EN (1 << 0) -#define BMI160_INT_ANYMO_Y_EN (1 << 1) -#define BMI160_INT_ANYMO_Z_EN (1 << 2) -#define BMI160_INT_D_TAP_EN (1 << 4) -#define BMI160_INT_S_TAP_EN (1 << 5) -#define BMI160_INT_ORIENT_EN (1 << 6) -#define BMI160_INT_FLAT_EN (1 << 7) +#define BMI160_INT_ANYMO_X_EN BIT(0) +#define BMI160_INT_ANYMO_Y_EN BIT(1) +#define BMI160_INT_ANYMO_Z_EN BIT(2) +#define BMI160_INT_D_TAP_EN BIT(4) +#define BMI160_INT_S_TAP_EN BIT(5) +#define BMI160_INT_ORIENT_EN BIT(6) +#define BMI160_INT_FLAT_EN BIT(7) #define BMI160_INT_EN_1 0x51 -#define BMI160_INT_HIGHG_X_EN (1 << 0) -#define BMI160_INT_HIGHG_Y_EN (1 << 1) -#define BMI160_INT_HIGHG_Z_EN (1 << 2) -#define BMI160_INT_LOW_EN (1 << 3) -#define BMI160_INT_DRDY_EN (1 << 4) -#define BMI160_INT_FFUL_EN (1 << 5) -#define BMI160_INT_FWM_EN (1 << 6) +#define BMI160_INT_HIGHG_X_EN BIT(0) +#define BMI160_INT_HIGHG_Y_EN BIT(1) +#define BMI160_INT_HIGHG_Z_EN BIT(2) +#define BMI160_INT_LOW_EN BIT(3) +#define BMI160_INT_DRDY_EN BIT(4) +#define BMI160_INT_FFUL_EN BIT(5) +#define BMI160_INT_FWM_EN BIT(6) #define BMI160_INT_EN_2 0x52 -#define BMI160_INT_NOMOX_EN (1 << 0) -#define BMI160_INT_NOMOY_EN (1 << 1) -#define BMI160_INT_NOMOZ_EN (1 << 2) -#define BMI160_INT_STEP_DET_EN (1 << 3) +#define BMI160_INT_NOMOX_EN BIT(0) +#define BMI160_INT_NOMOY_EN BIT(1) +#define BMI160_INT_NOMOZ_EN BIT(2) +#define BMI160_INT_STEP_DET_EN BIT(3) #define BMI160_INT_OUT_CTRL 0x53 -#define BMI160_INT_EDGE_CTRL (1 << 0) -#define BMI160_INT_LVL_CTRL (1 << 1) -#define BMI160_INT_OD (1 << 2) -#define BMI160_INT_OUTPUT_EN (1 << 3) +#define BMI160_INT_EDGE_CTRL BIT(0) +#define BMI160_INT_LVL_CTRL BIT(1) +#define BMI160_INT_OD BIT(2) +#define BMI160_INT_OUTPUT_EN BIT(3) #define BMI160_INT1_CTRL_OFFSET 0 #define BMI160_INT2_CTRL_OFFSET 4 #define BMI160_INT_CTRL(_i, _bit) \ (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) #define BMI160_INT_LATCH 0x54 -#define BMI160_INT1_INPUT_EN (1 << 4) -#define BMI160_INT2_INPUT_EN (1 << 5) +#define BMI160_INT1_INPUT_EN BIT(4) +#define BMI160_INT2_INPUT_EN BIT(5) #define BMI160_LATCH_MASK 0xf #define BMI160_LATCH_NONE 0 #define BMI160_LATCH_5MS 5 #define BMI160_LATCH_FOREVER 0xf #define BMI160_INT_MAP_0 0x55 -#define BMI160_INT_LOWG_STEP (1 << 0) -#define BMI160_INT_HIGHG (1 << 1) -#define BMI160_INT_ANYMOTION (1 << 2) -#define BMI160_INT_NOMOTION (1 << 3) -#define BMI160_INT_D_TAP (1 << 4) -#define BMI160_INT_S_TAP (1 << 5) -#define BMI160_INT_ORIENT (1 << 6) -#define BMI160_INT_FLAT (1 << 7) +#define BMI160_INT_LOWG_STEP BIT(0) +#define BMI160_INT_HIGHG BIT(1) +#define BMI160_INT_ANYMOTION BIT(2) +#define BMI160_INT_NOMOTION BIT(3) +#define BMI160_INT_D_TAP BIT(4) +#define BMI160_INT_S_TAP BIT(5) +#define BMI160_INT_ORIENT BIT(6) +#define BMI160_INT_FLAT BIT(7) #define BMI160_INT_MAP_1 0x56 -#define BMI160_INT_PMU_TRIG (1 << 0) -#define BMI160_INT_FFULL (1 << 1) -#define BMI160_INT_FWM (1 << 2) -#define BMI160_INT_DRDY (1 << 3) +#define BMI160_INT_PMU_TRIG BIT(0) +#define BMI160_INT_FFULL BIT(1) +#define BMI160_INT_FWM BIT(2) +#define BMI160_INT_DRDY BIT(3) #define BMI160_INT1_MAP_OFFSET 4 #define BMI160_INT2_MAP_OFFSET 0 #define BMI160_INT_MAP(_i, _bit) \ @@ -318,8 +318,8 @@ enum fifo_header { (MIN(((_mg) * 1000) / ((_s)->drv->get_range(_s) * 1953), 0xff)) #define BMI160_INT_MOTION_2 0x61 #define BMI160_INT_MOTION_3 0x62 -#define BMI160_MOTION_NO_MOT_SEL (1 << 0) -#define BMI160_MOTION_SIG_MOT_SEL (1 << 1) +#define BMI160_MOTION_NO_MOT_SEL BIT(0) +#define BMI160_MOTION_SIG_MOT_SEL BIT(1) #define BMI160_MOTION_SKIP_OFF 2 #define BMI160_MOTION_SKIP_MASK 0x3 #define BMI160_MOTION_SKIP_TIME(_ms) \ @@ -353,7 +353,7 @@ enum fifo_header { #define BMI160_INT_FLAT_1 0x68 #define BMI160_FOC_CONF 0x69 -#define BMI160_FOC_GYRO_EN (1 << 6) +#define BMI160_FOC_GYRO_EN BIT(6) #define BMI160_FOC_ACC_PLUS_1G 1 #define BMI160_FOC_ACC_MINUS_1G 2 #define BMI160_FOC_ACC_0G 3 @@ -379,8 +379,8 @@ enum fifo_header { #define BMI160_OFFSET_GYRO_MULTI_MDS (61 * 1024) #define BMI160_OFFSET_GYRO_DIV_MDS 1000 #define BMI160_OFFSET_EN_GYR98 0x77 -#define BMI160_OFFSET_ACC_EN (1 << 6) -#define BMI160_OFFSET_GYRO_EN (1 << 7) +#define BMI160_OFFSET_ACC_EN BIT(6) +#define BMI160_OFFSET_GYRO_EN BIT(7) #define BMI160_CMD_REG 0x7e @@ -410,8 +410,8 @@ enum fifo_header { #define BMI160_CMD_EXT_MODE_EN_B2 0xc0 #define BMI160_CMD_EXT_MODE_ADDR 0x7f -#define BMI160_CMD_PAGING_EN (1 << 7) -#define BMI160_CMD_TARGET_PAGE (1 << 4) +#define BMI160_CMD_PAGING_EN BIT(7) +#define BMI160_CMD_TARGET_PAGE BIT(4) #define BMI160_COM_C_TRIM_ADDR 0x85 #define BMI160_COM_C_TRIM (3 << 4) @@ -450,7 +450,7 @@ enum bmi160_running_mode { APPLICATION_INDOOR_NAVIGATION = 8, }; -#define BMI160_FLAG_SEC_I2C_ENABLED (1 << 0) +#define BMI160_FLAG_SEC_I2C_ENABLED BIT(0) #define BMI160_FIFO_FLAG_OFFSET 4 #define BMI160_FIFO_ALL_MASK 7 diff --git a/driver/accelgyro_lsm6ds0.h b/driver/accelgyro_lsm6ds0.h index cd1fefb199..bc5574d8c1 100644 --- a/driver/accelgyro_lsm6ds0.h +++ b/driver/accelgyro_lsm6ds0.h @@ -72,7 +72,7 @@ #define LSM6DS0_INT_GEN_DUR_G 0x37 #define LSM6DS0_DPS_SEL_245 (0 << 3) -#define LSM6DS0_DPS_SEL_500 (1 << 3) +#define LSM6DS0_DPS_SEL_500 BIT(3) #define LSM6DS0_DPS_SEL_1000 (2 << 3) #define LSM6DS0_DPS_SEL_2000 (3 << 3) #define LSM6DS0_GSEL_2G (0 << 3) @@ -82,8 +82,8 @@ #define LSM6DS0_RANGE_MASK (3 << 3) #define LSM6DS0_ODR_PD (0 << 5) -#define LSM6DS0_ODR_10HZ (1 << 5) -#define LSM6DS0_ODR_15HZ (1 << 5) +#define LSM6DS0_ODR_10HZ BIT(5) +#define LSM6DS0_ODR_15HZ BIT(5) #define LSM6DS0_ODR_50HZ (2 << 5) #define LSM6DS0_ODR_59HZ (2 << 5) #define LSM6DS0_ODR_119HZ (3 << 5) diff --git a/driver/als_si114x.h b/driver/als_si114x.h index e3a19895ba..d3fcf1d64a 100644 --- a/driver/als_si114x.h +++ b/driver/als_si114x.h @@ -75,7 +75,7 @@ #define SI114X_REG_PS2_DATA1 0x29 #define SI114X_REG_PS3_DATA0 0x2a #define SI114X_REG_PS3_DATA1 0x2b -#define SI114X_PS_INVERSION(_data) ((1 << 16) / (_data)) +#define SI114X_PS_INVERSION(_data) (BIT(16) / (_data)) #define SI114X_REG_AUX_DATA0 0x2c #define SI114X_REG_AUX_DATA1 0x2d #define SI114X_REG_PARAM_RD 0x2e diff --git a/driver/battery/bq27541.c b/driver/battery/bq27541.c index 760a367b9c..2731b908bf 100644 --- a/driver/battery/bq27541.c +++ b/driver/battery/bq27541.c @@ -312,7 +312,7 @@ enum battery_disconnect_state battery_get_disconnect_state(void) rv = bq27541_read(REG_PROTECTOR, &val); if (rv) return BATTERY_DISCONNECT_ERROR; - if (!(val & (1 << 6))) { + if (!(val & BIT(6))) { not_disconnected = 1; return BATTERY_NOT_DISCONNECTED; } diff --git a/driver/battery/max17055.h b/driver/battery/max17055.h index f223fa15e8..ba18af56d5 100644 --- a/driver/battery/max17055.h +++ b/driver/battery/max17055.h @@ -55,16 +55,16 @@ #define REG_MODELCFG 0xdb /* Status reg (0x00) flags */ -#define STATUS_POR (1 << 1) -#define STATUS_IMN (1 << 2) -#define STATUS_BST (1 << 3) -#define STATUS_IMX (1 << 6) -#define STATUS_VMN (1 << 8) -#define STATUS_TMN (1 << 9) -#define STATUS_SMN (1 << 10) -#define STATUS_VMX (1 << 12) -#define STATUS_TMX (1 << 13) -#define STATUS_SMX (1 << 14) +#define STATUS_POR BIT(1) +#define STATUS_IMN BIT(2) +#define STATUS_BST BIT(3) +#define STATUS_IMX BIT(6) +#define STATUS_VMN BIT(8) +#define STATUS_TMN BIT(9) +#define STATUS_SMN BIT(10) +#define STATUS_VMX BIT(12) +#define STATUS_TMX BIT(13) +#define STATUS_SMX BIT(14) #define STATUS_ALL_ALRT \ (STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN | \ STATUS_TMX | STATUS_SMN | STATUS_SMX) @@ -76,12 +76,12 @@ #define IALRT_DISABLE 0x7f80 /* Config reg (0x1d) flags */ -#define CONF_AEN (1 << 2) -#define CONF_IS (1 << 11) -#define CONF_VS (1 << 12) -#define CONF_TS (1 << 13) -#define CONF_SS (1 << 14) -#define CONF_TSEL (1 << 15) +#define CONF_AEN BIT(2) +#define CONF_IS BIT(11) +#define CONF_VS BIT(12) +#define CONF_TS BIT(13) +#define CONF_SS BIT(14) +#define CONF_TSEL BIT(15) #define CONF_ALL_STICKY (CONF_IS | CONF_VS | CONF_TS | CONF_SS) /* FStat reg (0x3d) flags */ diff --git a/driver/battery/mm8013.h b/driver/battery/mm8013.h index 1915c81832..4dedfbd4a3 100644 --- a/driver/battery/mm8013.h +++ b/driver/battery/mm8013.h @@ -24,17 +24,17 @@ #define REG_PRODUCT_INFORMATION 0x64 /* Over Temperature in charge */ -#define MM8013_FLAG_OTC (1 << 15) +#define MM8013_FLAG_OTC BIT(15) /* Over Temperature in discharge */ -#define MM8013_FLAG_OTD (1 << 14) +#define MM8013_FLAG_OTD BIT(14) /* Over-charge */ -#define MM8013_FLAG_BATHI (1 << 13) +#define MM8013_FLAG_BATHI BIT(13) /* Full Charge */ -#define MM8013_FLAG_FC (1 << 9) +#define MM8013_FLAG_FC BIT(9) /* Charge allowed */ -#define MM8013_FLAG_CHG (1 << 8) +#define MM8013_FLAG_CHG BIT(8) /* Discharge */ -#define MM8013_FLAG_DSG (1 << 0) +#define MM8013_FLAG_DSG BIT(0) #endif /* __CROS_EC_MM8013_H */ diff --git a/driver/bc12/max14637.h b/driver/bc12/max14637.h index 7013e46fb1..38e88b4ee2 100644 --- a/driver/bc12/max14637.h +++ b/driver/bc12/max14637.h @@ -7,8 +7,8 @@ #include "gpio.h" -#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW (1 << 0) -#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW (1 << 1) +#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW BIT(0) +#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW BIT(1) struct max14637_config_t { /* diff --git a/driver/bc12/pi3usb9201.h b/driver/bc12/pi3usb9201.h index 71b235c8d1..1e60e63c47 100644 --- a/driver/bc12/pi3usb9201.h +++ b/driver/bc12/pi3usb9201.h @@ -17,19 +17,19 @@ #define PI3USB9201_REG_HOST_STS 0x3 /* Control_1 regiter bit definitions */ -#define PI3USB9201_REG_CTRL_1_INT_MASK (1 << 0) +#define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0) #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1 #define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \ PI3USB9201_REG_CTRL_1_MODE_SHIFT) /* Control_2 regiter bit definitions */ -#define PI3USB9201_REG_CTRL_2_AUTO_SW (1 << 1) -#define PI3USB9201_REG_CTRL_2_START_DET (1 << 3) +#define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1) +#define PI3USB9201_REG_CTRL_2_START_DET BIT(3) /* Host status register bit definitions */ -#define PI3USB9201_REG_HOST_STS_BC12_DET (1 << 0) -#define PI3USB9201_REG_HOST_STS_DEV_PLUG (1 << 1) -#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG (1 << 2) +#define PI3USB9201_REG_HOST_STS_BC12_DET BIT(0) +#define PI3USB9201_REG_HOST_STS_DEV_PLUG BIT(1) +#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG BIT(2) struct pi3usb2901_config_t { const int i2c_port; diff --git a/driver/charger/bd9995x.h b/driver/charger/bd9995x.h index f9fb092b24..6719fd8661 100644 --- a/driver/charger/bd9995x.h +++ b/driver/charger/bd9995x.h @@ -71,13 +71,13 @@ enum bd9995x_charge_port { #define BD9995X_CMD_CHGSTM_STATUS 0x00 #define BD9995X_CMD_VBAT_VSYS_STATUS 0x01 #define BD9995X_CMD_VBUS_VCC_STATUS 0x02 -#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT (1 << 8) -#define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT (1 << 0) +#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT BIT(8) +#define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT BIT(0) #define BD9995X_CMD_CHGOP_STATUS 0x03 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 (1 << 10) -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 (1 << 9) -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 (1 << 8) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 BIT(10) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 BIT(9) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 BIT(8) #define BD9995X_BATTTEMP_MASK 0x700 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP 0 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1 1 @@ -87,7 +87,7 @@ enum bd9995x_charge_port { #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2 5 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE 6 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN 7 -#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV (1 << 1) +#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV BIT(1) #define BD9995X_CMD_WDT_STATUS 0x04 #define BD9995X_CMD_CUR_ILIM_VAL 0x05 @@ -96,29 +96,29 @@ enum bd9995x_charge_port { #define BD9995X_CMD_EXT_ICC_LIM_SET 0x08 #define BD9995X_CMD_IOTG_LIM_SET 0x09 #define BD9995X_CMD_VIN_CTRL_SET 0x0A -#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY (1 << 4) +#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY BIT(4) -#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU (1 << 11) -#define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY (1 << 7) -#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN (1 << 6) -#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN (1 << 5) +#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU BIT(11) +#define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY BIT(7) +#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN BIT(6) +#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN BIT(5) #define BD9995X_CMD_CHGOP_SET1 0x0B -#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL (1 << 15) -#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL (1 << 14) -#define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN (1 << 13) -#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN (1 << 11) -#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN (1 << 10) -#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN (1 << 9) -#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG (1 << 8) +#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL BIT(15) +#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL BIT(14) +#define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN BIT(13) +#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN BIT(11) +#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN BIT(10) +#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN BIT(9) +#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG BIT(8) #define BD9995X_CMD_CHGOP_SET2 0x0C -#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN (1 << 8) -#define BD9995X_CMD_CHGOP_SET2_CHG_EN (1 << 7) -#define BD9995X_CMD_CHGOP_SET2_USB_SUS (1 << 6) +#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN BIT(8) +#define BD9995X_CMD_CHGOP_SET2_CHG_EN BIT(7) +#define BD9995X_CMD_CHGOP_SET2_USB_SUS BIT(6) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL (3 << 2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600 (0 << 2) -#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 (1 << 2) +#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 BIT(2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1000 (2 << 2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200 (3 << 2) @@ -145,27 +145,27 @@ enum bd9995x_charge_port { #define BD9995X_CMD_VBATOVP_SET 0x1E #define BD9995X_CMD_IBATSHORT_SET 0x1F #define BD9995X_CMD_PROCHOT_CTRL_SET 0x20 -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 (1 << 4) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 (1 << 3) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 (1 << 2) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 (1 << 1) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 (1 << 0) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 BIT(4) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 BIT(3) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 BIT(2) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 BIT(1) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 BIT(0) #define BD9995X_CMD_PROCHOT_ICRIT_SET 0x21 #define BD9995X_CMD_PROCHOT_INORM_SET 0x22 #define BD9995X_CMD_PROCHOT_IDCHG_SET 0x23 #define BD9995X_CMD_PROCHOT_VSYS_SET 0x24 #define BD9995X_CMD_PMON_IOUT_CTRL_SET 0x25 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL (1 << 9) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL (1 << 8) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN (1 << 7) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL (1 << 6) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL BIT(9) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL BIT(8) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN BIT(7) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL BIT(6) #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK 0x30 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V 0x03 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V 0x02 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V 0x01 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V 0x00 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN (1 << 3) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN BIT(3) #define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK 0x07 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW 0x06 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW 0x05 @@ -181,21 +181,21 @@ enum bd9995x_charge_port { #define BD9995X_CMD_VCC_UCD_SET 0x28 /* Bits for both VCC_UCD_SET and VBUS_UCD_SET regs */ /* Retry BC1.2 detection on set */ -#define BD9995X_CMD_UCD_SET_BCSRETRY (1 << 12) +#define BD9995X_CMD_UCD_SET_BCSRETRY BIT(12) /* Enable BC1.2 detection, will automatically occur on VBUS detect */ -#define BD9995X_CMD_UCD_SET_USBDETEN (1 << 7) +#define BD9995X_CMD_UCD_SET_USBDETEN BIT(7) /* USB switch state auto-control */ -#define BD9995X_CMD_UCD_SET_USB_SW_EN (1 << 1) +#define BD9995X_CMD_UCD_SET_USB_SW_EN BIT(1) /* USB switch state, 1 = ON, only meaningful when USB_SW_EN = 0 */ -#define BD9995X_CMD_UCD_SET_USB_SW (1 << 0) +#define BD9995X_CMD_UCD_SET_USB_SW BIT(0) #define BD9995X_CMD_VCC_UCD_STATUS 0x29 /* Bits for both VCC_UCD_STATUS and VBUS_UCD_STATUS regs */ -#define BD9995X_CMD_UCD_STATUS_DCDFAIL (1 << 15) -#define BD9995X_CMD_UCD_STATUS_CHGPORT1 (1 << 13) -#define BD9995X_CMD_UCD_STATUS_CHGPORT0 (1 << 12) -#define BD9995X_CMD_UCD_STATUS_PUPDET (1 << 11) -#define BD9995X_CMD_UCD_STATUS_CHGDET (1 << 6) +#define BD9995X_CMD_UCD_STATUS_DCDFAIL BIT(15) +#define BD9995X_CMD_UCD_STATUS_CHGPORT1 BIT(13) +#define BD9995X_CMD_UCD_STATUS_CHGPORT0 BIT(12) +#define BD9995X_CMD_UCD_STATUS_PUPDET BIT(11) +#define BD9995X_CMD_UCD_STATUS_CHGDET BIT(6) #define BD9995X_TYPE_MASK (BD9995X_CMD_UCD_STATUS_DCDFAIL | \ BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ @@ -235,17 +235,17 @@ enum bd9995x_charge_port { #define BD9995X_CMD_IC_SET1 0x3A #define BD9995X_CMD_IC_SET2 0x3B #define BD9995X_CMD_SYSTEM_STATUS 0x3C -#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE (1 << 1) -#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE (1 << 0) +#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE BIT(1) +#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE BIT(0) #define BD9995X_CMD_SYSTEM_CTRL_SET 0x3D -#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD (1 << 1) -#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST (1 << 0) +#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD BIT(1) +#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST BIT(0) #define BD9995X_CMD_EXT_PROTECT_SET 0x3E #define BD9995X_CMD_EXT_MAP_SET 0x3F #define BD9995X_CMD_VM_CTRL_SET 0x40 -#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN (1 << 9) +#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN BIT(9) #define BD9995X_CMD_THERM_WINDOW_SET1 0x41 #define BD9995X_CMD_THERM_WINDOW_SET2 0x42 #define BD9995X_CMD_THERM_WINDOW_SET3 0x43 @@ -287,16 +287,16 @@ enum bd9995x_charge_port { #define BD9995X_CMD_EXTIADP_AVE_VAL 0x63 #define BD9995X_CMD_VACPCLPS_TH_SET 0x64 #define BD9995X_CMD_INT0_SET 0x68 -#define BD9995X_CMD_INT0_SET_INT2_EN (1 << 2) -#define BD9995X_CMD_INT0_SET_INT1_EN (1 << 1) -#define BD9995X_CMD_INT0_SET_INT0_EN (1 << 0) +#define BD9995X_CMD_INT0_SET_INT2_EN BIT(2) +#define BD9995X_CMD_INT0_SET_INT1_EN BIT(1) +#define BD9995X_CMD_INT0_SET_INT0_EN BIT(0) #define BD9995X_CMD_INT1_SET 0x69 /* Bits for both INT1 & INT2 reg */ -#define BD9995X_CMD_INT_SET_TH_DET (1 << 9) -#define BD9995X_CMD_INT_SET_TH_RES (1 << 8) -#define BD9995X_CMD_INT_SET_DET (1 << 1) -#define BD9995X_CMD_INT_SET_RES (1 << 0) +#define BD9995X_CMD_INT_SET_TH_DET BIT(9) +#define BD9995X_CMD_INT_SET_TH_RES BIT(8) +#define BD9995X_CMD_INT_SET_DET BIT(1) +#define BD9995X_CMD_INT_SET_RES BIT(0) #define BD9995X_CMD_INT_VBUS_DET (BD9995X_CMD_INT_SET_RES | \ BD9995X_CMD_INT_SET_DET) #define BD9995X_CMD_INT_VBUS_TH (BD9995X_CMD_INT_SET_TH_RES | \ @@ -311,8 +311,8 @@ enum bd9995x_charge_port { #define BD9995X_CMD_INT0_STATUS 0x70 #define BD9995X_CMD_INT1_STATUS 0x71 /* Bits for both INT1_STATUS & INT2_STATUS reg */ -#define BD9995X_CMD_INT_STATUS_DET (1 << 1) -#define BD9995X_CMD_INT_STATUS_RES (1 << 0) +#define BD9995X_CMD_INT_STATUS_DET BIT(1) +#define BD9995X_CMD_INT_STATUS_RES BIT(0) #define BD9995X_CMD_INT2_STATUS 0x72 #define BD9995X_CMD_INT3_STATUS 0x73 diff --git a/driver/charger/bq24192.c b/driver/charger/bq24192.c index 8c82b84475..5d7ca58862 100644 --- a/driver/charger/bq24192.c +++ b/driver/charger/bq24192.c @@ -53,7 +53,7 @@ static int bq24192_watchdog_reset(void) rv = bq24192_read(BQ24192_REG_POWER_ON_CFG, &val); if (rv) return rv; - val |= (1 << 6); + val |= BIT(6); return bq24192_write(BQ24192_REG_POWER_ON_CFG, val) || bq24192_write(BQ24192_REG_POWER_ON_CFG, val); } diff --git a/driver/charger/bq24707a.h b/driver/charger/bq24707a.h index 14e89ed136..ac3293e04d 100644 --- a/driver/charger/bq24707a.h +++ b/driver/charger/bq24707a.h @@ -15,28 +15,28 @@ #define BQ24707_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) +#define OPTION_CHARGE_INHIBIT BIT(0) #define OPTION_ACOC_THRESHOLD (3 << 1) -#define OPTION_COMPARATOR_THRESHOLD (1 << 4) -#define OPTION_IOUT_SELECTION (1 << 5) +#define OPTION_COMPARATOR_THRESHOLD BIT(4) +#define OPTION_IOUT_SELECTION BIT(5) #define OPTION_IFAULT_HI_THRESHOLD (3 << 7) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_AOC_DELITCH_TIME (1 << 15) +#define OPTION_AOC_DELITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) #define ACOC_THRESHOLD_166X_DEFAULT (2 << 1) #define ACOC_THRESHOLD_222X (3 << 1) /* OPTION_IFAULT_HI_THRESHOLD */ #define IFAULT_THRESHOLD_300MV (0 << 7) -#define IFAULT_THRESHOLD_500MV (1 << 7) +#define IFAULT_THRESHOLD_500MV BIT(7) #define IFAULT_THRESHOLD_700MV_DEFAULT (2 << 7) #define IFAULT_THRESHOLD_900MV (3 << 7) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) diff --git a/driver/charger/bq24715.h b/driver/charger/bq24715.h index bb5deec902..669dc542ed 100644 --- a/driver/charger/bq24715.h +++ b/driver/charger/bq24715.h @@ -23,63 +23,63 @@ #define BQ24715_DEVICE_ID 0xff /* ChargeOption Register - 0x12 */ -#define OPT_LOWPOWER_MASK (1 << 15) +#define OPT_LOWPOWER_MASK BIT(15) #define OPT_LOWPOWER_DSCHRG_I_MON_ON (0 << 15) -#define OPT_LOWPOWER_DSCHRG_I_MON_OFF (1 << 15) +#define OPT_LOWPOWER_DSCHRG_I_MON_OFF BIT(15) #define OPT_WATCHDOG_MASK (3 << 13) #define OPT_WATCHDOG_DISABLE (0 << 13) -#define OPT_WATCHDOG_44SEC (1 << 13) +#define OPT_WATCHDOG_44SEC BIT(13) #define OPT_WATCHDOG_88SEC (2 << 13) #define OPT_WATCHDOG_175SEC (3 << 13) -#define OPT_SYSOVP_MASK (1 << 12) +#define OPT_SYSOVP_MASK BIT(12) #define OPT_SYSOVP_15P1_3SEC_10P1_2SEC (0 << 12) -#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC (1 << 12) -#define OPT_SYSOVP_STATUS_MASK (1 << 11) -#define OPT_SYSOVP_STATUS (1 << 11) -#define OPT_AUDIO_FREQ_LIMIT_MASK (1 << 10) +#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC BIT(12) +#define OPT_SYSOVP_STATUS_MASK BIT(11) +#define OPT_SYSOVP_STATUS BIT(11) +#define OPT_AUDIO_FREQ_LIMIT_MASK BIT(10) #define OPT_AUDIO_FREQ_NO_LIMIT (0 << 10) -#define OPT_AUDIO_FREQ_40KHZ_LIMIT (1 << 10) +#define OPT_AUDIO_FREQ_40KHZ_LIMIT BIT(10) #define OPT_SWITCH_FREQ_MASK (3 << 8) #define OPT_SWITCH_FREQ_600KHZ (0 << 8) -#define OPT_SWITCH_FREQ_800KHZ (1 << 8) +#define OPT_SWITCH_FREQ_800KHZ BIT(8) #define OPT_SWITCH_FREQ_1MHZ (2 << 8) #define OPT_SWITCH_FREQ_800KHZ_DUP (3 << 8) -#define OPT_ACOC_MASK (1 << 7) +#define OPT_ACOC_MASK BIT(7) #define OPT_ACOC_DISABLED (0 << 7) -#define OPT_ACOC_333PCT_IPDM (1 << 7) -#define OPT_LSFET_OCP_MASK (1 << 6) +#define OPT_ACOC_333PCT_IPDM BIT(7) +#define OPT_LSFET_OCP_MASK BIT(6) #define OPT_LSFET_OCP_250MV (0 << 6) -#define OPT_LSFET_OCP_350MV (1 << 6) -#define OPT_LEARN_MASK (1 << 5) +#define OPT_LSFET_OCP_350MV BIT(6) +#define OPT_LEARN_MASK BIT(5) #define OPT_LEARN_DISABLE (0 << 5) -#define OPT_LEARN_ENABLE (1 << 5) -#define OPT_IOUT_MASK (1 << 4) +#define OPT_LEARN_ENABLE BIT(5) +#define OPT_IOUT_MASK BIT(4) #define OPT_IOUT_40X (0 << 4) -#define OPT_IOUT_16X (1 << 4) -#define OPT_FIX_IOUT_MASK (1 << 3) +#define OPT_IOUT_16X BIT(4) +#define OPT_FIX_IOUT_MASK BIT(3) #define OPT_FIX_IOUT_IDPM_EN (0 << 3) -#define OPT_FIX_IOUT_ALWAYS (1 << 3) -#define OPT_LDO_MODE_MASK (1 << 2) +#define OPT_FIX_IOUT_ALWAYS BIT(3) +#define OPT_LDO_MODE_MASK BIT(2) #define OPT_LDO_DISABLE (0 << 2) -#define OPT_LDO_ENABLE (1 << 2) -#define OPT_IDPM_MASK (1 << 1) +#define OPT_LDO_ENABLE BIT(2) +#define OPT_IDPM_MASK BIT(1) #define OPT_IDPM_DISABLE (0 << 1) -#define OPT_IDPM_ENABLE (1 << 1) -#define OPT_CHARGE_INHIBIT_MASK (1 << 0) +#define OPT_IDPM_ENABLE BIT(1) +#define OPT_CHARGE_INHIBIT_MASK BIT(0) #define OPT_CHARGE_ENABLE (0 << 0) -#define OPT_CHARGE_DISABLE (1 << 0) +#define OPT_CHARGE_DISABLE BIT(0) /* ChargeCurrent Register - 0x14 * The ChargeCurrent register controls a DAC. Therefore * the below definitions are cummulative. */ -#define CHARGE_I_64MA (1 << 6) -#define CHARGE_I_128MA (1 << 7) -#define CHARGE_I_256MA (1 << 8) -#define CHARGE_I_512MA (1 << 9) -#define CHARGE_I_1024MA (1 << 10) -#define CHARGE_I_2048MA (1 << 11) -#define CHARGE_I_4096MA (1 << 12) +#define CHARGE_I_64MA BIT(6) +#define CHARGE_I_128MA BIT(7) +#define CHARGE_I_256MA BIT(8) +#define CHARGE_I_512MA BIT(9) +#define CHARGE_I_1024MA BIT(10) +#define CHARGE_I_2048MA BIT(11) +#define CHARGE_I_4096MA BIT(12) #define CHARGE_I_OFF (0) #define CHARGE_I_MIN (128) #define CHARGE_I_MAX (8128) @@ -88,16 +88,16 @@ /* MaxChargeVoltage Register - 0x15 * The MaxChargeVoltage register controls a DAC. Therefore * the below definitions are cummulative. */ -#define CHARGE_V_16MV (1 << 4) -#define CHARGE_V_32MV (1 << 5) -#define CHARGE_V_64MV (1 << 6) -#define CHARGE_V_128MV (1 << 7) -#define CHARGE_V_256MV (1 << 8) -#define CHARGE_V_512MV (1 << 9) -#define CHARGE_V_1024MV (1 << 10) -#define CHARGE_V_2048MV (1 << 11) -#define CHARGE_V_4096MV (1 << 12) -#define CHARGE_V_8192MV (1 << 13) +#define CHARGE_V_16MV BIT(4) +#define CHARGE_V_32MV BIT(5) +#define CHARGE_V_64MV BIT(6) +#define CHARGE_V_128MV BIT(7) +#define CHARGE_V_256MV BIT(8) +#define CHARGE_V_512MV BIT(9) +#define CHARGE_V_1024MV BIT(10) +#define CHARGE_V_2048MV BIT(11) +#define CHARGE_V_4096MV BIT(12) +#define CHARGE_V_8192MV BIT(13) #define CHARGE_V_MIN (4096) #define CHARGE_V_MAX (0x3ff0) #define CHARGE_V_STEP (16) @@ -105,24 +105,24 @@ /* MinSystemVoltage Register - 0x3e * The MinSystemVoltage register controls a DAC. Therefore * the below definitions are cummulative. */ -#define MIN_SYS_V_256MV (1 << 8) -#define MIN_SYS_V_512MV (1 << 9) -#define MIN_SYS_V_1024MV (1 << 10) -#define MIN_SYS_V_2048MV (1 << 11) -#define MIN_SYS_V_4096MV (1 << 12) -#define MIN_SYS_V_8192MV (1 << 13) +#define MIN_SYS_V_256MV BIT(8) +#define MIN_SYS_V_512MV BIT(9) +#define MIN_SYS_V_1024MV BIT(10) +#define MIN_SYS_V_2048MV BIT(11) +#define MIN_SYS_V_4096MV BIT(12) +#define MIN_SYS_V_8192MV BIT(13) #define MIN_SYS_V_MIN (4096) /* InputCurrent Register - 0x3f * The InputCurrent register controls a DAC. Therefore * the below definitions are cummulative. */ -#define INPUT_I_64MA (1 << 6) -#define INPUT_I_128MA (1 << 7) -#define INPUT_I_256MA (1 << 8) -#define INPUT_I_512MA (1 << 9) -#define INPUT_I_1024MA (1 << 10) -#define INPUT_I_2048MA (1 << 11) -#define INPUT_I_4096MA (1 << 12) +#define INPUT_I_64MA BIT(6) +#define INPUT_I_128MA BIT(7) +#define INPUT_I_256MA BIT(8) +#define INPUT_I_512MA BIT(9) +#define INPUT_I_1024MA BIT(10) +#define INPUT_I_2048MA BIT(11) +#define INPUT_I_4096MA BIT(12) #define INPUT_I_MIN (128) #define INPUT_I_MAX (8064) #define INPUT_I_STEP (64) diff --git a/driver/charger/bq24725.h b/driver/charger/bq24725.h index b935501a20..c53019a2aa 100644 --- a/driver/charger/bq24725.h +++ b/driver/charger/bq24725.h @@ -15,34 +15,34 @@ #define BQ24725_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) +#define OPTION_CHARGE_INHIBIT BIT(0) #define OPTION_ACOC_THRESHOLD (3 << 1) -#define OPTION_IOUT_SELECTION (1 << 5) -#define OPTION_LEARN_ENABLE (1 << 6) +#define OPTION_IOUT_SELECTION BIT(5) +#define OPTION_LEARN_ENABLE BIT(6) #define OPTION_IFAULT_HI_THRESHOLD (3 << 7) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_BAT_DEPLETION_THRESHOLD (3 << 11) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_AOC_DELITCH_TIME (1 << 15) +#define OPTION_AOC_DELITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) #define ACOC_THRESHOLD_166X_DEFAULT (2 << 1) #define ACOC_THRESHOLD_222X (3 << 1) /* OPTION_IFAULT_HI_THRESHOLD */ #define IFAULT_THRESHOLD_300MV (0 << 7) -#define IFAULT_THRESHOLD_500MV (1 << 7) +#define IFAULT_THRESHOLD_500MV BIT(7) #define IFAULT_THRESHOLD_700MV_DEFAULT (2 << 7) #define IFAULT_THRESHOLD_900MV (3 << 7) /* OPTION_BAT_DEPLETION_THRESHOLD */ #define FALLING_THRESHOLD_5919 (0 << 11) -#define FALLING_THRESHOLD_6265 (1 << 11) +#define FALLING_THRESHOLD_6265 BIT(11) #define FALLING_THRESHOLD_6655 (2 << 11) #define FALLING_THRESHOLD_7097_DEFAULT (3 << 11) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) diff --git a/driver/charger/bq24735.h b/driver/charger/bq24735.h index 05336cb41c..e29b9aa692 100644 --- a/driver/charger/bq24735.h +++ b/driver/charger/bq24735.h @@ -15,43 +15,43 @@ #define BQ24735_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) -#define OPTION_ACOC_THRESHOLD (1 << 1) -#define OPTION_BOOST_MODE_STATE (1 << 2) -#define OPTION_BOOST_MODE_ENABLE (1 << 3) -#define OPTION_ACDET_STATE (1 << 4) -#define OPTION_IOUT_SELECTION (1 << 5) -#define OPTION_LEARN_ENABLE (1 << 6) -#define OPTION_IFAULT_LOW_THRESHOLD (1 << 7) -#define OPTION_IFAULT_HI_ENABLE (1 << 8) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_CHARGE_INHIBIT BIT(0) +#define OPTION_ACOC_THRESHOLD BIT(1) +#define OPTION_BOOST_MODE_STATE BIT(2) +#define OPTION_BOOST_MODE_ENABLE BIT(3) +#define OPTION_ACDET_STATE BIT(4) +#define OPTION_IOUT_SELECTION BIT(5) +#define OPTION_LEARN_ENABLE BIT(6) +#define OPTION_IFAULT_LOW_THRESHOLD BIT(7) +#define OPTION_IFAULT_HI_ENABLE BIT(8) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_BAT_DEPLETION_THRESHOLD (3 << 11) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_ACPRES_DEGLITCH_TIME (1 << 15) +#define OPTION_ACPRES_DEGLITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) /* OPTION_IFAULT_LOW_THRESHOLD */ #define IFAULT_LOW_135MV_DEFAULT (0 << 7) -#define IFAULT_LOW_230MV (1 << 7) +#define IFAULT_LOW_230MV BIT(7) /* OPTION_BAT_DEPLETION_THRESHOLD */ #define FALLING_THRESHOLD_5919 (0 << 11) -#define FALLING_THRESHOLD_6265 (1 << 11) +#define FALLING_THRESHOLD_6265 BIT(11) #define FALLING_THRESHOLD_6655 (2 << 11) #define FALLING_THRESHOLD_7097_DEFAULT (3 << 11) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) /* OPTION_ACPRES_DEGLITCH_TIME */ #define ACPRES_DEGLITCH_150MS (0 << 15) -#define ACPRES_DEGLITCH_1300MS_DEFAULT (1 << 15) +#define ACPRES_DEGLITCH_1300MS_DEFAULT BIT(15) #endif /* __CROS_EC_BQ24735_H */ diff --git a/driver/charger/bq24738.h b/driver/charger/bq24738.h index a40a9e193f..194a2941c0 100644 --- a/driver/charger/bq24738.h +++ b/driver/charger/bq24738.h @@ -15,43 +15,43 @@ #define BQ24738_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) -#define OPTION_ACOC_THRESHOLD (1 << 1) -#define OPTION_BOOST_MODE_STATE (1 << 2) -#define OPTION_BOOST_MODE_ENABLE (1 << 3) -#define OPTION_ACDET_STATE (1 << 4) -#define OPTION_IOUT_SELECTION (1 << 5) -#define OPTION_LEARN_ENABLE (1 << 6) -#define OPTION_IFAULT_LOW_THRESHOLD (1 << 7) -#define OPTION_IFAULT_HI_ENABLE (1 << 8) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_CHARGE_INHIBIT BIT(0) +#define OPTION_ACOC_THRESHOLD BIT(1) +#define OPTION_BOOST_MODE_STATE BIT(2) +#define OPTION_BOOST_MODE_ENABLE BIT(3) +#define OPTION_ACDET_STATE BIT(4) +#define OPTION_IOUT_SELECTION BIT(5) +#define OPTION_LEARN_ENABLE BIT(6) +#define OPTION_IFAULT_LOW_THRESHOLD BIT(7) +#define OPTION_IFAULT_HI_ENABLE BIT(8) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_BAT_DEPLETION_THRESHOLD (3 << 11) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_ACPRES_DEGLITCH_TIME (1 << 15) +#define OPTION_ACPRES_DEGLITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) /* OPTION_IFAULT_LOW_THRESHOLD */ #define IFAULT_LOW_135MV_DEFAULT (0 << 7) -#define IFAULT_LOW_230MV (1 << 7) +#define IFAULT_LOW_230MV BIT(7) /* OPTION_BAT_DEPLETION_THRESHOLD */ #define FALLING_THRESHOLD_5919 (0 << 11) -#define FALLING_THRESHOLD_6265 (1 << 11) +#define FALLING_THRESHOLD_6265 BIT(11) #define FALLING_THRESHOLD_6655 (2 << 11) #define FALLING_THRESHOLD_7097_DEFAULT (3 << 11) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) /* OPTION_ACPRES_DEGLITCH_TIME */ #define ACPRES_DEGLITCH_150MS (0 << 15) -#define ACPRES_DEGLITCH_1300MS_DEFAULT (1 << 15) +#define ACPRES_DEGLITCH_1300MS_DEFAULT BIT(15) #endif /* __CROS_EC_BQ24738_H */ diff --git a/driver/charger/bq24773.h b/driver/charger/bq24773.h index 216e3d4c77..2f1a7ffad2 100644 --- a/driver/charger/bq24773.h +++ b/driver/charger/bq24773.h @@ -41,15 +41,15 @@ #define BQ24773_CHARGE_OPTION2 0x10 /* Option bits */ -#define OPTION0_CHARGE_INHIBIT (1 << 0) -#define OPTION0_LEARN_ENABLE (1 << 5) +#define OPTION0_CHARGE_INHIBIT BIT(0) +#define OPTION0_LEARN_ENABLE BIT(5) #define OPTION0_SWITCHING_FREQ_MASK (3 << 8) #define OPTION0_SWITCHING_FREQ_600KHZ (0 << 8) -#define OPTION0_SWITCHING_FREQ_800KHZ (1 << 8) +#define OPTION0_SWITCHING_FREQ_800KHZ BIT(8) #define OPTION0_SWITCHING_FREQ_1000KHZ (2 << 8) #define OPTION0_SWITCHING_FREQ_1200KHZ (3 << 8) -#define OPTION2_EN_EXTILIM (1 << 7) +#define OPTION2_EN_EXTILIM BIT(7) /* Prochot Option bits */ #define PROCHOT_OPTION1_SELECTOR_MASK 0x7f /* [6:0] PROCHOT SELECTOR */ diff --git a/driver/charger/bq25703.h b/driver/charger/bq25703.h index db2c246658..54d64a81c7 100644 --- a/driver/charger/bq25703.h +++ b/driver/charger/bq25703.h @@ -24,9 +24,9 @@ /* ChargeOption0 Register */ #define BQ25703_REG_CHARGE_OPTION_0 0x00 -#define BQ25703_CHARGE_OPTION_0_LOW_POWER_MODE (1 << 15) -#define BQ25703_CHARGE_OPTION_0_EN_LEARN (1 << 5) -#define BQ25703_CHARGE_OPTION_0_CHRG_INHIBIT (1 << 0) +#define BQ25703_CHARGE_OPTION_0_LOW_POWER_MODE BIT(15) +#define BQ25703_CHARGE_OPTION_0_EN_LEARN BIT(5) +#define BQ25703_CHARGE_OPTION_0_CHRG_INHIBIT BIT(0) #define BQ25703_REG_CHARGE_CURRENT 0x02 #define BQ25703_REG_MAX_CHARGE_VOLTAGE 0x04 @@ -34,23 +34,23 @@ /* ChargeOption2 Register */ #define BQ25703_REG_CHARGE_OPTION_2 0x32 -#define BQ25703_CHARGE_OPTION_2_EN_EXTILIM (1 << 7) +#define BQ25703_CHARGE_OPTION_2_EN_EXTILIM BIT(7) /* ChargeOption3 Register */ #define BQ25703_REG_CHARGE_OPTION_3 0x34 -#define BQ25703_CHARGE_OPTION_3_EN_ICO_MODE (1 << 11) +#define BQ25703_CHARGE_OPTION_3_EN_ICO_MODE BIT(11) #define BQ25703_REG_PROCHOT_OPTION_0 0x36 #define BQ25703_REG_PROCHOT_OPTION_1 0x38 /* ADCOption Register */ #define BQ25703_REG_ADC_OPTION 0x3A -#define BQ25703_ADC_OPTION_ADC_START (1 << 14) -#define BQ25703_ADC_OPTION_EN_ADC_IIN (1 << 4) +#define BQ25703_ADC_OPTION_ADC_START BIT(14) +#define BQ25703_ADC_OPTION_EN_ADC_IIN BIT(4) /* ChargeStatus Register */ #define BQ25703_REG_CHARGER_STATUS 0x20 -#define BQ25703_CHARGE_STATUS_ICO_DONE (1 << 14) +#define BQ25703_CHARGE_STATUS_ICO_DONE BIT(14) #define BQ25703_REG_PROCHOT_STATUS 0x22 #define BQ25703_REG_IIN_DPM 0x25 diff --git a/driver/charger/bq25710.h b/driver/charger/bq25710.h index 086bf13edb..73d7545c06 100644 --- a/driver/charger/bq25710.h +++ b/driver/charger/bq25710.h @@ -40,27 +40,27 @@ #define BQ25710_REG_DEVICE_ADDRESS 0xFF /* ChargeOption0 Register */ -#define BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE (1 << 15) -#define BQ25710_CHARGE_OPTION_0_EN_LEARN (1 << 5) -#define BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT (1 << 0) +#define BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE BIT(15) +#define BQ25710_CHARGE_OPTION_0_EN_LEARN BIT(5) +#define BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT BIT(0) /* ChargeOption2 Register */ -#define BQ25710_CHARGE_OPTION_2_EN_EXTILIM (1 << 7) +#define BQ25710_CHARGE_OPTION_2_EN_EXTILIM BIT(7) /* ChargeOption3 Register */ -#define BQ25710_CHARGE_OPTION_3_EN_ICO_MODE (1 << 11) +#define BQ25710_CHARGE_OPTION_3_EN_ICO_MODE BIT(11) /* ChargeStatus Register */ -#define BQ25710_CHARGE_STATUS_ICO_DONE (1 << 14) +#define BQ25710_CHARGE_STATUS_ICO_DONE BIT(14) /* IIN_DPM Register */ #define BQ25710_CHARGE_IIN_BIT_0FFSET 8 #define BQ25710_CHARGE_MA_PER_STEP 50 /* ADCOption Register */ -#define BQ25710_ADC_OPTION_ADC_START (1 << 14) -#define BQ25710_ADC_OPTION_EN_ADC_VBUS (1 << 6) -#define BQ25710_ADC_OPTION_EN_ADC_IIN (1 << 4) +#define BQ25710_ADC_OPTION_ADC_START BIT(14) +#define BQ25710_ADC_OPTION_EN_ADC_VBUS BIT(6) +#define BQ25710_ADC_OPTION_EN_ADC_IIN BIT(4) #define BQ25710_ADC_OPTION_EN_ADC_ALL 0xFF /* ADCVBUS/PSYS Register */ @@ -73,6 +73,6 @@ #define BQ25710_ADC_IIN_STEP_BIT_OFFSET 8 /* ProchotOption1 Register */ -#define BQ25710_PROCHOT_PROFILE_VDPM (1 << 7) +#define BQ25710_PROCHOT_PROFILE_VDPM BIT(7) #endif /* __CROS_EC_BQ25710_H */ diff --git a/driver/charger/bq2589x.h b/driver/charger/bq2589x.h index ed49aeb661..c13d34ec7d 100644 --- a/driver/charger/bq2589x.h +++ b/driver/charger/bq2589x.h @@ -52,7 +52,7 @@ #define BQ2589X_IR_BAT_COMP_80MOHM (4 << 5) #define BQ2589X_IR_BAT_COMP_60MOHM (3 << 5) #define BQ2589X_IR_BAT_COMP_40MOHM (2 << 5) -#define BQ2589X_IR_BAT_COMP_20MOHM (1 << 5) +#define BQ2589X_IR_BAT_COMP_20MOHM BIT(5) #define BQ2589X_IR_BAT_COMP_0MOHM (0 << 5) #define BQ2589X_IR_VCLAMP_224MV (7 << 2) #define BQ2589X_IR_VCLAMP_192MV (6 << 2) @@ -60,11 +60,11 @@ #define BQ2589X_IR_VCLAMP_128MV (4 << 2) #define BQ2589X_IR_VCLAMP_96MV (3 << 2) #define BQ2589X_IR_VCLAMP_64MV (2 << 2) -#define BQ2589X_IR_VCLAMP_32MV (1 << 2) +#define BQ2589X_IR_VCLAMP_32MV BIT(2) #define BQ2589X_IR_VCLAMP_0MV (0 << 2) #define BQ2589X_IR_TREG_120C (3 << 0) #define BQ2589X_IR_TREG_100C (2 << 0) -#define BQ2589X_IR_TREG_80C (1 << 0) +#define BQ2589X_IR_TREG_80C BIT(0) #define BQ2589X_IR_TREG_60C (0 << 0) #define BQ2589X_IR_COMP_DEFAULT (BQ2589X_IR_TREG_120C | BQ2589X_IR_VCLAMP_0MV |\ diff --git a/driver/charger/isl923x.h b/driver/charger/isl923x.h index 118f22b77d..7947ce07bb 100644 --- a/driver/charger/isl923x.h +++ b/driver/charger/isl923x.h @@ -63,7 +63,7 @@ /* PROCHOT# debounce time and duration time in micro seconds */ #define ISL923X_PROCHOT_DURATION_10000 (0 << 6) -#define ISL923X_PROCHOT_DURATION_20000 (1 << 6) +#define ISL923X_PROCHOT_DURATION_20000 BIT(6) #define ISL923X_PROCHOT_DURATION_15000 (2 << 6) #define ISL923X_PROCHOT_DURATION_5000 (3 << 6) #define ISL923X_PROCHOT_DURATION_1000 (4 << 6) @@ -73,7 +73,7 @@ #define ISL923X_PROCHOT_DURATION_MASK (7 << 6) #define ISL923X_PROCHOT_DEBOUNCE_10 (0 << 9) -#define ISL923X_PROCHOT_DEBOUNCE_100 (1 << 9) +#define ISL923X_PROCHOT_DEBOUNCE_100 BIT(9) #define ISL923X_PROCHOT_DEBOUNCE_500 (2 << 9) #define ISL923X_PROCHOT_DEBOUNCE_1000 (3 << 9) #define ISL923X_PROCHOT_DEBOUNCE_MASK (3 << 9) @@ -90,35 +90,35 @@ #define ISL9237_C0_VREG_REF_MASK 0x03 /* Control0: disable adapter voltaqe regulation */ -#define ISL923X_C0_DISABLE_VREG (1 << 2) +#define ISL923X_C0_DISABLE_VREG BIT(2) /* Control0: battery DCHOT reference for RS2 == 20mOhm */ #define ISL923X_C0_DCHOT_6A (0 << 3) -#define ISL923X_C0_DCHOT_5A (1 << 3) +#define ISL923X_C0_DCHOT_5A BIT(3) #define ISL923X_C0_DCHOT_4A (2 << 3) #define ISL923X_C0_DCHOT_3A (3 << 3) #define ISL923X_C0_DCHOT_MASK (3 << 3) /* Control1: general purpose comparator debounce time in micro second */ #define ISL923X_C1_GP_DEBOUNCE_2 (0 << 14) -#define ISL923X_C1_GP_DEBOUNCE_12 (1 << 14) +#define ISL923X_C1_GP_DEBOUNCE_12 BIT(14) #define ISL923X_C1_GP_DEBOUNCE_2000 (2 << 14) #define ISL923X_C1_GP_DEBOUNCE_5000000 (3 << 14) #define ISL923X_C1_GP_DEBOUNCE_MASK (3 << 14) /* Control1: learn mode */ -#define ISL923X_C1_LEARN_MODE_AUTOEXIT (1 << 13) -#define ISL923X_C1_LEARN_MODE_ENABLE (1 << 12) +#define ISL923X_C1_LEARN_MODE_AUTOEXIT BIT(13) +#define ISL923X_C1_LEARN_MODE_ENABLE BIT(12) /* Control1: OTG enable */ -#define ISL923X_C1_OTG (1 << 11) +#define ISL923X_C1_OTG BIT(11) /* Control1: audio filter */ -#define ISL923X_C1_AUDIO_FILTER (1 << 10) +#define ISL923X_C1_AUDIO_FILTER BIT(10) /* Control1: switch frequency, ISL9238 defines bit 7 as unused */ #define ISL923X_C1_SWITCH_FREQ_PROG (0 << 7) /* 1000kHz or PROG */ -#define ISL9237_C1_SWITCH_FREQ_913K (1 << 7) +#define ISL9237_C1_SWITCH_FREQ_913K BIT(7) #define ISL923X_C1_SWITCH_FREQ_839K (2 << 7) #define ISL9237_C1_SWITCH_FREQ_777K (3 << 7) #define ISL923X_C1_SWITCH_FREQ_723K (4 << 7) @@ -128,15 +128,15 @@ #define ISL923X_C1_SWITCH_FREQ_MASK (7 << 7) /* Control1: turbo mode */ -#define ISL923X_C1_TURBO_MODE (1 << 6) +#define ISL923X_C1_TURBO_MODE BIT(6) /* Control1: AMON & BMON */ -#define ISL923X_C1_DISABLE_MON (1 << 5) -#define ISL923X_C1_SELECT_BMON (1 << 4) +#define ISL923X_C1_DISABLE_MON BIT(5) +#define ISL923X_C1_SELECT_BMON BIT(4) /* Control1: PSYS, VSYS, VSYSLO */ -#define ISL923X_C1_ENABLE_PSYS (1 << 3) -#define ISL923X_C1_ENABLE_VSYS (1 << 2) +#define ISL923X_C1_ENABLE_PSYS BIT(3) +#define ISL923X_C1_ENABLE_VSYS BIT(2) #define ISL923X_C1_VSYSLO_REF_6000 0 #define ISL923X_C1_VSYSLO_REF_6300 1 #define ISL923X_C1_VSYSLO_REF_6600 2 @@ -145,35 +145,35 @@ /* Control2: trickle charging current in mA */ #define ISL923X_C2_TRICKLE_256 (0 << 14) -#define ISL923X_C2_TRICKLE_128 (1 << 14) +#define ISL923X_C2_TRICKLE_128 BIT(14) #define ISL923X_C2_TRICKLE_64 (2 << 14) #define ISL923X_C2_TRICKLE_512 (3 << 14) #define ISL923X_C2_TRICKLE_MASK (3 << 14) /* Control2: OTGEN debounce time in ms */ #define ISL923X_C2_OTG_DEBOUNCE_1300 (0 << 13) -#define ISL923X_C2_OTG_DEBOUNCE_150 (1 << 13) -#define ISL923X_C2_OTG_DEBOUNCE_MASK (1 << 13) +#define ISL923X_C2_OTG_DEBOUNCE_150 BIT(13) +#define ISL923X_C2_OTG_DEBOUNCE_MASK BIT(13) /* Control2: 2-level adapter over current */ -#define ISL923X_C2_2LVL_OVERCURRENT (1 << 12) +#define ISL923X_C2_2LVL_OVERCURRENT BIT(12) /* Control2: adapter insertion debounce time in ms */ #define ISL923X_C2_ADAPTER_DEBOUNCE_1300 (0 << 11) -#define ISL923X_C2_ADAPTER_DEBOUNCE_150 (1 << 11) -#define ISL923X_C2_ADAPTER_DEBOUNCE_MASK (1 << 11) +#define ISL923X_C2_ADAPTER_DEBOUNCE_150 BIT(11) +#define ISL923X_C2_ADAPTER_DEBOUNCE_MASK BIT(11) /* Control2: PROCHOT debounce time in uS */ #define ISL9238_C2_PROCHOT_DEBOUNCE_7 (0 << 9) #define ISL9237_C2_PROCHOT_DEBOUNCE_10 (0 << 9) -#define ISL923X_C2_PROCHOT_DEBOUNCE_100 (1 << 9) +#define ISL923X_C2_PROCHOT_DEBOUNCE_100 BIT(9) #define ISL923X_C2_PROCHOT_DEBOUNCE_500 (2 << 9) #define ISL923X_C2_PROCHOT_DEBOUNCE_1000 (3 << 9) #define ISL923X_C2_PROCHOT_DEBOUNCE_MASK (3 << 9) /* Control2: min PROCHOT duration in uS */ #define ISL923X_C2_PROCHOT_DURATION_10000 (0 << 6) -#define ISL923X_C2_PROCHOT_DURATION_20000 (1 << 6) +#define ISL923X_C2_PROCHOT_DURATION_20000 BIT(6) #define ISL923X_C2_PROCHOT_DURATION_15000 (2 << 6) #define ISL923X_C2_PROCHOT_DURATION_5000 (3 << 6) #define ISL923X_C2_PROCHOT_DURATION_1000 (4 << 6) @@ -183,35 +183,35 @@ #define ISL923X_C2_PROCHOT_DURATION_MASK (7 << 6) /* Control2: turn off ASGATE in OTG mode */ -#define ISL923X_C2_ASGATE_OFF (1 << 5) +#define ISL923X_C2_ASGATE_OFF BIT(5) /* Control2: CMIN, general purpose comparator reference in mV */ #define ISL923X_C2_CMIN_2000 (0 << 4) -#define ISL923X_C2_CMIN_1200 (1 << 4) +#define ISL923X_C2_CMIN_1200 BIT(4) /* Control2: general purpose comparator enable */ -#define ISL923X_C2_COMPARATOR (1 << 3) +#define ISL923X_C2_COMPARATOR BIT(3) /* Control2: invert CMOUT, general purpose comparator output, polarity */ -#define ISL923X_C2_INVERT_CMOUT (1 << 2) +#define ISL923X_C2_INVERT_CMOUT BIT(2) /* Control2: disable WOC, way over current */ -#define ISL923X_C2_WOC_OFF (1 << 1) +#define ISL923X_C2_WOC_OFF BIT(1) /* Control2: PSYS gain in uA/W (ISL9237 only) */ -#define ISL9237_C2_PSYS_GAIN (1 << 0) +#define ISL9237_C2_PSYS_GAIN BIT(0) /* * Control3: Buck-Boost switching period * 0: x1 frequency, 1: half frequency. */ -#define ISL9238_C3_BB_SWITCHING_PERIOD (1 << 1) +#define ISL9238_C3_BB_SWITCHING_PERIOD BIT(1) /* * Control3: AMON/BMON direction. * 0: adapter/charging, 1:OTG/discharging (ISL9238 only) */ -#define ISL9238_C3_AMON_BMON_DIRECTION (1 << 3) +#define ISL9238_C3_AMON_BMON_DIRECTION BIT(3) /* * Control3: Disables Autonomous Charing @@ -219,16 +219,16 @@ * Note: This is disabled automatically when ever we set the current limit * manually (which we always do). */ -#define ISL9238_C3_DISABLE_AUTO_CHARING (1 << 7) +#define ISL9238_C3_DISABLE_AUTO_CHARING BIT(7) /* Control3: PSYS gain in uA/W (ISL9238 only) */ -#define ISL9238_C3_PSYS_GAIN (1 << 9) +#define ISL9238_C3_PSYS_GAIN BIT(9) /* Control3: Don't reload ACLIM on ACIN. */ -#define ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN (1 << 14) +#define ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN BIT(14) /* Control3: Don't reread PROG pin. */ -#define ISL9238_C3_NO_REREAD_PROG_PIN (1 << 15) +#define ISL9238_C3_NO_REREAD_PROG_PIN BIT(15) /* OTG voltage limit in mV, current limit in mA */ #define ISL9237_OTG_VOLTAGE_MIN 4864 @@ -247,7 +247,7 @@ /* Info register fields */ #define ISL9237_INFO_PROG_RESISTOR_MASK 0xf -#define ISL923X_INFO_TRICKLE_ACTIVE_MASK (1 << 4) +#define ISL923X_INFO_TRICKLE_ACTIVE_MASK BIT(4) #define ISL9237_INFO_PSTATE_SHIFT 5 #define ISL9237_INFO_PSTATE_MASK 3 @@ -272,9 +272,9 @@ enum isl9237_fsm_state { FSM_OTG }; -#define ISL923X_INFO_VSYSLO (1 << 10) -#define ISL923X_INFO_DCHOT (1 << 11) -#define ISL9237_INFO_ACHOT (1 << 12) +#define ISL923X_INFO_VSYSLO BIT(10) +#define ISL923X_INFO_DCHOT BIT(11) +#define ISL9237_INFO_ACHOT BIT(12) #if defined(CONFIG_CHARGER_ISL9237) #define CHARGER_NAME "isl9237" diff --git a/driver/charger/sy21612.h b/driver/charger/sy21612.h index 9d531a1ee2..d685406fcf 100644 --- a/driver/charger/sy21612.h +++ b/driver/charger/sy21612.h @@ -41,25 +41,25 @@ enum sy21612_vbus_adj { }; #define SY21612_CTRL1 0x00 -#define SY21612_CTRL1_REG_EN (1 << 7) +#define SY21612_CTRL1_REG_EN BIT(7) #define SY21612_CTRL1_LOW_BAT_MASK (7 << 4) #define SY21612_CTRL1_LOW_BAT_10_2V (0 << 4) -#define SY21612_CTRL1_LOW_BAT_10_7V (1 << 4) +#define SY21612_CTRL1_LOW_BAT_10_7V BIT(4) #define SY21612_CTRL1_LOW_BAT_11_2V (2 << 4) #define SY21612_CTRL1_LOW_BAT_11_7V (3 << 4) #define SY21612_CTRL1_LOW_BAT_22_0V (4 << 4) #define SY21612_CTRL1_LOW_BAT_22_5V (5 << 4) #define SY21612_CTRL1_LOW_BAT_23_0V (6 << 4) #define SY21612_CTRL1_LOW_BAT_23_5V (7 << 4) -#define SY21612_CTRL1_ADC_EN (1 << 3) -#define SY21612_CTRL1_ADC_AUTO_MODE (1 << 2) -#define SY21612_CTRL1_VBUS_NDISCHG (1 << 1) +#define SY21612_CTRL1_ADC_EN BIT(3) +#define SY21612_CTRL1_ADC_AUTO_MODE BIT(2) +#define SY21612_CTRL1_VBUS_NDISCHG BIT(1) #define SY21612_CTRL2 0x01 #define SY21612_CTRL2_FREQ_MASK (3 << 6) #define SY21612_CTRL2_FREQ_SHIFT 6 #define SY21612_CTRL2_FREQ_250K (0 << 6) -#define SY21612_CTRL2_FREQ_500K (1 << 6) +#define SY21612_CTRL2_FREQ_500K BIT(6) #define SY21612_CTRL2_FREQ_750K (2 << 6) #define SY21612_CTRL2_FREQ_1M (3 << 6) #define SY21612_CTRL2_VBUS_MASK (7 << 3) @@ -83,7 +83,7 @@ enum sy21612_vbus_adj { #define SY21612_PROT1 0x02 #define SY21612_PROT1_I_THRESH_MASK (7 << 5) #define SY21612_PROT1_I_THRESH_18MV (0 << 5) -#define SY21612_PROT1_I_THRESH_22MV (1 << 5) +#define SY21612_PROT1_I_THRESH_22MV BIT(5) #define SY21612_PROT1_I_THRESH_27MV (2 << 5) #define SY21612_PROT1_I_THRESH_31MV (3 << 5) #define SY21612_PROT1_I_THRESH_36MV (4 << 5) @@ -92,12 +92,12 @@ enum sy21612_vbus_adj { #define SY21612_PROT1_I_THRESH_64MV (7 << 5) #define SY21612_PROT1_OVP_THRESH_MASK (3 << 3) #define SY21612_PROT1_OVP_THRESH_110 (0 << 3) -#define SY21612_PROT1_OVP_THRESH_115 (1 << 3) +#define SY21612_PROT1_OVP_THRESH_115 BIT(3) #define SY21612_PROT1_OVP_THRESH_120 (2 << 3) #define SY21612_PROT1_OVP_THRESH_125 (3 << 3) #define SY21612_PROT1_UVP_THRESH_MASK (3 << 1) #define SY21612_PROT1_UVP_THRESH_50 (0 << 1) -#define SY21612_PROT1_UVP_THRESH_60 (1 << 1) +#define SY21612_PROT1_UVP_THRESH_60 BIT(1) #define SY21612_PROT1_UVP_THRESH_70 (2 << 1) #define SY21612_PROT1_UVP_THRESH_80 (3 << 1) @@ -106,22 +106,22 @@ enum sy21612_vbus_adj { #define SY21612_PROT2_I_LIMIT_6A (0 << 6) #define SY21612_PROT2_I_LIMIT_8A (2 << 6) #define SY21612_PROT2_I_LIMIT_10A (3 << 6) -#define SY21612_PROT2_OCP_AUTORECOVER (1 << 5) -#define SY21612_PROT2_UVP_AUTORECOVER (1 << 4) -#define SY21612_PROT2_OTP_AUTORECOVER (1 << 3) -#define SY21612_PROT2_SINK_MODE (1 << 2) +#define SY21612_PROT2_OCP_AUTORECOVER BIT(5) +#define SY21612_PROT2_UVP_AUTORECOVER BIT(4) +#define SY21612_PROT2_OTP_AUTORECOVER BIT(3) +#define SY21612_PROT2_SINK_MODE BIT(2) #define SY21612_STATE 0x04 -#define SY21612_STATE_POWER_GOOD (1 << 7) -#define SY21612_STATE_VBAT_LT_VBUS (1 << 6) -#define SY21612_STATE_VBAT_LOW (1 << 5) +#define SY21612_STATE_POWER_GOOD BIT(7) +#define SY21612_STATE_VBAT_LT_VBUS BIT(6) +#define SY21612_STATE_VBAT_LOW BIT(5) #define SY21612_INT 0x05 -#define SY21612_INT_ADC_READY (1 << 7) -#define SY21612_INT_VBUS_OCP (1 << 6) -#define SY21612_INT_INDUCTOR_OCP (1 << 5) -#define SY21612_INT_UVP (1 << 4) -#define SY21612_INT_OTP (1 << 3) +#define SY21612_INT_ADC_READY BIT(7) +#define SY21612_INT_VBUS_OCP BIT(6) +#define SY21612_INT_INDUCTOR_OCP BIT(5) +#define SY21612_INT_UVP BIT(4) +#define SY21612_INT_OTP BIT(3) /* Battery voltage range: 0 ~ 25V */ #define SY21612_VBAT_VOLT 0x06 diff --git a/driver/gyro_l3gd20h.c b/driver/gyro_l3gd20h.c index 2afe948f27..d7d3663ab2 100644 --- a/driver/gyro_l3gd20h.c +++ b/driver/gyro_l3gd20h.c @@ -75,7 +75,7 @@ static inline int get_ctrl_reg(enum motionsensor_type type) static inline int get_xyz_reg(enum motionsensor_type type) { - return L3GD20_OUT_X_L | (1 << 7); + return L3GD20_OUT_X_L | BIT(7); } /** @@ -240,8 +240,8 @@ static int set_data_rate(const struct motion_sensor_t *s, if (ret != EC_SUCCESS) goto gyro_cleanup; - val |= (1 << 4); /* high-pass filter enabled */ - val |= (1 << 0); /* data in data reg are high-pass filtered */ + val |= BIT(4); /* high-pass filter enabled */ + val |= BIT(0); /* data in data reg are high-pass filtered */ ret = raw_write8(s->port, s->addr, L3GD20_CTRL_REG5, val); if (ret != EC_SUCCESS) goto gyro_cleanup; diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h index 24ad81a693..1864c5afac 100644 --- a/driver/gyro_l3gd20h.h +++ b/driver/gyro_l3gd20h.h @@ -51,25 +51,25 @@ #define L3GD20_LOW_ODR 0x39 #define L3GD20_DPS_SEL_245 (0 << 4) -#define L3GD20_DPS_SEL_500 (1 << 4) +#define L3GD20_DPS_SEL_500 BIT(4) #define L3GD20_DPS_SEL_2000_0 (2 << 4) #define L3GD20_DPS_SEL_2000_1 (3 << 4) #define L3GD20_ODR_PD (0 << 3) #define L3GD20_ODR_12_5HZ (0 << 6) -#define L3GD20_ODR_25HZ (1 << 6) +#define L3GD20_ODR_25HZ BIT(6) #define L3GD20_ODR_50HZ_0 (2 << 6) #define L3GD20_ODR_50HZ_1 (3 << 6) #define L3GD20_ODR_100HZ (0 << 6) -#define L3GD20_ODR_200HZ (1 << 6) +#define L3GD20_ODR_200HZ BIT(6) #define L3GD20_ODR_400HZ (2 << 6) #define L3GD20_ODR_800HZ (3 << 6) #define L3GD20_ODR_MASK (3 << 6) -#define L3GD20_STS_ZYXDA_MASK (1 << 3) +#define L3GD20_STS_ZYXDA_MASK BIT(3) #define L3GD20_RANGE_MASK (3 << 4) -#define L3GD20_LOW_ODR_MASK (1 << 0) -#define L3GD20_ODR_PD_MASK (1 << 3) +#define L3GD20_LOW_ODR_MASK BIT(0) +#define L3GD20_ODR_PD_MASK BIT(3) /* Min and Max sampling frequency in mHz */ #define L3GD20_GYRO_MIN_FREQ 12500 diff --git a/driver/ina2xx.h b/driver/ina2xx.h index b1ddbd1368..9af3ab06df 100644 --- a/driver/ina2xx.h +++ b/driver/ina2xx.h @@ -19,10 +19,10 @@ #define INA2XX_CONFIG_MODE_MASK (7 << 0) #define INA2XX_CONFIG_MODE_PWRDWN (0 << 0) -#define INA2XX_CONFIG_MODE_SHUNT (1 << 0) -#define INA2XX_CONFIG_MODE_BUS (1 << 1) +#define INA2XX_CONFIG_MODE_SHUNT BIT(0) +#define INA2XX_CONFIG_MODE_BUS BIT(1) #define INA2XX_CONFIG_MODE_TRG (0 << 2) -#define INA2XX_CONFIG_MODE_CONT (1 << 2) +#define INA2XX_CONFIG_MODE_CONT BIT(2) /* Conversion time for bus and shunt in micro-seconds */ enum ina2xx_conv_time { @@ -40,7 +40,7 @@ enum ina2xx_conv_time { #define INA2XX_CONFIG_BUS_CONV_TIME(t) ((t) << 6) #define INA2XX_CONFIG_AVG_1 (0 << 9) -#define INA2XX_CONFIG_AVG_4 (1 << 9) +#define INA2XX_CONFIG_AVG_4 BIT(9) #define INA2XX_CONFIG_AVG_16 (2 << 9) #define INA2XX_CONFIG_AVG_64 (3 << 9) #define INA2XX_CONFIG_AVG_128 (4 << 9) @@ -48,17 +48,17 @@ enum ina2xx_conv_time { #define INA2XX_CONFIG_AVG_512 (6 << 9) #define INA2XX_CONFIG_AVG_1024 (7 << 9) -#define INA2XX_MASK_EN_LEN (1 << 0) -#define INA2XX_MASK_EN_APOL (1 << 1) -#define INA2XX_MASK_EN_OVF (1 << 2) -#define INA2XX_MASK_EN_CVRF (1 << 3) -#define INA2XX_MASK_EN_AFF (1 << 4) -#define INA2XX_MASK_EN_CNVR (1 << 10) -#define INA2XX_MASK_EN_POL (1 << 11) -#define INA2XX_MASK_EN_BUL (1 << 12) -#define INA2XX_MASK_EN_BOL (1 << 13) -#define INA2XX_MASK_EN_SUL (1 << 14) -#define INA2XX_MASK_EN_SOL (1 << 15) +#define INA2XX_MASK_EN_LEN BIT(0) +#define INA2XX_MASK_EN_APOL BIT(1) +#define INA2XX_MASK_EN_OVF BIT(2) +#define INA2XX_MASK_EN_CVRF BIT(3) +#define INA2XX_MASK_EN_AFF BIT(4) +#define INA2XX_MASK_EN_CNVR BIT(10) +#define INA2XX_MASK_EN_POL BIT(11) +#define INA2XX_MASK_EN_BUL BIT(12) +#define INA2XX_MASK_EN_BOL BIT(13) +#define INA2XX_MASK_EN_SUL BIT(14) +#define INA2XX_MASK_EN_SOL BIT(15) #if defined(CONFIG_INA231) && defined(CONFIG_INA219) diff --git a/driver/ioexpander_it8300.h b/driver/ioexpander_it8300.h index b457d89ddc..2b47e7f3e1 100644 --- a/driver/ioexpander_it8300.h +++ b/driver/ioexpander_it8300.h @@ -68,10 +68,10 @@ #define IT8300_GPCR_E5 0x37 #define IT8300_GPCR_E6 0x38 -#define IT8300_GPCR_GPI_MODE (1 << 7) -#define IT8300_GPCR_GP0_MODE (1 << 6) -#define IT8300_GPCR_PULL_UP_EN (1 << 2) -#define IT8300_GPCR_PULL_DN_EN (1 << 1) +#define IT8300_GPCR_GPI_MODE BIT(7) +#define IT8300_GPCR_GP0_MODE BIT(6) +#define IT8300_GPCR_PULL_UP_EN BIT(2) +#define IT8300_GPCR_PULL_DN_EN BIT(1) /* EXGPIO Clear Alert */ #define IT8300_ECA 0x30 @@ -94,13 +94,13 @@ #define IT8300_OODER_E 0x3D /* IT83200 Port GPIOs */ -#define IT8300_GPX_0 (1 << 0) -#define IT8300_GPX_1 (1 << 1) -#define IT8300_GPX_2 (1 << 2) -#define IT8300_GPX_3 (1 << 3) -#define IT8300_GPX_4 (1 << 4) -#define IT8300_GPX_5 (1 << 5) -#define IT8300_GPX_6 (1 << 6) -#define IT8300_GPX_7 (1 << 7) +#define IT8300_GPX_0 BIT(0) +#define IT8300_GPX_1 BIT(1) +#define IT8300_GPX_2 BIT(2) +#define IT8300_GPX_3 BIT(3) +#define IT8300_GPX_4 BIT(4) +#define IT8300_GPX_5 BIT(5) +#define IT8300_GPX_6 BIT(6) +#define IT8300_GPX_7 BIT(7) #endif /* __CROS_EC_IOEXPANDER_IT8300_H */ diff --git a/driver/ioexpander_pca9555.h b/driver/ioexpander_pca9555.h index 3a932ceef0..874f24356a 100644 --- a/driver/ioexpander_pca9555.h +++ b/driver/ioexpander_pca9555.h @@ -19,14 +19,14 @@ #define PCA9555_CMD_CONFIGURATION_PORT_0 6 #define PCA9555_CMD_CONFIGURATION_PORT_1 7 -#define PCA9555_IO_0 (1 << 0) -#define PCA9555_IO_1 (1 << 1) -#define PCA9555_IO_2 (1 << 2) -#define PCA9555_IO_3 (1 << 3) -#define PCA9555_IO_4 (1 << 4) -#define PCA9555_IO_5 (1 << 5) -#define PCA9555_IO_6 (1 << 6) -#define PCA9555_IO_7 (1 << 7) +#define PCA9555_IO_0 BIT(0) +#define PCA9555_IO_1 BIT(1) +#define PCA9555_IO_2 BIT(2) +#define PCA9555_IO_3 BIT(3) +#define PCA9555_IO_4 BIT(4) +#define PCA9555_IO_5 BIT(5) +#define PCA9555_IO_6 BIT(6) +#define PCA9555_IO_7 BIT(7) static inline int pca9555_read(int port, int addr, int reg, int *data_ptr) { diff --git a/driver/led/lm3630a.h b/driver/led/lm3630a.h index 38fc52e111..d43304b66e 100644 --- a/driver/led/lm3630a.h +++ b/driver/led/lm3630a.h @@ -27,37 +27,37 @@ #define LM3630A_REG_FILTER_STRENGTH 0x50 /* Control register bits */ -#define LM3630A_CTRL_BIT_SLEEP_CMD (1 << 7) -#define LM3630A_CTRL_BIT_SLEEP_STAT (1 << 6) -#define LM3630A_CTRL_BIT_LINEAR_A (1 << 4) -#define LM3630A_CTRL_BIT_LINEAR_B (1 << 3) -#define LM3630A_CTRL_BIT_LED_EN_A (1 << 2) -#define LM3630A_CTRL_BIT_LED_EN_B (1 << 1) -#define LM3630A_CTRL_BIT_LED2_ON_A (1 << 0) +#define LM3630A_CTRL_BIT_SLEEP_CMD BIT(7) +#define LM3630A_CTRL_BIT_SLEEP_STAT BIT(6) +#define LM3630A_CTRL_BIT_LINEAR_A BIT(4) +#define LM3630A_CTRL_BIT_LINEAR_B BIT(3) +#define LM3630A_CTRL_BIT_LED_EN_A BIT(2) +#define LM3630A_CTRL_BIT_LED_EN_B BIT(1) +#define LM3630A_CTRL_BIT_LED2_ON_A BIT(0) /* Config register bits */ -#define LM3630A_CFG_BIT_FB_EN_B (1 << 4) -#define LM3630A_CFG_BIT_FB_EN_A (1 << 3) -#define LM3630A_CFG_BIT_PWM_LOW (1 << 2) -#define LM3630A_CFG_BIT_PWM_EN_B (1 << 1) -#define LM3630A_CFG_BIT_PWM_EN_A (1 << 0) +#define LM3630A_CFG_BIT_FB_EN_B BIT(4) +#define LM3630A_CFG_BIT_FB_EN_A BIT(3) +#define LM3630A_CFG_BIT_PWM_LOW BIT(2) +#define LM3630A_CFG_BIT_PWM_EN_B BIT(1) +#define LM3630A_CFG_BIT_PWM_EN_A BIT(0) /* Boost control register bits */ #define LM3630A_BOOST_OVP_16V (0 << 5) -#define LM3630A_BOOST_OVP_24V (1 << 5) +#define LM3630A_BOOST_OVP_24V BIT(5) #define LM3630A_BOOST_OVP_32V (2 << 5) #define LM3630A_BOOST_OVP_40V (3 << 5) #define LM3630A_BOOST_OCP_600MA (0 << 3) -#define LM3630A_BOOST_OCP_800MA (1 << 3) +#define LM3630A_BOOST_OCP_800MA BIT(3) #define LM3630A_BOOST_OCP_1000MA (2 << 3) #define LM3630A_BOOST_OCP_1200MA (3 << 3) -#define LM3630A_BOOST_SLOW_START (1 << 2) +#define LM3630A_BOOST_SLOW_START BIT(2) #define LM3630A_SHIFT_500KHZ (0 << 1) /* FMODE=0 */ -#define LM3630A_SHIFT_560KHZ (1 << 1) /* FMODE=0 */ +#define LM3630A_SHIFT_560KHZ BIT(1) /* FMODE=0 */ #define LM3630A_SHIFT_1000KHZ (0 << 1) /* FMODE=1 */ -#define LM3630A_SHIFT_1120KHZ (1 << 1) /* FMODE=1 */ +#define LM3630A_SHIFT_1120KHZ BIT(1) /* FMODE=1 */ #define LM3630A_FMODE_500KHZ (0 << 0) -#define LM3630A_FMODE_1000KHZ (1 << 0) +#define LM3630A_FMODE_1000KHZ BIT(0) /* Power on and initialize LM3630A. */ int lm3630a_poweron(void); diff --git a/driver/mag_bmm150.c b/driver/mag_bmm150.c index cb53641c00..9598d85105 100644 --- a/driver/mag_bmm150.c +++ b/driver/mag_bmm150.c @@ -149,7 +149,7 @@ void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, if (r == 0) inter = 0; else - inter = ((int)regs->dig_xyz1 << 14) / r - (1 << 14); + inter = ((int)regs->dig_xyz1 << 14) / r - BIT(14); for (axis = X; axis <= Y; axis++) { if (raw[axis] == BMM150_FLIP_OVERFLOW_ADCVAL) { @@ -195,16 +195,16 @@ void bmm150_temp_compensate_z(const struct motion_sensor_t *s, * ((z - dig_z4) * 131072 - dig_z3 * (r - dig_xyz1)) / * ((dig_z2 + dig_z1 * r / 32768) * 4); * - * We spread 4 so we multiply by 131072 / 4 == (1<<15) only. + * We spread 4 so we multiply by 131072 / 4 == BIT(15) only. */ dividend = (raw[Z] - (int)regs->dig_z4) << 15; dividend -= (regs->dig_z3 * (r - (int)regs->dig_xyz1)) >> 2; - /* add 1 << 15 to round to next integer. */ - divisor = (int)regs->dig_z1 * (r << 1) + (1 << 15); + /* add BIT(15) to round to next integer. */ + divisor = (int)regs->dig_z1 * (r << 1) + BIT(15); divisor >>= 16; divisor += (int)regs->dig_z2; comp[Z] = dividend / divisor; - if (comp[Z] > (1 << 15) || comp[Z] < -(1 << 15)) + if (comp[Z] > BIT(15) || comp[Z] < -(BIT(15))) comp[Z] = BMM150_OVERFLOW_OUTPUT; } diff --git a/driver/mag_bmm150.h b/driver/mag_bmm150.h index c15cbc065b..94777e1b61 100644 --- a/driver/mag_bmm150.h +++ b/driver/mag_bmm150.h @@ -23,8 +23,8 @@ #define BMM150_INT_STATUS 0x4a #define BMM150_PWR_CTRL 0x4b -#define BMM150_SRST ((1 << 7) | (1 << 1)) -#define BMM150_PWR_ON (1 << 0) +#define BMM150_SRST (BIT(7) | BIT(1)) +#define BMM150_PWR_ON BIT(0) #define BMM150_OP_CTRL 0x4c #define BMM150_OP_MODE_OFFSET 1 diff --git a/driver/pi3usb30532.h b/driver/pi3usb30532.h index 15a9241239..7f120a9f85 100644 --- a/driver/pi3usb30532.h +++ b/driver/pi3usb30532.h @@ -21,9 +21,9 @@ #define PI3USB30532_VENDOR_ID 0 /* PI3USB30532 control flags */ -#define PI3USB30532_BIT_SWAP (1 << 0) -#define PI3USB30532_BIT_DP (1 << 1) -#define PI3USB30532_BIT_USB (1 << 2) +#define PI3USB30532_BIT_SWAP BIT(0) +#define PI3USB30532_BIT_DP BIT(1) +#define PI3USB30532_BIT_USB BIT(2) /* PI3USB30532 modes */ /* Power down, switch open */ diff --git a/driver/pi3usb9281.h b/driver/pi3usb9281.h index 8ed4c77c57..980c565e21 100644 --- a/driver/pi3usb9281.h +++ b/driver/pi3usb9281.h @@ -21,40 +21,40 @@ #define PI3USB9281_DEV_ID 0x10 #define PI3USB9281_DEV_ID_A 0x18 -#define PI3USB9281_CTRL_INT_DIS (1 << 0) -#define PI3USB9281_CTRL_AUTO (1 << 2) -#define PI3USB9281_CTRL_SWITCH_AUTO (1 << 4) +#define PI3USB9281_CTRL_INT_DIS BIT(0) +#define PI3USB9281_CTRL_AUTO BIT(2) +#define PI3USB9281_CTRL_SWITCH_AUTO BIT(4) /* Bits 5 thru 7 are read X, write 0 */ #define PI3USB9281_CTRL_MASK 0x1f /* Bits 1 and 3 are read 1, write 1 */ #define PI3USB9281_CTRL_RSVD_1 0x0a #define PI3USB9281_PIN_MANUAL_VBUS (3 << 0) -#define PI3USB9281_PIN_MANUAL_DP (1 << 2) -#define PI3USB9281_PIN_MANUAL_DM (1 << 5) +#define PI3USB9281_PIN_MANUAL_DP BIT(2) +#define PI3USB9281_PIN_MANUAL_DM BIT(5) -#define PI3USB9281_INT_ATTACH (1 << 0) -#define PI3USB9281_INT_DETACH (1 << 1) -#define PI3USB9281_INT_OVP (1 << 5) -#define PI3USB9281_INT_OCP (1 << 6) -#define PI3USB9281_INT_OVP_OC (1 << 7) +#define PI3USB9281_INT_ATTACH BIT(0) +#define PI3USB9281_INT_DETACH BIT(1) +#define PI3USB9281_INT_OVP BIT(5) +#define PI3USB9281_INT_OCP BIT(6) +#define PI3USB9281_INT_OVP_OC BIT(7) #define PI3USB9281_INT_ATTACH_DETACH (PI3USB9281_INT_ATTACH | \ PI3USB9281_INT_DETACH) #define PI3USB9281_TYPE_NONE 0 -#define PI3USB9281_TYPE_MHL (1 << 0) -#define PI3USB9281_TYPE_OTG (1 << 1) -#define PI3USB9281_TYPE_SDP (1 << 2) -#define PI3USB9281_TYPE_CAR (1 << 4) -#define PI3USB9281_TYPE_CDP (1 << 5) -#define PI3USB9281_TYPE_DCP (1 << 6) +#define PI3USB9281_TYPE_MHL BIT(0) +#define PI3USB9281_TYPE_OTG BIT(1) +#define PI3USB9281_TYPE_SDP BIT(2) +#define PI3USB9281_TYPE_CAR BIT(4) +#define PI3USB9281_TYPE_CDP BIT(5) +#define PI3USB9281_TYPE_DCP BIT(6) #define PI3USB9281_CHG_NONE 0 -#define PI3USB9281_CHG_CAR_TYPE1 (1 << 1) +#define PI3USB9281_CHG_CAR_TYPE1 BIT(1) #define PI3USB9281_CHG_CAR_TYPE2 (3 << 0) -#define PI3USB9281_CHG_APPLE_1A (1 << 2) -#define PI3USB9281_CHG_APPLE_2A (1 << 3) -#define PI3USB9281_CHG_APPLE_2_4A (1 << 4) +#define PI3USB9281_CHG_APPLE_1A BIT(2) +#define PI3USB9281_CHG_APPLE_2A BIT(3) +#define PI3USB9281_CHG_APPLE_2_4A BIT(4) /* Check if charge status has any connection */ #define PI3USB9281_CHG_STATUS_ANY(x) (((x) & 0x1f) > 1) diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h index a59160bf29..e00ea1d252 100644 --- a/driver/pmic_bd99992gw.h +++ b/driver/pmic_bd99992gw.h @@ -26,6 +26,6 @@ #define BD99992GW_REG_DISCHGCNT3 0x3e #define BD99992GW_REG_DISCHGCNT4 0x3f #define BD99992GW_REG_SDWNCTRL 0x49 -#define BD99992GW_SDWNCTRL_SWDN (1 << 0) /* SWDN mask */ +#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */ #endif /* __CROS_EC_PMIC_BD99992GW_H */ diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index 35202c8fe8..3423b77f53 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -27,7 +27,7 @@ static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */ #define NX20P348X_DB_EXIT_FAIL_THRESHOLD 10 static int db_exit_fail_count[CONFIG_USB_PD_PORT_COUNT]; -#define NX20P348X_FLAGS_SOURCE_ENABLED (1 << 0) +#define NX20P348X_FLAGS_SOURCE_ENABLED BIT(0) static uint8_t flags[CONFIG_USB_PD_PORT_COUNT]; static int read_reg(uint8_t port, int reg, int *regval) diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index 68048be6ea..531842d766 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -40,10 +40,10 @@ #define NX20P348X_DEVICE_CONTROL_REG 0x0B /* Device Control Register */ -#define NX20P348X_CTRL_FRS_AT (1 << 3) -#define NX20P348X_CTRL_DB_EXIT (1 << 2) -#define NX20P348X_CTRL_VBUSDIS_EN (1 << 1) -#define NX20P348X_CTRL_LDO_SD (1 << 0) +#define NX20P348X_CTRL_FRS_AT BIT(3) +#define NX20P348X_CTRL_DB_EXIT BIT(2) +#define NX20P348X_CTRL_VBUSDIS_EN BIT(1) +#define NX20P348X_CTRL_LDO_SD BIT(0) /* Device Status Modes */ #define NX20P348X_DEVICE_MODE_MASK 0x7 @@ -59,14 +59,14 @@ #define NX20P3483_MODE_STANDBY 4 /* Switch Control Register */ -#define NX20P348X_SWITCH_CONTROL_HVSNK (1 << 0) -#define NX20P348X_SWITCH_CONTROL_HVSRC (1 << 1) -#define NX20P348X_SWITCH_CONTROL_5VSRC (1 << 2) +#define NX20P348X_SWITCH_CONTROL_HVSNK BIT(0) +#define NX20P348X_SWITCH_CONTROL_HVSRC BIT(1) +#define NX20P348X_SWITCH_CONTROL_5VSRC BIT(2) /* Switch Status Register */ -#define NX20P348X_HVSNK_STS (1 << 0) -#define NX20P348X_HVSRC_STS (1 << 1) -#define NX20P348X_5VSRC_STS (1 << 2) +#define NX20P348X_HVSNK_STS BIT(0) +#define NX20P348X_HVSRC_STS BIT(1) +#define NX20P348X_5VSRC_STS BIT(2) #define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25 #define NX20P348X_SWITCH_STATUS_MASK 0x7 @@ -100,23 +100,23 @@ #define NX20P348X_OVLO_23_0 6 /* Interrupt 1 Register Bits */ -#define NX20P348X_INT1_DBEXIT_ERR (1 << 7) -#define NX20P348X_INT1_FRS_DET (1 << 6) -#define NX20P348X_INT1_OV_5VSRC (1 << 4) -#define NX20P348X_INT1_RCP_5VSRC (1 << 3) -#define NX20P348X_INT1_SC_5VSRC (1 << 2) -#define NX20P348X_INT1_OC_5VSRC (1 << 1) -#define NX20P348X_INT1_OTP (1 << 0) +#define NX20P348X_INT1_DBEXIT_ERR BIT(7) +#define NX20P348X_INT1_FRS_DET BIT(6) +#define NX20P348X_INT1_OV_5VSRC BIT(4) +#define NX20P348X_INT1_RCP_5VSRC BIT(3) +#define NX20P348X_INT1_SC_5VSRC BIT(2) +#define NX20P348X_INT1_OC_5VSRC BIT(1) +#define NX20P348X_INT1_OTP BIT(0) /* Interrupt 2 Register Bits */ -#define NX20P348X_INT2_EN_ERR (1 << 7) -#define NX20P348X_INT2_RCP_HVSNK (1 << 6) -#define NX20P348X_INT2_SC_HVSNK (1 << 5) -#define NX20P348X_INT2_OV_HVSNK (1 << 4) -#define NX20P348X_INT2_RCP_HVSRC (1 << 3) -#define NX20P348X_INT2_SC_HVSRC (1 << 2) -#define NX20P348X_INT2_OC_HVSRC (1 << 1) -#define NX20P348X_INT2_OV_HVSRC (1 << 0) +#define NX20P348X_INT2_EN_ERR BIT(7) +#define NX20P348X_INT2_RCP_HVSNK BIT(6) +#define NX20P348X_INT2_SC_HVSNK BIT(5) +#define NX20P348X_INT2_OV_HVSNK BIT(4) +#define NX20P348X_INT2_RCP_HVSRC BIT(3) +#define NX20P348X_INT2_SC_HVSRC BIT(2) +#define NX20P348X_INT2_OC_HVSRC BIT(1) +#define NX20P348X_INT2_OV_HVSRC BIT(0) struct ppc_drv; extern const struct ppc_drv nx20p348x_drv; diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h index c5b16ea73b..6c79aa46ed 100644 --- a/driver/ppc/sn5s330.h +++ b/driver/ppc/sn5s330.h @@ -86,44 +86,44 @@ enum sn5s330_pp_idx { #define SN5S330_ILIM_3_30 12 /* FUNC_SET_2 */ -#define SN5S330_SBU_EN (1 << 4) +#define SN5S330_SBU_EN BIT(4) /* FUNC_SET_3 */ -#define SN5S330_PP1_EN (1 << 0) -#define SN5S330_PP2_EN (1 << 1) -#define SN5S330_VBUS_DISCH_EN (1 << 2) -#define SN5S330_SET_RCP_MODE_PP1 (1 << 5) -#define SN5S330_SET_RCP_MODE_PP2 (1 << 6) +#define SN5S330_PP1_EN BIT(0) +#define SN5S330_PP2_EN BIT(1) +#define SN5S330_VBUS_DISCH_EN BIT(2) +#define SN5S330_SET_RCP_MODE_PP1 BIT(5) +#define SN5S330_SET_RCP_MODE_PP2 BIT(6) /* FUNC_SET_4 */ -#define SN5S330_VCONN_EN (1 << 0) -#define SN5S330_CC_POLARITY (1 << 1) -#define SN5S330_CC_EN (1 << 4) -#define SN5S330_VCONN_ILIM_SEL (1 << 5) +#define SN5S330_VCONN_EN BIT(0) +#define SN5S330_CC_POLARITY BIT(1) +#define SN5S330_CC_EN BIT(4) +#define SN5S330_VCONN_ILIM_SEL BIT(5) /* FUNC_SET_8 */ #define SN5S330_VCONN_DEGLITCH_MASK (3 << 6) #define SN5S330_VCONN_DEGLITCH_63_US (0 << 6) -#define SN5S330_VCONN_DEGLITCH_125_US (1 << 6) +#define SN5S330_VCONN_DEGLITCH_125_US BIT(6) #define SN5S330_VCONN_DEGLITCH_640_US (2 << 6) #define SN5S330_VCONN_DEGLITCH_1280_US (3 << 6) /* FUNC_SET_9 */ -#define SN5S330_FORCE_OVP_EN_SBU (1 << 1) -#define SN5S330_PP2_CONFIG (1 << 2) -#define SN5S330_OVP_EN_CC (1 << 4) -#define SN5S330_CONFIG_UVP (1 << 5) -#define SN5S330_FORCE_ON_VBUS_OVP (1 << 6) -#define SN5S330_FORCE_ON_VBUS_UVP (1 << 7) +#define SN5S330_FORCE_OVP_EN_SBU BIT(1) +#define SN5S330_PP2_CONFIG BIT(2) +#define SN5S330_OVP_EN_CC BIT(4) +#define SN5S330_CONFIG_UVP BIT(5) +#define SN5S330_FORCE_ON_VBUS_OVP BIT(6) +#define SN5S330_FORCE_ON_VBUS_UVP BIT(7) /* INT_STATUS_REG3 */ -#define SN5S330_VBUS_GOOD (1 << 0) +#define SN5S330_VBUS_GOOD BIT(0) /* INT_STATUS_REG4 */ -#define SN5S330_DIG_RES (1 << 0) -#define SN5S330_DB_BOOT (1 << 1) -#define SN5S330_VSAFE0V_STAT (1 << 2) -#define SN5S330_VSAFE0V_MASK (1 << 3) +#define SN5S330_DIG_RES BIT(0) +#define SN5S330_DB_BOOT BIT(1) +#define SN5S330_VSAFE0V_STAT BIT(2) +#define SN5S330_VSAFE0V_MASK BIT(3) /* * INT_MASK_RISE/FALL_EDGE_1 @@ -133,7 +133,7 @@ enum sn5s330_pp_idx { * occured; similarly for falling edge, it means the overcurrent condition is no * longer present. */ -#define SN5S330_ILIM_PP1_MASK (1 << 4) +#define SN5S330_ILIM_PP1_MASK BIT(4) /* * INT_MASK_RISE/FALL_EDGE2 @@ -150,7 +150,7 @@ enum sn5s330_pp_idx { * For rising edge registers, this indicates VBUS has risen above 4.0V. * For falling edge registers, this indicates VBUS has fallen below 4.0V. */ -#define SN5S330_VBUS_GOOD_MASK (1 << 0) +#define SN5S330_VBUS_GOOD_MASK BIT(0) extern const struct ppc_drv sn5s330_drv; diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c index d7c050cbce..24a8b9a3ee 100644 --- a/driver/ppc/syv682x.c +++ b/driver/ppc/syv682x.c @@ -13,10 +13,10 @@ #include "usbc_ppc.h" #include "util.h" -#define SYV682X_FLAGS_SOURCE_ENABLED (1 << 0) +#define SYV682X_FLAGS_SOURCE_ENABLED BIT(0) /* 0 -> CC1, 1 -> CC2 */ -#define SYV682X_FLAGS_CC_POLARITY (1 << 1) -#define SYV682X_FLAGS_VBUS_PRESENT (1 << 2) +#define SYV682X_FLAGS_CC_POLARITY BIT(1) +#define SYV682X_FLAGS_VBUS_PRESENT BIT(2) static uint8_t flags[CONFIG_USB_PD_PORT_COUNT]; #define SYV682X_VBUS_DET_THRESH_MV 4000 diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h index 5188a75b79..98bb67d522 100644 --- a/driver/ppc/syv682x.h +++ b/driver/ppc/syv682x.h @@ -22,13 +22,13 @@ #define SYV682X_CONTROL_4_REG 0x04 /* Status Register */ -#define SYV682X_STATUS_VSAFE_5V (1 << 1) -#define SYV682X_STATUS_VSAFE_0V (1 << 0) +#define SYV682X_STATUS_VSAFE_5V BIT(1) +#define SYV682X_STATUS_VSAFE_0V BIT(0) /* Control Register 1 */ -#define SYV682X_CONTROL_1_CH_SEL (1 << 1) -#define SYV682X_CONTROL_1_HV_DR (1 << 2) -#define SYV682X_CONTROL_1_PWR_ENB (1 << 7) +#define SYV682X_CONTROL_1_CH_SEL BIT(1) +#define SYV682X_CONTROL_1_HV_DR BIT(2) +#define SYV682X_CONTROL_1_PWR_ENB BIT(7) #define SYV682X_ILIM_MASK 0x18 #define SYV682X_ILIM_BIT_SHIFT 3 @@ -38,8 +38,8 @@ #define SYV682X_ILIM_3_30 3 /* Control Register 2 */ -#define SYV682X_CONTROL_2_SDSG (1 << 1) -#define SYV682X_CONTROL_2_FDSG (1 << 0) +#define SYV682X_CONTROL_2_SDSG BIT(1) +#define SYV682X_CONTROL_2_FDSG BIT(0) /* Control Register 3 */ #define SYV682X_OVP_MASK 0x70 @@ -54,13 +54,13 @@ #define SYV682X_OVP_23_7 7 /* Control Register 4 */ -#define SYV682X_CONTROL_4_CC1_BPS (1 << 7) -#define SYV682X_CONTROL_4_CC2_BPS (1 << 6) -#define SYV682X_CONTROL_4_VCONN1 (1 << 5) -#define SYV682X_CONTROL_4_VCONN2 (1 << 4) -#define SYV682X_CONTROL_4_VBAT_OVP (1 << 3) -#define SYV682X_CONTROL_4_VCONN_OCP (1 << 2) -#define SYV682X_CONTROL_4_CC_FRS (1 << 1) +#define SYV682X_CONTROL_4_CC1_BPS BIT(7) +#define SYV682X_CONTROL_4_CC2_BPS BIT(6) +#define SYV682X_CONTROL_4_VCONN1 BIT(5) +#define SYV682X_CONTROL_4_VCONN2 BIT(4) +#define SYV682X_CONTROL_4_VBAT_OVP BIT(3) +#define SYV682X_CONTROL_4_VCONN_OCP BIT(2) +#define SYV682X_CONTROL_4_CC_FRS BIT(1) struct ppc_drv; extern const struct ppc_drv syv682x_drv; diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c index 3eac7732af..5b49cd685e 100644 --- a/driver/tcpm/anx7447.c +++ b/driver/tcpm/anx7447.c @@ -18,15 +18,15 @@ #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) -#define ANX7447_VENDOR_ALERT (1 << 15) +#define ANX7447_VENDOR_ALERT BIT(15) #define ANX7447_REG_STATUS 0x82 -#define ANX7447_REG_STATUS_LINK (1 << 0) +#define ANX7447_REG_STATUS_LINK BIT(0) #define ANX7447_REG_HPD 0x83 -#define ANX7447_REG_HPD_HIGH (1 << 0) -#define ANX7447_REG_HPD_IRQ (1 << 1) -#define ANX7447_REG_HPD_ENABLE (1 << 2) +#define ANX7447_REG_HPD_HIGH BIT(0) +#define ANX7447_REG_HPD_IRQ BIT(1) +#define ANX7447_REG_HPD_ENABLE BIT(2) #define vsafe5v_min (3800/25) #define vsafe0v_max (800/25) diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h index deaebf3f1d..18708d38b4 100644 --- a/driver/tcpm/anx74xx.h +++ b/driver/tcpm/anx74xx.h @@ -30,16 +30,16 @@ #define ANX74XX_REG_INTP_VCONN_CTRL 0x33 #define ANX74XX_REG_VCONN_DISABLE 0x0f -#define ANX74XX_REG_VCONN_1_ENABLE (1 << 4) -#define ANX74XX_REG_VCONN_2_ENABLE (1 << 5) -#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN (1 << 2) +#define ANX74XX_REG_VCONN_1_ENABLE BIT(4) +#define ANX74XX_REG_VCONN_2_ENABLE BIT(5) +#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN BIT(2) #define ANX74XX_STANDBY_MODE (0) #define ANX74XX_NORMAL_MODE (1) #define ANX74XX_REG_TX_CTRL_1 0x81 -#define ANX74XX_REG_TX_HARD_RESET_REQ (1 << 1) -#define ANX74XX_REG_TX_CABLE_RESET_REQ (1 << 2) +#define ANX74XX_REG_TX_HARD_RESET_REQ BIT(1) +#define ANX74XX_REG_TX_CABLE_RESET_REQ BIT(2) #define ANX74XX_REG_TX_CTRL_2 0x82 #define ANX74XX_REG_TX_WR_FIFO 0x83 @@ -50,36 +50,36 @@ #define ANX74XX_REG_TX_START_ADDR_1 0xd0 #define ANX74XX_REG_CTRL_COMMAND 0xdb -#define ANX74XX_REG_TX_SEND_DATA_REQ (1 << 0) -#define ANX74XX_REG_TX_HARD_RST_REQ (1 << 1) +#define ANX74XX_REG_TX_SEND_DATA_REQ BIT(0) +#define ANX74XX_REG_TX_HARD_RST_REQ BIT(1) #define ANX74XX_REG_TX_BIST_CTRL 0x9D -#define ANX74XX_REG_TX_BIST_MODE (1 << 4) -#define ANX74XX_REG_TX_BIST_STOP (1 << 3) -#define ANX74XX_REG_TX_BIXT_FOREVER (1 << 2) -#define ANX74XX_REG_TX_BIST_ENABLE (1 << 1) -#define ANX74XX_REG_TX_BIST_START (1 << 0) +#define ANX74XX_REG_TX_BIST_MODE BIT(4) +#define ANX74XX_REG_TX_BIST_STOP BIT(3) +#define ANX74XX_REG_TX_BIXT_FOREVER BIT(2) +#define ANX74XX_REG_TX_BIST_ENABLE BIT(1) +#define ANX74XX_REG_TX_BIST_START BIT(0) #define ANX74XX_REG_PD_HEADER 0x69 #define ANX74XX_REG_PD_RX_DATA_OBJ 0x11 #define ANX74XX_REG_PD_RX_DATA_OBJ_M 0x4d #define ANX74XX_REG_ANALOG_STATUS 0x40 -#define ANX74XX_REG_VBUS_STATUS (1 << 4) +#define ANX74XX_REG_VBUS_STATUS BIT(4) #define ANX74XX_REG_CC_PULL_RD 0xfd #define ANX74XX_REG_CC_PULL_RP 0x02 #define ANX74XX_REG_TX_AUTO_GOODCRC_2 0x94 -#define ANX74XX_REG_REPLY_SOP_EN (1 << 3) -#define ANX74XX_REG_REPLY_SOP_1_EN (1 << 4) -#define ANX74XX_REG_REPLY_SOP_2_EN (1 << 5) +#define ANX74XX_REG_REPLY_SOP_EN BIT(3) +#define ANX74XX_REG_REPLY_SOP_1_EN BIT(4) +#define ANX74XX_REG_REPLY_SOP_2_EN BIT(5) #define ANX74XX_REG_TX_AUTO_GOODCRC_1 0x9c #define ANX74XX_REG_SPEC_REV_BIT_POS (3) #define ANX74XX_REG_DATA_ROLE_BIT_POS (2) #define ANX74XX_REG_PWR_ROLE_BIT_POS (1) -#define ANX74XX_REG_AUTO_GOODCRC_EN (1 << 0) +#define ANX74XX_REG_AUTO_GOODCRC_EN BIT(0) #define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole) \ ((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \ ((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS) | \ @@ -88,7 +88,7 @@ #define ANX74XX_REG_ANALOG_CTRL_0 0x41 -#define ANX74XX_REG_R_PIN_CABLE_DET (1 << 7) +#define ANX74XX_REG_R_PIN_CABLE_DET BIT(7) #define ANX74XX_REG_ANALOG_CTRL_1 0x42 #define ANX74XX_REG_ANALOG_CTRL_5 0x46 @@ -106,19 +106,19 @@ #define ANX74XX_REG_ANALOG_CTRL_11 0x4c #define ANX74XX_REG_ANALOG_CTRL_12 0x4d -#define ANX74XX_REG_MUX_ML0_RX2 (1 << 0) -#define ANX74XX_REG_MUX_ML0_RX1 (1 << 1) -#define ANX74XX_REG_MUX_ML3_RX2 (1 << 2) -#define ANX74XX_REG_MUX_ML3_RX1 (1 << 3) -#define ANX74XX_REG_MUX_SSRX_RX2 (1 << 4) -#define ANX74XX_REG_MUX_SSRX_RX1 (1 << 5) -#define ANX74XX_REG_MUX_ML1_TX2 (1 << 6) -#define ANX74XX_REG_MUX_ML1_TX1 (1 << 7) +#define ANX74XX_REG_MUX_ML0_RX2 BIT(0) +#define ANX74XX_REG_MUX_ML0_RX1 BIT(1) +#define ANX74XX_REG_MUX_ML3_RX2 BIT(2) +#define ANX74XX_REG_MUX_ML3_RX1 BIT(3) +#define ANX74XX_REG_MUX_SSRX_RX2 BIT(4) +#define ANX74XX_REG_MUX_SSRX_RX1 BIT(5) +#define ANX74XX_REG_MUX_ML1_TX2 BIT(6) +#define ANX74XX_REG_MUX_ML1_TX1 BIT(7) -#define ANX74XX_REG_MUX_ML2_TX2 (1 << 4) -#define ANX74XX_REG_MUX_ML2_TX1 (1 << 5) -#define ANX74XX_REG_MUX_SSTX_TX2 (1 << 6) -#define ANX74XX_REG_MUX_SSTX_TX1 (1 << 7) +#define ANX74XX_REG_MUX_ML2_TX2 BIT(4) +#define ANX74XX_REG_MUX_ML2_TX1 BIT(5) +#define ANX74XX_REG_MUX_SSTX_TX2 BIT(6) +#define ANX74XX_REG_MUX_SSTX_TX1 BIT(7) #define ANX74XX_REG_CC_SOFTWARE_CTRL 0x4a #define ANX74XX_REG_CC_SW_CTRL_ENABLE 0x01 @@ -133,29 +133,29 @@ #define ANX74XX_REG_IRQ_EXT_MASK_1 0x3b #define ANX74XX_REG_IRQ_EXT_MASK_2 0x3c #define ANX74XX_REG_IRQ_EXT_SOURCE_1 0x3e -#define ANX74XX_REG_EXT_SOP (1 << 6) -#define ANX74XX_REG_EXT_SOP_PRIME (1 << 7) +#define ANX74XX_REG_EXT_SOP BIT(6) +#define ANX74XX_REG_EXT_SOP_PRIME BIT(7) #define ANX74XX_REG_IRQ_EXT_SOURCE_2 0x4e -#define ANX74XX_REG_EXT_SOP_PRIME_PRIME (1 << 0) -#define ANX74XX_REG_EXT_HARD_RST (1 << 2) +#define ANX74XX_REG_EXT_SOP_PRIME_PRIME BIT(0) +#define ANX74XX_REG_EXT_HARD_RST BIT(2) #define ANX74XX_REG_IRQ_EXT_SOURCE_3 0x4f -#define ANX74XX_REG_CLEAR_SOFT_IRQ (1 << 2) +#define ANX74XX_REG_CLEAR_SOFT_IRQ BIT(2) #define ANX74XX_REG_IRQ_SOURCE_RECV_MSG 0x6b -#define ANX74XX_REG_IRQ_CC_MSG_INT (1 << 0) -#define ANX74XX_REG_IRQ_CC_STATUS_INT (1 << 1) -#define ANX74XX_REG_IRQ_GOOD_CRC_INT (1 << 2) -#define ANX74XX_REG_IRQ_TX_FAIL_INT (1 << 3) +#define ANX74XX_REG_IRQ_CC_MSG_INT BIT(0) +#define ANX74XX_REG_IRQ_CC_STATUS_INT BIT(1) +#define ANX74XX_REG_IRQ_GOOD_CRC_INT BIT(2) +#define ANX74XX_REG_IRQ_TX_FAIL_INT BIT(3) #define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK 0x6c #define ANX74XX_REG_CLEAR_SET_BITS 0xff -#define ANX74XX_REG_ALERT_HARD_RST_RECV (1 << 6) -#define ANX74XX_REG_ALERT_MSG_RECV (1 << 5) -#define ANX74XX_REG_ALERT_TX_MSG_ERROR (1 << 4) -#define ANX74XX_REG_ALERT_TX_ACK_RECV (1 << 3) -#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK (1 << 2) -#define ANX74XX_REG_ALERT_TX_HARD_RESETOK (1 << 1) -#define ANX74XX_REG_ALERT_CC_CHANGE (1 << 0) +#define ANX74XX_REG_ALERT_HARD_RST_RECV BIT(6) +#define ANX74XX_REG_ALERT_MSG_RECV BIT(5) +#define ANX74XX_REG_ALERT_TX_MSG_ERROR BIT(4) +#define ANX74XX_REG_ALERT_TX_ACK_RECV BIT(3) +#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK BIT(2) +#define ANX74XX_REG_ALERT_TX_HARD_RESETOK BIT(1) +#define ANX74XX_REG_ALERT_CC_CHANGE BIT(0) #define ANX74XX_REG_ANALOG_CTRL_2 0x43 #define ANX74XX_REG_MODE_TRANS 0x01 @@ -181,12 +181,12 @@ #define ANX74XX_REG_CTRL_FW 0x2E #define CLEAR_RX_BUFFER (1) #define ANX74XX_REG_POWER_DOWN_CTRL 0x0d -#define ANX74XX_REG_STATUS_CC1_VRD_USB (1 << 7) -#define ANX74XX_REG_STATUS_CC1_VRD_1P5 (1 << 6) -#define ANX74XX_REG_STATUS_CC1_VRD_3P0 (1 << 5) -#define ANX74XX_REG_STATUS_CC2_VRD_USB (1 << 4) -#define ANX74XX_REG_STATUS_CC2_VRD_1P5 (1 << 3) -#define ANX74XX_REG_STATUS_CC2_VRD_3P0 (1 << 2) +#define ANX74XX_REG_STATUS_CC1_VRD_USB BIT(7) +#define ANX74XX_REG_STATUS_CC1_VRD_1P5 BIT(6) +#define ANX74XX_REG_STATUS_CC1_VRD_3P0 BIT(5) +#define ANX74XX_REG_STATUS_CC2_VRD_USB BIT(4) +#define ANX74XX_REG_STATUS_CC2_VRD_1P5 BIT(3) +#define ANX74XX_REG_STATUS_CC2_VRD_3P0 BIT(2) /* defined in the inter-bock Spec: 4.2.10 CC Detect Status */ #define ANX74XX_REG_CC_STATUS_MASK 0xf diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c index c9d6045b44..bac65892de 100644 --- a/driver/tcpm/anx7688.c +++ b/driver/tcpm/anx7688.c @@ -11,19 +11,19 @@ #include "timer.h" #include "usb_mux.h" -#define ANX7688_VENDOR_ALERT (1 << 15) +#define ANX7688_VENDOR_ALERT BIT(15) #define ANX7688_REG_STATUS 0x82 -#define ANX7688_REG_STATUS_LINK (1 << 0) +#define ANX7688_REG_STATUS_LINK BIT(0) #define ANX7688_REG_HPD 0x83 -#define ANX7688_REG_HPD_HIGH (1 << 0) -#define ANX7688_REG_HPD_IRQ (1 << 1) -#define ANX7688_REG_HPD_ENABLE (1 << 2) +#define ANX7688_REG_HPD_HIGH BIT(0) +#define ANX7688_REG_HPD_IRQ BIT(1) +#define ANX7688_REG_HPD_ENABLE BIT(2) #define ANX7688_USBC_ADDR 0x50 #define ANX7688_REG_RAMCTRL 0xe7 -#define ANX7688_REG_RAMCTRL_BOOT_DONE (1 << 6) +#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6) static int anx7688_init(int port) { diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c index f63e9e38bb..b31a9192f7 100644 --- a/driver/tcpm/it83xx.c +++ b/driver/tcpm/it83xx.c @@ -45,7 +45,7 @@ void it83xx_disable_pd_module(int port) if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG && *usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) { /* Disable PD PHY */ - IT83XX_USBPD_GCR(port) &= ~((1 << 0) | (1 << 4)); + IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4)); /* Power down CC1/CC2 */ IT83XX_USBPD_CCGCR(port) |= 0x1f; /* Disable CC1/CC2 voltage detector */ @@ -70,10 +70,10 @@ static enum tcpc_cc_voltage_status it83xx_get_cc( /* select Rp */ if (pull) - CLEAR_MASK(cc_state, (1 << 2)); + CLEAR_MASK(cc_state, BIT(2)); /* select Rd */ else - SET_MASK(cc_state, (1 << 2)); + SET_MASK(cc_state, BIT(2)); /* sink */ if (USBPD_GET_POWER_ROLE(port) == USBPD_POWER_ROLE_CONSUMER) { @@ -181,7 +181,7 @@ static enum tcpc_transmit_complete it83xx_tx_data( if (length) { /* set data bit */ - IT83XX_USBPD_MTSR0(port) |= (1 << 4); + IT83XX_USBPD_MTSR0(port) |= BIT(4); /* set data length setting */ IT83XX_USBPD_MTSR1(port) |= length; /* set data */ @@ -279,9 +279,9 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled) static void it83xx_enable_cc(enum usbpd_port port, int enable) { if (enable) - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 4)); + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(4)); else - SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 4)); + SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(4)); } static void it83xx_set_power_role(enum usbpd_port port, int power_role) @@ -300,11 +300,11 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) */ IT83XX_USBPD_CCADCR(port) = 0x08; /* bit0: source */ - SET_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0)); + SET_MASK(IT83XX_USBPD_PDMSR(port), BIT(0)); /* bit1: CC1 select Rp */ - SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 1)); + SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(1)); /* bit3: CC2 select Rp */ - SET_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3)); + SET_MASK(IT83XX_USBPD_BMCSR(port), BIT(3)); } else { /* * bit[2,3] BMC Rx threshold setting @@ -318,11 +318,11 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) */ IT83XX_USBPD_CCADCR(port) = 0x04; /* bit0: sink */ - CLEAR_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0)); + CLEAR_MASK(IT83XX_USBPD_PDMSR(port), BIT(0)); /* bit1: CC1 select Rd */ - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 1)); + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(1)); /* bit3: CC2 select Rd */ - CLEAR_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3)); + CLEAR_MASK(IT83XX_USBPD_BMCSR(port), BIT(3)); } } @@ -339,10 +339,10 @@ static void it83xx_init(enum usbpd_port port, int role) invalidate_last_message_id(port); #ifdef IT83XX_USBPD_CC_PARAMETER_RELOAD /* bit7: Reload CC parameter setting. */ - IT83XX_USBPD_CCPSR0(port) |= (1 << 7); + IT83XX_USBPD_CCPSR0(port) |= BIT(7); #endif /* reset and disable HW auto generate message header */ - IT83XX_USBPD_GCR(port) = (1 << 5); + IT83XX_USBPD_GCR(port) = BIT(5); USBPD_SW_RESET(port); /* set SOP: receive SOP message only. * bit[7]: SOP" support enable. @@ -379,7 +379,7 @@ static void it83xx_init(enum usbpd_port port, int role) /* disable vconn */ it83xx_enable_vconn(port, 0); /* TX start from high */ - IT83XX_USBPD_CCADCR(port) |= (1 << 6); + IT83XX_USBPD_CCADCR(port) |= BIT(6); /* enable cc1/cc2 */ *usbpd_ctrl_regs[port].cc1 = IT83XX_USBPD_CC_PIN_CONFIG; *usbpd_ctrl_regs[port].cc2 = IT83XX_USBPD_CC_PIN_CONFIG; @@ -393,9 +393,9 @@ static void it83xx_select_polarity(enum usbpd_port port, { /* cc1/cc2 selection */ if (cc_pin == USBPD_CC_PIN_1) - SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 0)); + SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(0)); else - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 0)); + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(0)); } static int it83xx_set_cc(enum usbpd_port port, int pull) @@ -457,7 +457,7 @@ static int it83xx_tcpm_select_rp_value(int port, int rp_sel) rp = 2 << 2; break; case TYPEC_RP_3A0: - rp = 1 << 2; + rp = BIT(2); break; case TYPEC_RP_USB: default: diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h index 0f6be9b24f..73c613ff0e 100644 --- a/driver/tcpm/it83xx_pd.h +++ b/driver/tcpm/it83xx_pd.h @@ -14,7 +14,7 @@ */ #define IT83XX_USBPD_CC_PIN_CONFIG 0x86 -#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM((1 << 17)) +#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM(BIT(17)) #define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) #define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) @@ -51,9 +51,9 @@ #define USBPD_GET_POWER_ROLE(port) \ (IT83XX_USBPD_PDMSR(port) & 1) #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \ - (IT83XX_USBPD_CCGCR(port) & (1 << 1)) + (IT83XX_USBPD_CCGCR(port) & BIT(1)) #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \ - (IT83XX_USBPD_BMCSR(port) & (1 << 3)) + (IT83XX_USBPD_BMCSR(port) & BIT(3)) #define USBPD_GET_PULL_CC_SELECTION(port) \ (IT83XX_USBPD_CCGCR(port) & 1) diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h index 5fdcffbdca..1d30d27f8f 100644 --- a/driver/tcpm/mt6370.h +++ b/driver/tcpm/mt6370.h @@ -63,45 +63,45 @@ * MT6370_REG_CLK_CTRL2 0x87 */ -#define MT6370_REG_CLK_DIV_600K_EN (1 << 7) -#define MT6370_REG_CLK_BCLK2_EN (1 << 6) -#define MT6370_REG_CLK_BCLK2_TG_EN (1 << 5) -#define MT6370_REG_CLK_DIV_300K_EN (1 << 3) -#define MT6370_REG_CLK_CK_300K_EN (1 << 2) -#define MT6370_REG_CLK_BCLK_EN (1 << 1) -#define MT6370_REG_CLK_BCLK_TH_EN (1 << 0) +#define MT6370_REG_CLK_DIV_600K_EN BIT(7) +#define MT6370_REG_CLK_BCLK2_EN BIT(6) +#define MT6370_REG_CLK_BCLK2_TG_EN BIT(5) +#define MT6370_REG_CLK_DIV_300K_EN BIT(3) +#define MT6370_REG_CLK_CK_300K_EN BIT(2) +#define MT6370_REG_CLK_BCLK_EN BIT(1) +#define MT6370_REG_CLK_BCLK_TH_EN BIT(0) /* * MT6370_REG_CLK_CTRL3 0x88 */ -#define MT6370_REG_CLK_OSCMUX_RG_EN (1 << 7) -#define MT6370_REG_CLK_CK_24M_EN (1 << 6) -#define MT6370_REG_CLK_OSC_RG_EN (1 << 5) -#define MT6370_REG_CLK_DIV_2P4M_EN (1 << 4) -#define MT6370_REG_CLK_CK_2P4M_EN (1 << 3) -#define MT6370_REG_CLK_PCLK_EN (1 << 2) -#define MT6370_REG_CLK_PCLK_RG_EN (1 << 1) -#define MT6370_REG_CLK_PCLK_TG_EN (1 << 0) +#define MT6370_REG_CLK_OSCMUX_RG_EN BIT(7) +#define MT6370_REG_CLK_CK_24M_EN BIT(6) +#define MT6370_REG_CLK_OSC_RG_EN BIT(5) +#define MT6370_REG_CLK_DIV_2P4M_EN BIT(4) +#define MT6370_REG_CLK_CK_2P4M_EN BIT(3) +#define MT6370_REG_CLK_PCLK_EN BIT(2) +#define MT6370_REG_CLK_PCLK_RG_EN BIT(1) +#define MT6370_REG_CLK_PCLK_TG_EN BIT(0) /* * MT6370_REG_RX_TX_DBG 0x8b */ -#define MT6370_REG_RX_TX_DBG_RX_BUSY (1 << 7) -#define MT6370_REG_RX_TX_DBG_TX_BUSY (1 << 6) +#define MT6370_REG_RX_TX_DBG_RX_BUSY BIT(7) +#define MT6370_REG_RX_TX_DBG_TX_BUSY BIT(6) /* * MT6370_REG_BMC_CTRL 0x90 */ -#define MT6370_REG_IDLE_EN (1 << 6) -#define MT6370_REG_DISCHARGE_EN (1 << 5) -#define MT6370_REG_BMCIO_LPRPRD (1 << 4) -#define MT6370_REG_BMCIO_LPEN (1 << 3) -#define MT6370_REG_BMCIO_BG_EN (1 << 2) -#define MT6370_REG_VBUS_DET_EN (1 << 1) -#define MT6370_REG_BMCIO_OSC_EN (1 << 0) +#define MT6370_REG_IDLE_EN BIT(6) +#define MT6370_REG_DISCHARGE_EN BIT(5) +#define MT6370_REG_BMCIO_LPRPRD BIT(4) +#define MT6370_REG_BMCIO_LPEN BIT(3) +#define MT6370_REG_BMCIO_BG_EN BIT(2) +#define MT6370_REG_VBUS_DET_EN BIT(1) +#define MT6370_REG_BMCIO_OSC_EN BIT(0) #define MT6370_REG_BMC_CTRL_DEFAULT \ (MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN | \ MT6370_REG_BMCIO_OSC_EN) @@ -111,41 +111,41 @@ */ #define MT6370_MASK_DISCHARGE_LVL 0x03 -#define MT6370_REG_DISCHARGE_LVL (1 << 0) +#define MT6370_REG_DISCHARGE_LVL BIT(0) /* * MT6370_REG_RT_STATUS 0x97 */ -#define MT6370_REG_RA_DETACH (1 << 5) -#define MT6370_REG_VBUS_80 (1 << 1) +#define MT6370_REG_RA_DETACH BIT(5) +#define MT6370_REG_VBUS_80 BIT(1) /* * MT6370_REG_RT_INT 0x98 */ -#define MT6370_REG_INT_RA_DETACH (1 << 5) -#define MT6370_REG_INT_WATCHDOG (1 << 2) -#define MT6370_REG_INT_VBUS_80 (1 << 1) -#define MT6370_REG_INT_WAKEUP (1 << 0) +#define MT6370_REG_INT_RA_DETACH BIT(5) +#define MT6370_REG_INT_WATCHDOG BIT(2) +#define MT6370_REG_INT_VBUS_80 BIT(1) +#define MT6370_REG_INT_WAKEUP BIT(0) /* * MT6370_REG_RT_MASK 0x99 */ -#define MT6370_REG_M_RA_DETACH (1 << 5) -#define MT6370_REG_M_WATCHDOG (1 << 2) -#define MT6370_REG_M_VBUS_80 (1 << 1) -#define MT6370_REG_M_WAKEUP (1 << 0) +#define MT6370_REG_M_RA_DETACH BIT(5) +#define MT6370_REG_M_WATCHDOG BIT(2) +#define MT6370_REG_M_VBUS_80 BIT(1) +#define MT6370_REG_M_WAKEUP BIT(0) /* * MT6370_REG_IDLE_CTRL 0x9B */ -#define MT6370_REG_CK_300K_SEL (1 << 7) -#define MT6370_REG_SHIPPING_OFF (1 << 5) -#define MT6370_REG_ENEXTMSG (1 << 4) -#define MT6370_REG_AUTOIDLE_EN (1 << 3) +#define MT6370_REG_CK_300K_SEL BIT(7) +#define MT6370_REG_SHIPPING_OFF BIT(5) +#define MT6370_REG_ENEXTMSG BIT(4) +#define MT6370_REG_AUTOIDLE_EN BIT(3) /* timeout = (tout*2+1) * 6.4ms */ #ifdef CONFIG_USB_PD_REV30 @@ -161,7 +161,7 @@ * MT6370_REG_INTRST_CTRL 0x9C */ -#define MT6370_REG_INTRST_EN (1 << 7) +#define MT6370_REG_INTRST_EN BIT(7) /* timeout = (tout+1) * 0.2sec */ #define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03)) @@ -170,7 +170,7 @@ * MT6370_REG_WATCHDOG_CTRL 0x9D */ -#define MT6370_REG_WATCHDOG_EN (1 << 7) +#define MT6370_REG_WATCHDOG_EN BIT(7) /* timeout = (tout+1) * 0.4sec */ #define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07)) @@ -179,7 +179,7 @@ * MT6370_REG_I2CRST_CTRL 0x9E */ -#define MT6370_REG_I2CRST_EN (1 << 7) +#define MT6370_REG_I2CRST_EN BIT(7) /* timeout = (tout+1) * 12.5ms */ #define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f)) diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index 6d0faab56f..6b94b56094 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -43,8 +43,8 @@ #define PS8XXX_REG_VENDOR_ID_L 0x00 #define PS8XXX_REG_VENDOR_ID_H 0x01 #define MUX_IN_HPD_ASSERTION_REG 0xD0 -#define IN_HPD (1 << 0) -#define HPD_IRQ (1 << 1) +#define IN_HPD BIT(0) +#define HPD_IRQ BIT(1) #define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3 #define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 #define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 @@ -55,8 +55,8 @@ #define FW_VER_REG 0x82 #define MUX_IN_HPD_ASSERTION_REG 0xD0 -#define IN_HPD (1 << 0) -#define HPD_IRQ (1 << 1) +#define IN_HPD BIT(0) +#define HPD_IRQ BIT(1) #endif diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c index f20fbd91e3..59393a62a9 100644 --- a/driver/tcpm/tcpci.c +++ b/driver/tcpm/tcpci.c @@ -420,7 +420,7 @@ struct cached_tcpm_message { }; /* Cache depth needs to be power of 2 */ -#define CACHE_DEPTH (1 << 2) +#define CACHE_DEPTH BIT(2) #define CACHE_DEPTH_MASK (CACHE_DEPTH - 1) struct queue { diff --git a/driver/tcpm/tcpci.h b/driver/tcpm/tcpci.h index 8084e92232..600e28f284 100644 --- a/driver/tcpm/tcpci.h +++ b/driver/tcpm/tcpci.h @@ -43,9 +43,9 @@ #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB (1 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED (1 << 0) +#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) #define TCPC_REG_TCPC_CTRL 0x19 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity) @@ -62,7 +62,7 @@ #define TCPC_REG_FAULT_CTRL 0x1b #define TCPC_REG_POWER_CTRL 0x1c -#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE (1 << 2) +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) #define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1) diff --git a/driver/temp_sensor/adt7481.h b/driver/temp_sensor/adt7481.h index 11e9856b9c..45da88560e 100644 --- a/driver/temp_sensor/adt7481.h +++ b/driver/temp_sensor/adt7481.h @@ -55,18 +55,18 @@ #define ADT7481_MANUFACTURER_ID 0x3e /* Config1 register bits */ -#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK (1 << 0) -#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK (1 << 1) -#define ADT7481_CONFIG1_TEMP_RANGE (1 << 2) -#define ADT7481_CONFIG1_SEL_REMOTE2 (1 << 3) +#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK BIT(0) +#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK BIT(1) +#define ADT7481_CONFIG1_TEMP_RANGE BIT(2) +#define ADT7481_CONFIG1_SEL_REMOTE2 BIT(3) /* ADT7481_CONFIG1_MODE bit is use to enable THERM mode */ -#define ADT7481_CONFIG1_MODE (1 << 5) -#define ADT7481_CONFIG1_RUN_L (1 << 6) +#define ADT7481_CONFIG1_MODE BIT(5) +#define ADT7481_CONFIG1_RUN_L BIT(6) /* mask all alerts on ALERT# pin */ -#define ADT7481_CONFIG1_ALERT_MASK_L (1 << 7) +#define ADT7481_CONFIG1_ALERT_MASK_L BIT(7) /* Config2 register bits */ -#define ADT7481_CONFIG2_LOCK (1 << 7) +#define ADT7481_CONFIG2_LOCK BIT(7) /* Conversion Rate/Channel Select Register */ #define ADT7481_CONV_RATE_MASK (0x0f) @@ -85,28 +85,28 @@ #define ADT7481_CONV_RATE_73MS_AVE (0x0b) #define ADT7481_CONV_CHAN_SELECT_MASK (0x30) #define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN (0 << 4) -#define ADT7481_CONV_CHAN_SEL_LOCAL (1 << 4) +#define ADT7481_CONV_CHAN_SEL_LOCAL BIT(4) #define ADT7481_CONV_CHAN_SEL_REMOTE1 (2 << 4) #define ADT7481_CONV_CHAN_SEL_REMOTE2 (3 << 4) -#define ADT7481_CONV_AVERAGING_L (1 << 7) +#define ADT7481_CONV_AVERAGING_L BIT(7) /* Status1 register bits */ -#define ADT7481_STATUS1_LOCAL_THERM_ALARM (1 << 0) -#define ADT7481_STATUS1_REMOTE1_THERM_ALARM (1 << 1) -#define ADT7481_STATUS1_REMOTE1_OPEN (1 << 2) -#define ADT7481_STATUS1_REMOTE1_LOW_ALARM (1 << 3) -#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM (1 << 4) -#define ADT7481_STATUS1_LOCAL_LOW_ALARM (1 << 5) -#define ADT7481_STATUS1_LOCAL_HIGH_ALARM (1 << 6) -#define ADT7481_STATUS1_BUSY (1 << 7) +#define ADT7481_STATUS1_LOCAL_THERM_ALARM BIT(0) +#define ADT7481_STATUS1_REMOTE1_THERM_ALARM BIT(1) +#define ADT7481_STATUS1_REMOTE1_OPEN BIT(2) +#define ADT7481_STATUS1_REMOTE1_LOW_ALARM BIT(3) +#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM BIT(4) +#define ADT7481_STATUS1_LOCAL_LOW_ALARM BIT(5) +#define ADT7481_STATUS1_LOCAL_HIGH_ALARM BIT(6) +#define ADT7481_STATUS1_BUSY BIT(7) /* Status2 register bits */ -#define ADT7481_STATUS2_ALERT (1 << 0) -#define ADT7481_STATUS2_REMOTE2_THERM_ALARM (1 << 1) -#define ADT7481_STATUS2_REMOTE2_OPEN (1 << 2) -#define ADT7481_STATUS2_REMOTE2_LOW_ALARM (1 << 3) -#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM (1 << 4) +#define ADT7481_STATUS2_ALERT BIT(0) +#define ADT7481_STATUS2_REMOTE2_THERM_ALARM BIT(1) +#define ADT7481_STATUS2_REMOTE2_OPEN BIT(2) +#define ADT7481_STATUS2_REMOTE2_LOW_ALARM BIT(3) +#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM BIT(4) /* Consecutive Alert register */ #define ADT7481_CONSEC_MASK (0xf) @@ -114,9 +114,9 @@ #define ADT7481_CONSEC_2 (0x2) #define ADT7481_CONSEC_3 (0x6) #define ADT7481_CONSEC_4 (0xe) -#define ADT7481_CONSEC_EN_SCL_TIMEOUT (1 << 5) -#define ADT7481_CONSEC_EN_SDA_TIMEOUT (1 << 6) -#define ADT7481_CONSEC_MASK_LOCAL_ALERT (1 << 7) +#define ADT7481_CONSEC_EN_SCL_TIMEOUT BIT(5) +#define ADT7481_CONSEC_EN_SDA_TIMEOUT BIT(6) +#define ADT7481_CONSEC_MASK_LOCAL_ALERT BIT(7) /* Limits */ diff --git a/driver/temp_sensor/bd99992gw.h b/driver/temp_sensor/bd99992gw.h index 27a9943de1..7db3990e07 100644 --- a/driver/temp_sensor/bd99992gw.h +++ b/driver/temp_sensor/bd99992gw.h @@ -26,26 +26,26 @@ enum bd99992gw_adc_channel { /* Registers */ #define BD99992GW_REG_IRQLVL1 0x02 -#define BD99992GW_IRQLVL1_ADC (1 << 1) /* ADC IRQ asserted */ +#define BD99992GW_IRQLVL1_ADC BIT(1) /* ADC IRQ asserted */ #define BD99992GW_REG_ADC1INT 0x03 -#define BD99992GW_ADC1INT_RND (1 << 0) /* RR cycle completed */ +#define BD99992GW_ADC1INT_RND BIT(0) /* RR cycle completed */ #define BD99992GW_REG_MADC1INT 0x0a -#define BD99992GW_MADC1INT_RND (1 << 0) /* RR cycle mask */ +#define BD99992GW_MADC1INT_RND BIT(0) /* RR cycle mask */ #define BD99992GW_REG_IRQLVL1MSK 0x13 -#define BD99992GW_IRQLVL1MSK_MADC (1 << 1) /* ADC IRQ mask */ +#define BD99992GW_IRQLVL1MSK_MADC BIT(1) /* ADC IRQ mask */ #define BD99992GW_REG_ADC1CNTL1 0x80 #define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */ #define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */ -#define BD99992GW_ADC1CNTL1_ADPAUSE (1 << 2) /* ADC pause */ -#define BD99992GW_ADC1CNTL1_ADSTRT (1 << 1) /* ADC start */ -#define BD99992GW_ADC1CNTL1_ADEN (1 << 0) /* ADC enable */ +#define BD99992GW_ADC1CNTL1_ADPAUSE BIT(2) /* ADC pause */ +#define BD99992GW_ADC1CNTL1_ADSTRT BIT(1) /* ADC start */ +#define BD99992GW_ADC1CNTL1_ADEN BIT(0) /* ADC enable */ #define BD99992GW_REG_ADC1CNTL2 0x81 -#define BD99992GW_ADC1CNTL2_ADCTHERM (1 << 0) /* Enable ADC sequencing */ +#define BD99992GW_ADC1CNTL2_ADCTHERM BIT(0) /* Enable ADC sequencing */ /* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */ #define BD99992GW_ADC_POINTER_REG_COUNT 8 @@ -57,7 +57,7 @@ enum bd99992gw_adc_channel { #define BD99992GW_REG_ADC1ADDR5 0x87 #define BD99992GW_REG_ADC1ADDR6 0x88 #define BD99992GW_REG_ADC1ADDR7 0x89 -#define BD99992GW_ADC1ADDR_STOP (1 << 3) /* Last conversion channel */ +#define BD99992GW_ADC1ADDR_STOP BIT(3) /* Last conversion channel */ /* Result registers */ #define BD99992GW_REG_ADC1DATA0L 0x95 diff --git a/driver/temp_sensor/g78x.h b/driver/temp_sensor/g78x.h index 8fa78ffa83..2ef75f1da9 100644 --- a/driver/temp_sensor/g78x.h +++ b/driver/temp_sensor/g78x.h @@ -49,18 +49,18 @@ #define G78X_DEVICE_ID 0xFF /* Config register bits */ -#define G78X_CONFIGURATION_STANDBY (1 << 6) -#define G78X_CONFIGURATION_ALERT_MASK (1 << 7) +#define G78X_CONFIGURATION_STANDBY BIT(6) +#define G78X_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM (1 << 0) -#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM (1 << 1) -#define G78X_STATUS_REMOTE1_TEMP_FAULT (1 << 2) -#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM (1 << 3) -#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM (1 << 4) -#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM (1 << 5) -#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM (1 << 6) -#define G78X_STATUS_BUSY (1 << 7) +#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(0) +#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(1) +#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(2) +#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(3) +#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(4) +#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) +#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define G78X_STATUS_BUSY BIT(7) #elif defined(CONFIG_TEMP_SENSOR_G782) /* G782 register */ @@ -105,25 +105,25 @@ #define G78X_DEVICE_ID 0xFF /* Config register bits */ -#define G78X_CONFIGURATION_REMOTE2_DIS (1 << 5) -#define G78X_CONFIGURATION_STANDBY (1 << 6) -#define G78X_CONFIGURATION_ALERT_MASK (1 << 7) +#define G78X_CONFIGURATION_REMOTE2_DIS BIT(5) +#define G78X_CONFIGURATION_STANDBY BIT(6) +#define G78X_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM (1 << 0) -#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM (1 << 1) -#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM (1 << 2) -#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM (1 << 3) -#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM (1 << 4) -#define G78X_STATUS_REMOTE2_TEMP_FAULT (1 << 5) -#define G78X_STATUS_REMOTE1_TEMP_FAULT (1 << 6) -#define G78X_STATUS_BUSY (1 << 7) +#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(0) +#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(1) +#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(2) +#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM BIT(3) +#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(4) +#define G78X_STATUS_REMOTE2_TEMP_FAULT BIT(5) +#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(6) +#define G78X_STATUS_BUSY BIT(7) /* Status1 register bits */ -#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM (1 << 4) -#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM (1 << 5) -#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM (1 << 6) -#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM (1 << 7) +#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM BIT(4) +#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM BIT(5) +#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(6) +#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(7) #endif /** diff --git a/driver/temp_sensor/tmp006.c b/driver/temp_sensor/tmp006.c index 67b31dfa98..fd81647c41 100644 --- a/driver/temp_sensor/tmp006.c +++ b/driver/temp_sensor/tmp006.c @@ -30,10 +30,10 @@ #define ALGORITHM_PARAMS 12 /* Flags for tdata->fail */ -#define FAIL_INIT (1 << 0) /* Just initialized */ -#define FAIL_POWER (1 << 1) /* Sensor not powered */ -#define FAIL_I2C (1 << 2) /* I2C communication error */ -#define FAIL_NOT_READY (1 << 3) /* Data not ready */ +#define FAIL_INIT BIT(0) /* Just initialized */ +#define FAIL_POWER BIT(1) /* Sensor not powered */ +#define FAIL_I2C BIT(2) /* I2C communication error */ +#define FAIL_NOT_READY BIT(3) /* Data not ready */ /* State and conversion factors to track for each sensor */ struct tmp006_data_t { diff --git a/driver/temp_sensor/tmp112.c b/driver/temp_sensor/tmp112.c index f567e2433c..32ffc1ced6 100644 --- a/driver/temp_sensor/tmp112.c +++ b/driver/temp_sensor/tmp112.c @@ -74,7 +74,7 @@ static void tmp112_init(void) set_mask = (3 << 5); /* not oneshot mode */ - clr_mask = (1 << 7); + clr_mask = BIT(7); raw_read16(TMP112_REG_CONF, &tmp); raw_write16(TMP112_REG_CONF, (tmp & ~clr_mask) | set_mask); diff --git a/driver/temp_sensor/tmp411.h b/driver/temp_sensor/tmp411.h index a0ad95a5d8..52635e810f 100644 --- a/driver/temp_sensor/tmp411.h +++ b/driver/temp_sensor/tmp411.h @@ -67,20 +67,20 @@ #define TMP411d_DEVICE_ID_VAL 0x12 /* Config register bits */ -#define TMP411_CONFIG1_TEMP_RANGE (1 << 2) +#define TMP411_CONFIG1_TEMP_RANGE BIT(2) /* TMP411_CONFIG1_MODE bit is use to enable THERM mode */ -#define TMP411_CONFIG1_MODE (1 << 5) -#define TMP411_CONFIG1_RUN_L (1 << 6) -#define TMP411_CONFIG1_ALERT_MASK_L (1 << 7) +#define TMP411_CONFIG1_MODE BIT(5) +#define TMP411_CONFIG1_RUN_L BIT(6) +#define TMP411_CONFIG1_ALERT_MASK_L BIT(7) /* Status register bits */ -#define TMP411_STATUS_TEMP_THERM_ALARM (1 << 1) -#define TMP411_STATUS_OPEN (1 << 2) -#define TMP411_STATUS_TEMP_LOW_ALARM (1 << 3) -#define TMP411_STATUS_TEMP_HIGH_ALARM (1 << 4) -#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM (1 << 5) -#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM (1 << 6) -#define TMP411_STATUS_BUSY (1 << 7) +#define TMP411_STATUS_TEMP_THERM_ALARM BIT(1) +#define TMP411_STATUS_OPEN BIT(2) +#define TMP411_STATUS_TEMP_LOW_ALARM BIT(3) +#define TMP411_STATUS_TEMP_HIGH_ALARM BIT(4) +#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) +#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define TMP411_STATUS_BUSY BIT(7) /* Limits */ #define TMP411_HYSTERESIS_HIGH_LIMIT 255 diff --git a/driver/temp_sensor/tmp432.h b/driver/temp_sensor/tmp432.h index 2d8d2515dc..f9bd03dd32 100644 --- a/driver/temp_sensor/tmp432.h +++ b/driver/temp_sensor/tmp432.h @@ -67,22 +67,22 @@ #define TMP432_MANUFACTURER_ID 0xfe /* Config register bits */ -#define TMP432_CONFIG1_TEMP_RANGE (1 << 2) +#define TMP432_CONFIG1_TEMP_RANGE BIT(2) /* TMP432_CONFIG1_MODE bit is use to enable THERM mode */ -#define TMP432_CONFIG1_MODE (1 << 5) -#define TMP432_CONFIG1_RUN_L (1 << 6) -#define TMP432_CONFIG1_ALERT_MASK_L (1 << 7) -#define TMP432_CONFIG2_RESISTANCE_CORRECTION (1 << 2) -#define TMP432_CONFIG2_LOCAL_ENABLE (1 << 3) -#define TMP432_CONFIG2_REMOTE1_ENABLE (1 << 4) -#define TMP432_CONFIG2_REMOTE2_ENABLE (1 << 5) +#define TMP432_CONFIG1_MODE BIT(5) +#define TMP432_CONFIG1_RUN_L BIT(6) +#define TMP432_CONFIG1_ALERT_MASK_L BIT(7) +#define TMP432_CONFIG2_RESISTANCE_CORRECTION BIT(2) +#define TMP432_CONFIG2_LOCAL_ENABLE BIT(3) +#define TMP432_CONFIG2_REMOTE1_ENABLE BIT(4) +#define TMP432_CONFIG2_REMOTE2_ENABLE BIT(5) /* Status register bits */ -#define TMP432_STATUS_TEMP_THERM_ALARM (1 << 1) -#define TMP432_STATUS_OPEN (1 << 2) -#define TMP432_STATUS_TEMP_LOW_ALARM (1 << 3) -#define TMP432_STATUS_TEMP_HIGH_ALARM (1 << 4) -#define TMP432_STATUS_BUSY (1 << 7) +#define TMP432_STATUS_TEMP_THERM_ALARM BIT(1) +#define TMP432_STATUS_OPEN BIT(2) +#define TMP432_STATUS_TEMP_LOW_ALARM BIT(3) +#define TMP432_STATUS_TEMP_HIGH_ALARM BIT(4) +#define TMP432_STATUS_BUSY BIT(7) /* Limintaions */ #define TMP432_HYSTERESIS_HIGH_LIMIT 255 diff --git a/driver/temp_sensor/tmp468.h b/driver/temp_sensor/tmp468.h index ec528d0dcc..4b7f6bb814 100644 --- a/driver/temp_sensor/tmp468.h +++ b/driver/temp_sensor/tmp468.h @@ -77,7 +77,7 @@ #define TMP468_DEVICE_ID 0xfd #define TMP468_MANUFACTURER_ID 0xfe -#define TMP468_SHUTDOWN (1 << 5) +#define TMP468_SHUTDOWN BIT(5) enum tmp468_channel_id { TMP468_CHANNEL_LOCAL, diff --git a/driver/touchpad_elan.c b/driver/touchpad_elan.c index f0e456b525..848985109e 100644 --- a/driver/touchpad_elan.c +++ b/driver/touchpad_elan.c @@ -74,15 +74,15 @@ #define ETP_I2C_IAP_RESET_CMD 0x0314 #define ETP_I2C_IAP_RESET 0xF0F0 #define ETP_I2C_IAP_CTRL_CMD 0x0310 -#define ETP_I2C_MAIN_MODE_ON (1 << 9) +#define ETP_I2C_MAIN_MODE_ON BIT(9) #define ETP_I2C_IAP_CMD 0x0311 #define ETP_I2C_IAP_PASSWORD 0x1EA5 #define ETP_I2C_IAP_REG_L 0x01 #define ETP_I2C_IAP_REG_H 0x06 -#define ETP_FW_IAP_PAGE_ERR (1 << 5) -#define ETP_FW_IAP_INTF_ERR (1 << 4) +#define ETP_FW_IAP_PAGE_ERR BIT(5) +#define ETP_FW_IAP_INTF_ERR BIT(4) #ifdef CONFIG_USB_UPDATE /* The actual FW_SIZE depends on IC. */ diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c index d4ba6e7d5b..8c4a5cf2dd 100644 --- a/driver/touchpad_st.c +++ b/driver/touchpad_st.c @@ -55,26 +55,26 @@ static void touchpad_power_control(void); */ static int system_state; -#define SYSTEM_STATE_DEBUG_MODE (1 << 0) -#define SYSTEM_STATE_ENABLE_HEAT_MAP (1 << 1) -#define SYSTEM_STATE_ENABLE_DOME_SWITCH (1 << 2) -#define SYSTEM_STATE_ACTIVE_MODE (1 << 3) -#define SYSTEM_STATE_DOME_SWITCH_LEVEL (1 << 4) -#define SYSTEM_STATE_READY (1 << 5) +#define SYSTEM_STATE_DEBUG_MODE BIT(0) +#define SYSTEM_STATE_ENABLE_HEAT_MAP BIT(1) +#define SYSTEM_STATE_ENABLE_DOME_SWITCH BIT(2) +#define SYSTEM_STATE_ACTIVE_MODE BIT(3) +#define SYSTEM_STATE_DOME_SWITCH_LEVEL BIT(4) +#define SYSTEM_STATE_READY BIT(5) /* * Pending action for touchpad. */ static int tp_control; -#define TP_CONTROL_SHALL_HALT (1 << 0) -#define TP_CONTROL_SHALL_RESET (1 << 1) -#define TP_CONTROL_SHALL_INIT (1 << 2) -#define TP_CONTROL_SHALL_INIT_FULL (1 << 3) -#define TP_CONTROL_SHALL_DUMP_ERROR (1 << 4) -#define TP_CONTROL_RESETTING (1 << 5) -#define TP_CONTROL_INIT (1 << 6) -#define TP_CONTROL_INIT_FULL (1 << 7) +#define TP_CONTROL_SHALL_HALT BIT(0) +#define TP_CONTROL_SHALL_RESET BIT(1) +#define TP_CONTROL_SHALL_INIT BIT(2) +#define TP_CONTROL_SHALL_INIT_FULL BIT(3) +#define TP_CONTROL_SHALL_DUMP_ERROR BIT(4) +#define TP_CONTROL_RESETTING BIT(5) +#define TP_CONTROL_INIT BIT(6) +#define TP_CONTROL_INIT_FULL BIT(7) /* * Number of times we have reset the touchpad because of errors. @@ -124,7 +124,7 @@ static struct { struct packet_header_t { uint8_t index; -#define HEADER_FLAGS_NEW_FRAME (1 << 0) +#define HEADER_FLAGS_NEW_FRAME BIT(0) uint8_t flags; } __packed; BUILD_ASSERT(sizeof(struct packet_header_t) < USB_ISO_PACKET_SIZE); @@ -133,7 +133,7 @@ static struct packet_header_t packet_header; /* What will be sent to USB interface. */ struct st_tp_usb_packet_t { -#define USB_FRAME_FLAGS_BUTTON (1 << 0) +#define USB_FRAME_FLAGS_BUTTON BIT(0) /* * This will be true if user clicked on touchpad. * TODO(b/70482333): add corresponding code for button signal. @@ -375,14 +375,14 @@ static int st_tp_update_system_state(int new_state, int mask) }; if (new_state & SYSTEM_STATE_ENABLE_HEAT_MAP) { CPRINTS("Heatmap enabled"); - tx_buf[2] |= 1 << 0; + tx_buf[2] |= BIT(0); need_locked_scan_mode = 1; } else { CPRINTS("Heatmap disabled"); } if (new_state & SYSTEM_STATE_ENABLE_DOME_SWITCH) - tx_buf[2] |= 1 << 1; + tx_buf[2] |= BIT(1); ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0); if (ret) return ret; @@ -1782,7 +1782,7 @@ static int get_heat_map_addr(void) } struct st_tp_interrupt_t { -#define ST_TP_INT_FRAME_AVAILABLE (1 << 0) +#define ST_TP_INT_FRAME_AVAILABLE BIT(0) uint8_t flags; } __packed; diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h index 6ae612be11..ecbddcb324 100644 --- a/driver/touchpad_st.h +++ b/driver/touchpad_st.h @@ -33,10 +33,10 @@ /* Max number of bytes that can be written in I2C to the DMA */ #define ST_TP_DMA_CHUNK_SIZE 32 -#define ST_HOST_BUFFER_DATA_VALID (1 << 0) -#define ST_HOST_BUFFER_MT_READY (1 << 3) -#define ST_HOST_BUFFER_SF_READY (1 << 4) -#define ST_HOST_BUFFER_SS_READY (1 << 5) +#define ST_HOST_BUFFER_DATA_VALID BIT(0) +#define ST_HOST_BUFFER_MT_READY BIT(3) +#define ST_HOST_BUFFER_SF_READY BIT(4) +#define ST_HOST_BUFFER_SS_READY BIT(5) #define ST_TP_SCAN_MODE_ACTIVE 0x00 #define ST_TP_SCAN_MODE_LOW_POWER 0x01 @@ -171,13 +171,13 @@ struct st_tp_system_info_t { ST_TP_SYSTEM_INFO_PART_1_RESERVED) struct st_tp_host_buffer_header_t { -#define ST_TP_BUFFER_HEADER_DATA_VALID (1 << 0) -#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY (1 << 1) -#define ST_TP_BUFFER_HEADER_SYS_FAULT (1 << 2) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY (1 << 3) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY (1 << 4) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY (1 << 5) -#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL (1 << 6) +#define ST_TP_BUFFER_HEADER_DATA_VALID BIT(0) +#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY BIT(1) +#define ST_TP_BUFFER_HEADER_SYS_FAULT BIT(2) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY BIT(3) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY BIT(4) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY BIT(5) +#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL BIT(6) uint8_t flags; uint8_t reserved[3]; uint8_t heatmap_miss_count; diff --git a/driver/usb_mux.c b/driver/usb_mux.c index fd3f4381c4..43ebd9841a 100644 --- a/driver/usb_mux.c +++ b/driver/usb_mux.c @@ -23,7 +23,7 @@ static int enable_debug_prints; */ static uint8_t flags[CONFIG_USB_PD_PORT_COUNT]; -#define USB_MUX_FLAG_IN_LPM (1 << 0) /* Device is in low power mode. */ +#define USB_MUX_FLAG_IN_LPM BIT(0) /* Device is in low power mode. */ static void enter_low_power_mode(int port) diff --git a/driver/usb_mux_it5205.h b/driver/usb_mux_it5205.h index 2c26f7ca41..dbc30466d6 100644 --- a/driver/usb_mux_it5205.h +++ b/driver/usb_mux_it5205.h @@ -20,11 +20,11 @@ /* MUX power down register */ #define IT5205_REG_MUXPDR 0x10 -#define IT5205_MUX_POWER_DOWN (1 << 0) +#define IT5205_MUX_POWER_DOWN BIT(0) /* MUX control register */ #define IT5205_REG_MUXCR 0x11 -#define IT5205_POLARITY_INVERTED (1 << 4) +#define IT5205_POLARITY_INVERTED BIT(4) #define IT5205_DP_USB_CTRL_MASK 0x0f #define IT5205_DP 0x0f diff --git a/driver/usb_mux_ps874x.h b/driver/usb_mux_ps874x.h index e9d4c1ff36..2b98ebcb63 100644 --- a/driver/usb_mux_ps874x.h +++ b/driver/usb_mux_ps874x.h @@ -11,17 +11,17 @@ /* Mode register for setting mux */ #define PS874X_REG_MODE 0x00 #ifdef CONFIG_USB_MUX_PS8740 - #define PS874X_MODE_POLARITY_INVERTED (1 << 4) - #define PS874X_MODE_USB_ENABLED (1 << 5) - #define PS874X_MODE_DP_ENABLED (1 << 6) - #define PS874X_MODE_POWER_DOWN (1 << 7) + #define PS874X_MODE_POLARITY_INVERTED BIT(4) + #define PS874X_MODE_USB_ENABLED BIT(5) + #define PS874X_MODE_DP_ENABLED BIT(6) + #define PS874X_MODE_POWER_DOWN BIT(7) #elif defined(CONFIG_USB_MUX_PS8743) - #define PS874X_MODE_POLARITY_INVERTED (1 << 2) - #define PS874X_MODE_FLIP_PIN_ENABLED (1 << 3) - #define PS874X_MODE_USB_ENABLED (1 << 4) - #define PS874X_MODE_CE_USB_ENABLED (1 << 5) - #define PS874X_MODE_DP_ENABLED (1 << 6) - #define PS874X_MODE_CE_DP_ENABLED (1 << 7) + #define PS874X_MODE_POLARITY_INVERTED BIT(2) + #define PS874X_MODE_FLIP_PIN_ENABLED BIT(3) + #define PS874X_MODE_USB_ENABLED BIT(4) + #define PS874X_MODE_CE_USB_ENABLED BIT(5) + #define PS874X_MODE_DP_ENABLED BIT(6) + #define PS874X_MODE_CE_DP_ENABLED BIT(7) /* To reset the state machine to default */ #define PS874X_MODE_POWER_DOWN (PS874X_MODE_CE_USB_ENABLED | \ PS874X_MODE_CE_DP_ENABLED) @@ -29,10 +29,10 @@ /* Status register for checking mux state */ #define PS874X_REG_STATUS 0x09 -#define PS874X_STATUS_POLARITY_INVERTED (1 << 2) -#define PS874X_STATUS_USB_ENABLED (1 << 3) -#define PS874X_STATUS_DP_ENABLED (1 << 4) -#define PS874X_STATUS_HPD_ASSERTED (1 << 7) +#define PS874X_STATUS_POLARITY_INVERTED BIT(2) +#define PS874X_STATUS_USB_ENABLED BIT(3) +#define PS874X_STATUS_DP_ENABLED BIT(4) +#define PS874X_STATUS_HPD_ASSERTED BIT(7) /* Chip ID / revision registers and expected fused values */ #define PS874X_REG_REVISION_ID1 0xf0 @@ -62,7 +62,7 @@ #define PS874X_USB_EQ_TX_9_5_DB 0xc0 #define PS874X_USB_EQ_TX_7_5_DB 0xe0 #define PS874X_USB_EQ_TERM_100_OHM (0 << 2) - #define PS874X_USB_EQ_TERM_85_OHM (1 << 2) + #define PS874X_USB_EQ_TERM_85_OHM BIT(2) #elif defined(CONFIG_USB_MUX_PS8743) #define PS874X_USB_EQ_TX_12_8_DB 0x00 #define PS874X_USB_EQ_TX_17_DB 0x20 diff --git a/include/bluetooth_le.h b/include/bluetooth_le.h index 8e0422c3a7..25a360730d 100644 --- a/include/bluetooth_le.h +++ b/include/bluetooth_le.h @@ -139,7 +139,7 @@ struct ble_adv_header { /* LL SCA Values. They are shifted left 5 bits for Hop values */ #define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5) -#define BLE_LL_SCA_151_PPM_TO_250_PPM (1 << 5) +#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5) #define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5) #define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5) #define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5) diff --git a/include/button.h b/include/button.h index 5fca2e9037..2e1749c338 100644 --- a/include/button.h +++ b/include/button.h @@ -12,7 +12,7 @@ #include "compile_time_macros.h" #include "gpio.h" -#define BUTTON_FLAG_ACTIVE_HIGH (1 << 0) +#define BUTTON_FLAG_ACTIVE_HIGH BIT(0) enum keyboard_button_type { KEYBOARD_BUTTON_POWER = 0, diff --git a/include/ccd_config.h b/include/ccd_config.h index d3ac141d49..41d81697da 100644 --- a/include/ccd_config.h +++ b/include/ccd_config.h @@ -32,31 +32,31 @@ enum ccd_flag { * Note: This is used internally by CCD config. Do NOT test this * to control other things; use capabilities for those. */ - CCD_FLAG_TEST_LAB = (1 << 0), + CCD_FLAG_TEST_LAB = BIT(0), /* * What state were we in when the password was set? * (0=opened, 1=unlocked) */ - CCD_FLAG_PASSWORD_SET_WHEN_UNLOCKED = (1 << 1), + CCD_FLAG_PASSWORD_SET_WHEN_UNLOCKED = BIT(1), /* * Factory mode state */ - CCD_FLAG_FACTORY_MODE_ENABLED = (1 << 2), + CCD_FLAG_FACTORY_MODE_ENABLED = BIT(2), /* (flags in the middle are unused) */ /* Flags that can be set via ccd_set_flags(); fill from top down */ /* Override write protect at boot */ - CCD_FLAG_OVERRIDE_WP_AT_BOOT = (1 << 22), + CCD_FLAG_OVERRIDE_WP_AT_BOOT = BIT(22), /* * If overriding WP at boot, set it to what value * (0=disabled, 1=enabled) */ - CCD_FLAG_OVERRIDE_WP_STATE_ENABLED = (1 << 23), + CCD_FLAG_OVERRIDE_WP_STATE_ENABLED = BIT(23), }; /* Capabilities */ @@ -221,10 +221,10 @@ struct ccd_info_response { enum ccd_indicator_bits { /* has_password? */ - CCD_INDICATOR_BIT_HAS_PASSWORD = (1 << 0), + CCD_INDICATOR_BIT_HAS_PASSWORD = BIT(0), /* Are CCD capabilities in CCD_CAP_STATE_DEFAULT */ - CCD_INDICATOR_BIT_ALL_CAPS_DEFAULT = (1 << 1), + CCD_INDICATOR_BIT_ALL_CAPS_DEFAULT = BIT(1), }; /** @@ -295,16 +295,16 @@ int ccd_get_factory_mode(void); /* Flags for ccd_reset_config() */ enum ccd_reset_config_flags { /* Also reset test lab flag */ - CCD_RESET_TEST_LAB = (1 << 0), + CCD_RESET_TEST_LAB = BIT(0), /* Only reset Always/UnlessLocked settings */ - CCD_RESET_UNLOCKED_ONLY = (1 << 1), + CCD_RESET_UNLOCKED_ONLY = BIT(1), /* * Do a factory reset to enable factory mode. Factory mode sets all ccd * capabilities to always and disables write protect */ - CCD_RESET_FACTORY = (1 << 2) + CCD_RESET_FACTORY = BIT(2) }; /** diff --git a/include/charge_state.h b/include/charge_state.h index e19a2a9ab1..1435621615 100644 --- a/include/charge_state.h +++ b/include/charge_state.h @@ -47,11 +47,11 @@ enum charge_state { /* Charge state flags */ /* Forcing idle state */ -#define CHARGE_FLAG_FORCE_IDLE (1 << 0) +#define CHARGE_FLAG_FORCE_IDLE BIT(0) /* External (AC) power is present */ -#define CHARGE_FLAG_EXTERNAL_POWER (1 << 1) +#define CHARGE_FLAG_EXTERNAL_POWER BIT(1) /* Battery is responsive */ -#define CHARGE_FLAG_BATT_RESPONSIVE (1 << 2) +#define CHARGE_FLAG_BATT_RESPONSIVE BIT(2) /* Debugging constants, in the same order as enum charge_state. This string * table was moved here to sync with enum above. diff --git a/include/charge_state_v1.h b/include/charge_state_v1.h index 8d0afe32a0..97b01608ff 100644 --- a/include/charge_state_v1.h +++ b/include/charge_state_v1.h @@ -13,16 +13,16 @@ #define CHARGER_UPDATE_PERIOD (SECOND * 10) /* Power state error flags */ -#define F_CHARGER_INIT (1 << 0) /* Charger initialization */ -#define F_CHARGER_VOLTAGE (1 << 1) /* Charger maximum output voltage */ -#define F_CHARGER_CURRENT (1 << 2) /* Charger maximum output current */ -#define F_BATTERY_VOLTAGE (1 << 3) /* Battery voltage */ -#define F_BATTERY_MODE (1 << 8) /* Battery mode */ -#define F_BATTERY_CAPACITY (1 << 9) /* Battery capacity */ -#define F_BATTERY_STATE_OF_CHARGE (1 << 10) /* State of charge, percentage */ -#define F_BATTERY_UNRESPONSIVE (1 << 11) /* Battery not responding */ -#define F_BATTERY_NOT_CONNECTED (1 << 12) /* Battery not connected */ -#define F_BATTERY_GET_PARAMS (1 << 13) /* Any battery parameter bad */ +#define F_CHARGER_INIT BIT(0) /* Charger initialization */ +#define F_CHARGER_VOLTAGE BIT(1) /* Charger maximum output voltage */ +#define F_CHARGER_CURRENT BIT(2) /* Charger maximum output current */ +#define F_BATTERY_VOLTAGE BIT(3) /* Battery voltage */ +#define F_BATTERY_MODE BIT(8) /* Battery mode */ +#define F_BATTERY_CAPACITY BIT(9) /* Battery capacity */ +#define F_BATTERY_STATE_OF_CHARGE BIT(10) /* State of charge, percentage */ +#define F_BATTERY_UNRESPONSIVE BIT(11) /* Battery not responding */ +#define F_BATTERY_NOT_CONNECTED BIT(12) /* Battery not connected */ +#define F_BATTERY_GET_PARAMS BIT(13) /* Any battery parameter bad */ #define F_BATTERY_MASK (F_BATTERY_VOLTAGE | \ F_BATTERY_MODE | \ diff --git a/include/chipset.h b/include/chipset.h index 8e834680e7..77695c8303 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -80,7 +80,7 @@ enum chipset_reset_reason { * Hard shutdowns are logged on the same path as resets. */ enum chipset_shutdown_reason { - CHIPSET_SHUTDOWN_BEGIN = 1 << 15, + CHIPSET_SHUTDOWN_BEGIN = BIT(15), CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, /* Forcing a shutdown as part of EC initialization */ CHIPSET_SHUTDOWN_INIT, diff --git a/include/clock.h b/include/clock.h index 7702ca85eb..e794d65206 100644 --- a/include/clock.h +++ b/include/clock.h @@ -71,9 +71,9 @@ enum bus_type { void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles); /* Clock gate control modes for clock_enable_peripheral() */ -#define CGC_MODE_RUN (1 << 0) -#define CGC_MODE_SLEEP (1 << 1) -#define CGC_MODE_DSLEEP (1 << 2) +#define CGC_MODE_RUN BIT(0) +#define CGC_MODE_SLEEP BIT(1) +#define CGC_MODE_DSLEEP BIT(2) #define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP) /** diff --git a/include/ec_commands.h b/include/ec_commands.h index dca16805d1..eb0e05afd5 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -2651,7 +2651,7 @@ struct ec_params_motion_sense { /* * Scale for calibration: * By default scale is 1, it is encoded on 16bits: - * 1 = BIT(1)5 + * 1 = BIT(15) * ~2 = 0xFFFF * ~0 = 0. */ diff --git a/include/extension.h b/include/extension.h index b984c583b0..5ce0410f57 100644 --- a/include/extension.h +++ b/include/extension.h @@ -19,7 +19,7 @@ enum vendor_cmd_flags { * command endpoint or the console). If this flag is not present, * the command is coming from the AP. */ - VENDOR_CMD_FROM_USB = (1 << 0), + VENDOR_CMD_FROM_USB = BIT(0), }; /* Parameters for vendor commands */ diff --git a/include/fan.h b/include/fan.h index 2facf83d9f..a92d35fccb 100644 --- a/include/fan.h +++ b/include/fan.h @@ -33,9 +33,9 @@ struct fan_t { /* Values for .flags field */ /* Enable automatic RPM control using tach input */ -#define FAN_USE_RPM_MODE (1 << 0) +#define FAN_USE_RPM_MODE BIT(0) /* Require a higher duty cycle to start up than to keep running */ -#define FAN_USE_FAST_START (1 << 1) +#define FAN_USE_FAST_START BIT(1) /* The list of fans is instantiated in board.c. */ extern struct fan_t fans[]; diff --git a/include/gpio.h b/include/gpio.h index 1c80f7e32d..f01cd5147e 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -12,29 +12,29 @@ /* Flag definitions for gpio_info and gpio_alt_func */ /* The following are valid for both gpio_info and gpio_alt_func: */ -#define GPIO_OPEN_DRAIN (1 << 0) /* Output type is open-drain */ -#define GPIO_PULL_UP (1 << 1) /* Enable on-chip pullup */ -#define GPIO_PULL_DOWN (1 << 2) /* Enable on-chip pulldown */ +#define GPIO_OPEN_DRAIN BIT(0) /* Output type is open-drain */ +#define GPIO_PULL_UP BIT(1) /* Enable on-chip pullup */ +#define GPIO_PULL_DOWN BIT(2) /* Enable on-chip pulldown */ /* The following are valid for gpio_alt_func only */ -#define GPIO_ANALOG (1 << 3) /* Set pin to analog-mode */ +#define GPIO_ANALOG BIT(3) /* Set pin to analog-mode */ /* The following are valid for gpio_info only */ -#define GPIO_INPUT (1 << 4) /* Input */ -#define GPIO_OUTPUT (1 << 5) /* Output */ -#define GPIO_LOW (1 << 6) /* If GPIO_OUTPUT, set level low */ -#define GPIO_HIGH (1 << 7) /* If GPIO_OUTPUT, set level high */ -#define GPIO_INT_F_RISING (1 << 8) /* Interrupt on rising edge */ -#define GPIO_INT_F_FALLING (1 << 9) /* Interrupt on falling edge */ -#define GPIO_INT_F_LOW (1 << 11) /* Interrupt on low level */ -#define GPIO_INT_F_HIGH (1 << 12) /* Interrupt on high level */ -#define GPIO_DEFAULT (1 << 13) /* Don't set up on boot */ -#define GPIO_INT_DSLEEP (1 << 14) /* Interrupt in deep sleep */ -#define GPIO_INT_SHARED (1 << 15) /* Shared among multiple pins */ -#define GPIO_SEL_1P8V (1 << 16) /* Support 1.8v */ -#define GPIO_ALTERNATE (1 << 17) /* GPIO used for alternate function. */ -#define GPIO_LOCKED (1 << 18) /* Lock GPIO output and configuration */ -#define GPIO_HIB_WAKE_HIGH (1 << 19) /* Hibernate wake on high level */ +#define GPIO_INPUT BIT(4) /* Input */ +#define GPIO_OUTPUT BIT(5) /* Output */ +#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */ +#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */ +#define GPIO_INT_F_RISING BIT(8) /* Interrupt on rising edge */ +#define GPIO_INT_F_FALLING BIT(9) /* Interrupt on falling edge */ +#define GPIO_INT_F_LOW BIT(11) /* Interrupt on low level */ +#define GPIO_INT_F_HIGH BIT(12) /* Interrupt on high level */ +#define GPIO_DEFAULT BIT(13) /* Don't set up on boot */ +#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */ +#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */ +#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */ +#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */ +#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */ +#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ #ifdef CONFIG_GPIO_POWER_DOWN -#define GPIO_POWER_DOWN (1 << 20) /* Pin and pad is powered off */ +#define GPIO_POWER_DOWN BIT(20) /* Pin and pad is powered off */ #endif /* Common flag combinations */ diff --git a/include/i2c.h b/include/i2c.h index 66e2e82029..a43a2223d3 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -84,8 +84,8 @@ extern const int i2c_test_dev_used; #endif /* Flags for i2c_xfer_unlocked() */ -#define I2C_XFER_START (1 << 0) /* Start smbus session from idle state */ -#define I2C_XFER_STOP (1 << 1) /* Terminate smbus session with stop bit */ +#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */ +#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */ #define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */ /** @@ -115,8 +115,8 @@ int i2c_xfer_unlocked(int port, int slave_addr, const uint8_t *out, int out_size, uint8_t *in, int in_size, int flags); -#define I2C_LINE_SCL_HIGH (1 << 0) -#define I2C_LINE_SDA_HIGH (1 << 1) +#define I2C_LINE_SCL_HIGH BIT(0) +#define I2C_LINE_SDA_HIGH BIT(1) #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH) /** diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h index eecdafc476..8844cd658d 100644 --- a/include/i8042_protocol.h +++ b/include/i8042_protocol.h @@ -80,11 +80,11 @@ #define I8042_RET_ERR 0xff /* port 64 - command byte bits */ -#define I8042_XLATE (1 << 6) -#define I8042_AUX_DIS (1 << 5) -#define I8042_KBD_DIS (1 << 4) -#define I8042_SYS_FLAG (1 << 2) -#define I8042_ENIRQ12 (1 << 1) -#define I8042_ENIRQ1 (1 << 0) +#define I8042_XLATE BIT(6) +#define I8042_AUX_DIS BIT(5) +#define I8042_KBD_DIS BIT(4) +#define I8042_SYS_FLAG BIT(2) +#define I8042_ENIRQ12 BIT(1) +#define I8042_ENIRQ1 BIT(0) #endif /* __CROS_EC_I8042_PROTOCOL_H */ diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h index 9d1b506f9d..814e4d954c 100644 --- a/include/keyboard_scan.h +++ b/include/keyboard_scan.h @@ -52,9 +52,9 @@ extern struct keyboard_scan_config keyscan_config; enum boot_key { /* No keys other than keyboard-controlled reset keys */ BOOT_KEY_NONE = 0, - BOOT_KEY_ESC = (1 << 0), - BOOT_KEY_DOWN_ARROW = (1 << 1), - BOOT_KEY_LEFT_SHIFT = (1 << 2), + BOOT_KEY_ESC = BIT(0), + BOOT_KEY_DOWN_ARROW = BIT(1), + BOOT_KEY_LEFT_SHIFT = BIT(2), }; #if defined(HAS_TASK_KEYSCAN) && defined(CONFIG_KEYBOARD_BOOT_KEYS) diff --git a/include/motion_sense.h b/include/motion_sense.h index 0e6f7aa342..65512c733b 100644 --- a/include/motion_sense.h +++ b/include/motion_sense.h @@ -70,7 +70,7 @@ enum sensor_config { 1 << (TASK_EVENT_MOTION_FIRST_SW_EVENT + (_activity_id)))) -#define ROUND_UP_FLAG (1 << 31) +#define ROUND_UP_FLAG BIT(31) #define BASE_ODR(_odr) ((_odr) & ~ROUND_UP_FLAG) #define BASE_RANGE(_range) ((_range) & ~ROUND_UP_FLAG) diff --git a/include/panic.h b/include/panic.h index aeaa8f8024..45fc31583d 100644 --- a/include/panic.h +++ b/include/panic.h @@ -99,13 +99,13 @@ enum panic_arch { /* Flags for panic_data.flags */ /* panic_data.frame is valid */ -#define PANIC_DATA_FLAG_FRAME_VALID (1 << 0) +#define PANIC_DATA_FLAG_FRAME_VALID BIT(0) /* Already printed at console */ -#define PANIC_DATA_FLAG_OLD_CONSOLE (1 << 1) +#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1) /* Already returned via host command */ -#define PANIC_DATA_FLAG_OLD_HOSTCMD (1 << 2) +#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2) /* Already reported via host event */ -#define PANIC_DATA_FLAG_OLD_HOSTEVENT (1 << 3) +#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3) /** * Write a string to the panic reporting device diff --git a/include/power.h b/include/power.h index 5d506a7646..3bf598b182 100644 --- a/include/power.h +++ b/include/power.h @@ -51,12 +51,12 @@ enum power_state { * +-----------------+------------------------------------+ */ -#define POWER_SIGNAL_ACTIVE_STATE (1 << 0) +#define POWER_SIGNAL_ACTIVE_STATE BIT(0) #define POWER_SIGNAL_ACTIVE_LOW (0 << 0) -#define POWER_SIGNAL_ACTIVE_HIGH (1 << 0) +#define POWER_SIGNAL_ACTIVE_HIGH BIT(0) -#define POWER_SIGNAL_INTR_STATE (1 << 1) -#define POWER_SIGNAL_DISABLE_AT_BOOT (1 << 1) +#define POWER_SIGNAL_INTR_STATE BIT(1) +#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1) /* Information on an power signal */ struct power_signal_info { diff --git a/include/pwm.h b/include/pwm.h index 15413c537c..8c0c248e75 100644 --- a/include/pwm.h +++ b/include/pwm.h @@ -45,28 +45,28 @@ int pwm_get_duty(enum pwm_channel ch); /** * PWM output signal is inverted, so 100% duty means always low */ -#define PWM_CONFIG_ACTIVE_LOW (1 << 0) +#define PWM_CONFIG_ACTIVE_LOW BIT(0) /** * PWM channel has a fan controller with a tach input and can auto-adjust * its duty cycle to produce a given fan RPM. */ -#define PWM_CONFIG_HAS_RPM_MODE (1 << 1) +#define PWM_CONFIG_HAS_RPM_MODE BIT(1) /** * PWM clock select alternate source. The actual clock and alternate * source are chip dependent. */ -#define PWM_CONFIG_ALT_CLOCK (1 << 2) +#define PWM_CONFIG_ALT_CLOCK BIT(2) /** * PWM channel has a complementary output signal which should be enabled in * addition to the primary output. */ -#define PWM_CONFIG_COMPLEMENTARY_OUTPUT (1 << 3) +#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3) /** * PWM channel must stay active in low-power idle, if enabled. */ -#define PWM_CONFIG_DSLEEP (1 << 4) +#define PWM_CONFIG_DSLEEP BIT(4) /** * PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.) */ -#define PWM_CONFIG_OPEN_DRAIN (1 << 5) +#define PWM_CONFIG_OPEN_DRAIN BIT(5) #endif /* __CROS_EC_PWM_H */ diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h index 2d564e6b50..a0ffefc721 100644 --- a/include/spi_flash_reg.h +++ b/include/spi_flash_reg.h @@ -15,21 +15,21 @@ * Common register bits for SPI flash. All registers / bits may not be valid * for all parts. */ -#define SPI_FLASH_SR2_SUS (1 << 7) -#define SPI_FLASH_SR2_CMP (1 << 6) -#define SPI_FLASH_SR2_LB3 (1 << 5) -#define SPI_FLASH_SR2_LB2 (1 << 4) -#define SPI_FLASH_SR2_LB1 (1 << 3) -#define SPI_FLASH_SR2_QE (1 << 1) -#define SPI_FLASH_SR2_SRP1 (1 << 0) -#define SPI_FLASH_SR1_SRP0 (1 << 7) -#define SPI_FLASH_SR1_SEC (1 << 6) -#define SPI_FLASH_SR1_TB (1 << 5) -#define SPI_FLASH_SR1_BP2 (1 << 4) -#define SPI_FLASH_SR1_BP1 (1 << 3) -#define SPI_FLASH_SR1_BP0 (1 << 2) -#define SPI_FLASH_SR1_WEL (1 << 1) -#define SPI_FLASH_SR1_BUSY (1 << 0) +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* SR2 register existence based upon chip */ #ifdef CONFIG_SPI_FLASH_W25X40 diff --git a/include/spi_nor.h b/include/spi_nor.h index 07be853520..4bf8d853f2 100644 --- a/include/spi_nor.h +++ b/include/spi_nor.h @@ -73,8 +73,8 @@ extern const unsigned int spi_nor_devices_used; #define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ /* Flags for SPI_NOR_OPCODE_READ_STATUS */ -#define SPI_NOR_STATUS_REGISTER_WIP (1 << 0) /* Write in progres */ -#define SPI_NOR_STATUS_REGISTER_WEL (1 << 1) /* Write enabled latch */ +#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ +#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ /* If needed in the future this driver can be extended to discover SFDP * advertised erase sizes and opcodes for SFDP v1.0+. */ diff --git a/include/system.h b/include/system.h index f1c2d33cbf..0411ab71eb 100644 --- a/include/system.h +++ b/include/system.h @@ -15,26 +15,26 @@ #include "timer.h" /* Reset causes */ -#define RESET_FLAG_OTHER (1 << 0) /* Other known reason */ -#define RESET_FLAG_RESET_PIN (1 << 1) /* Reset pin asserted */ -#define RESET_FLAG_BROWNOUT (1 << 2) /* Brownout */ -#define RESET_FLAG_POWER_ON (1 << 3) /* Power-on reset */ -#define RESET_FLAG_WATCHDOG (1 << 4) /* Watchdog timer reset */ -#define RESET_FLAG_SOFT (1 << 5) /* Soft reset trigger by core */ -#define RESET_FLAG_HIBERNATE (1 << 6) /* Wake from hibernate */ -#define RESET_FLAG_RTC_ALARM (1 << 7) /* RTC alarm wake */ -#define RESET_FLAG_WAKE_PIN (1 << 8) /* Wake pin triggered wake */ -#define RESET_FLAG_LOW_BATTERY (1 << 9) /* Low battery triggered wake */ -#define RESET_FLAG_SYSJUMP (1 << 10) /* Jumped directly to this image */ -#define RESET_FLAG_HARD (1 << 11) /* Hard reset from software */ -#define RESET_FLAG_AP_OFF (1 << 12) /* Do not power on AP */ -#define RESET_FLAG_PRESERVED (1 << 13) /* Some reset flags preserved from +#define RESET_FLAG_OTHER BIT(0) /* Other known reason */ +#define RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ +#define RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ +#define RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ +#define RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ +#define RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ +#define RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ +#define RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ +#define RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ +#define RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ +#define RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ +#define RESET_FLAG_HARD BIT(11) /* Hard reset from software */ +#define RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ +#define RESET_FLAG_PRESERVED BIT(13) /* Some reset flags preserved from * previous boot */ -#define RESET_FLAG_USB_RESUME (1 << 14) /* USB resume triggered wake */ -#define RESET_FLAG_RDD (1 << 15) /* USB Type-C debug cable */ -#define RESET_FLAG_RBOX (1 << 16) /* Fixed Reset Functionality */ -#define RESET_FLAG_SECURITY (1 << 17) /* Security threat */ -#define RESET_FLAG_AP_WATCHDOG (1 << 18) /* AP experienced a watchdog reset */ +#define RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ +#define RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ +#define RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ +#define RESET_FLAG_SECURITY BIT(17) /* Security threat */ +#define RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */ /* Per chip implementation to save/read raw RESET_FLAG_ flags. */ void chip_save_reset_flags(int flags); @@ -257,29 +257,29 @@ const char *system_get_build_info(void); * Hard reset. Cuts power to the entire system. If not present, does a soft * reset which just resets the core and on-chip peripherals. */ -#define SYSTEM_RESET_HARD (1 << 0) +#define SYSTEM_RESET_HARD BIT(0) /* * Preserve existing reset flags. Used by flash pre-init when it discovers it * needs to do a hard reset to clear write protect registers. */ -#define SYSTEM_RESET_PRESERVE_FLAGS (1 << 1) +#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1) /* * Leave AP off on next reboot, instead of powering it on to do EC software * sync. */ -#define SYSTEM_RESET_LEAVE_AP_OFF (1 << 2) +#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2) /* * Indicate that this was a manually triggered reset. */ -#define SYSTEM_RESET_MANUALLY_TRIGGERED (1 << 3) +#define SYSTEM_RESET_MANUALLY_TRIGGERED BIT(3) /* * Wait for reset pin to be driven, rather that resetting ourselves. */ -#define SYSTEM_RESET_WAIT_EXT (1 << 4) +#define SYSTEM_RESET_WAIT_EXT BIT(4) /* * Indicate that this reset was triggered by an AP watchdog */ -#define SYSTEM_RESET_AP_WATCHDOG (1 << 5) +#define SYSTEM_RESET_AP_WATCHDOG BIT(5) /** * Reset the system. @@ -423,32 +423,32 @@ enum { /* * Sleep masks to prevent going in to deep sleep. */ - SLEEP_MASK_AP_RUN = (1 << 0), /* the main CPU is running */ - SLEEP_MASK_UART = (1 << 1), /* UART communication ongoing */ - SLEEP_MASK_I2C_MASTER = (1 << 2), /* I2C master communication ongoing */ - SLEEP_MASK_CHARGING = (1 << 3), /* Charging loop ongoing */ - SLEEP_MASK_USB_PWR = (1 << 4), /* USB power loop ongoing */ - SLEEP_MASK_USB_PD = (1 << 5), /* USB PD device connected */ - SLEEP_MASK_SPI = (1 << 6), /* SPI communications ongoing */ - SLEEP_MASK_I2C_SLAVE = (1 << 7), /* I2C slave communication ongoing */ - SLEEP_MASK_FAN = (1 << 8), /* Fan control loop ongoing */ - SLEEP_MASK_USB_DEVICE = (1 << 9), /* Generic USB device in use */ - SLEEP_MASK_PWM = (1 << 10), /* PWM output is enabled */ - SLEEP_MASK_PHYSICAL_PRESENCE = (1 << 11), /* Physical presence + SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */ + SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */ + SLEEP_MASK_I2C_MASTER = BIT(2), /* I2C master communication ongoing */ + SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */ + SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */ + SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */ + SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */ + SLEEP_MASK_I2C_SLAVE = BIT(7), /* I2C slave communication ongoing */ + SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */ + SLEEP_MASK_USB_DEVICE = BIT(9), /* Generic USB device in use */ + SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */ + SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence * detection ongoing */ - SLEEP_MASK_PLL = (1 << 12), /* High-speed PLL in-use */ - SLEEP_MASK_ADC = (1 << 13), /* ADC conversion ongoing */ - SLEEP_MASK_EMMC = (1 << 14), /* eMMC emulation ongoing */ - SLEEP_MASK_FORCE_NO_DSLEEP = (1 << 15), /* Force disable. */ + SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */ + SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */ + SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */ + SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */ /* * Sleep masks to prevent using slow speed clock in deep sleep. */ - SLEEP_MASK_JTAG = (1 << 16), /* JTAG is in use. */ - SLEEP_MASK_CONSOLE = (1 << 17), /* Console is in use. */ + SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */ + SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */ - SLEEP_MASK_FORCE_NO_LOW_SPEED = (1 << 31) /* Force disable. */ + SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */ }; /* diff --git a/include/task.h b/include/task.h index 014531721c..74bb7efe64 100644 --- a/include/task.h +++ b/include/task.h @@ -16,10 +16,10 @@ /* Tasks may use the bits in TASK_EVENT_CUSTOM for their own events */ #define TASK_EVENT_CUSTOM(x) (x & 0x0003ffff) -#define TASK_EVENT_PD_AWAKE (1 << 18) +#define TASK_EVENT_PD_AWAKE BIT(18) /* npcx peci event */ -#define TASK_EVENT_PECI_DONE (1 << 19) +#define TASK_EVENT_PECI_DONE BIT(19) /* I2C tx/rx interrupt handler completion event. */ #ifdef CHIP_STM32 @@ -33,19 +33,19 @@ #endif #endif #else -#define TASK_EVENT_I2C_IDLE (1 << 20) +#define TASK_EVENT_I2C_IDLE BIT(20) #endif /* DMA transmit complete event */ -#define TASK_EVENT_DMA_TC (1 << 26) +#define TASK_EVENT_DMA_TC BIT(26) /* ADC interrupt handler event */ -#define TASK_EVENT_ADC_DONE (1 << 27) +#define TASK_EVENT_ADC_DONE BIT(27) /* task_reset() that was requested has been completed */ -#define TASK_EVENT_RESET_DONE (1 << 28) +#define TASK_EVENT_RESET_DONE BIT(28) /* task_wake() called on task */ -#define TASK_EVENT_WAKE (1 << 29) +#define TASK_EVENT_WAKE BIT(29) /* Mutex unlocking */ -#define TASK_EVENT_MUTEX (1 << 30) +#define TASK_EVENT_MUTEX BIT(30) /* * Timer expired. For example, task_wait_event() timed out before receiving * another event. diff --git a/include/tpm_vendor_cmds.h b/include/tpm_vendor_cmds.h index c17929f96d..9c344d6f55 100644 --- a/include/tpm_vendor_cmds.h +++ b/include/tpm_vendor_cmds.h @@ -206,7 +206,7 @@ enum vendor_cc_spi_hash_request_subcmd { enum vendor_cc_spi_hash_request_flags { /* EC uses gang programmer mode */ - SPI_HASH_FLAG_EC_GANG = (1 << 0), + SPI_HASH_FLAG_EC_GANG = BIT(0), }; /* Structure for VENDOR_CC_SPI_HASH request which follows tpm_header */ @@ -224,10 +224,10 @@ struct vendor_cc_spi_hash_request { /* * Subcommand code, used to set write protect. */ -#define WPV_UPDATE (1 << 0) -#define WPV_ENABLE (1 << 1) -#define WPV_FORCE (1 << 2) -#define WPV_ATBOOT_SET (1 << 3) -#define WPV_ATBOOT_ENABLE (1 << 4) +#define WPV_UPDATE BIT(0) +#define WPV_ENABLE BIT(1) +#define WPV_FORCE BIT(2) +#define WPV_ATBOOT_SET BIT(3) +#define WPV_ATBOOT_ENABLE BIT(4) #endif /* __INCLUDE_TPM_VENDOR_CMDS_H */ diff --git a/include/usb_descriptor.h b/include/usb_descriptor.h index aadb5dc80a..f4b3014ecf 100644 --- a/include/usb_descriptor.h +++ b/include/usb_descriptor.h @@ -232,8 +232,8 @@ struct usb_endpoint_descriptor { /* Standard requests for bRequest field in a SETUP packet. */ #define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_GET_STATUS_SELF_POWERED (1 << 0) -#define USB_REQ_GET_STATUS_REMOTE_WAKEUP (1 << 1) +#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0) +#define USB_REQ_GET_STATUS_REMOTE_WAKEUP BIT(1) #define USB_REQ_CLEAR_FEATURE 0x01 #define USB_REQ_SET_FEATURE 0x03 #define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000 diff --git a/include/usb_mux.h b/include/usb_mux.h index e483954733..808c767465 100644 --- a/include/usb_mux.h +++ b/include/usb_mux.h @@ -87,7 +87,7 @@ struct usb_mux_driver { }; /* Flags used for usb_mux.flags */ -#define USB_MUX_FLAG_NOT_TCPC (1 << 0) /* TCPC/MUX device used only as MUX */ +#define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */ /* Describes a USB mux present in the system */ struct usb_mux { diff --git a/include/usb_pd.h b/include/usb_pd.h index 435b2c6e3f..406dd93ce1 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -74,16 +74,16 @@ enum pd_rx_errors { * above by examining bits <29:28> to determine the additional PDO function. */ #define PDO_TYPE_FIXED (0 << 30) -#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_BATTERY BIT(30) #define PDO_TYPE_VARIABLE (2 << 30) #define PDO_TYPE_AUGMENTED (3 << 30) #define PDO_TYPE_MASK (3 << 30) -#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Dual role device */ -#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported */ -#define PDO_FIXED_EXTERNAL (1 << 27) /* Externally powered */ -#define PDO_FIXED_COMM_CAP (1 << 26) /* USB Communications Capable */ -#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap command supported */ +#define PDO_FIXED_DUAL_ROLE BIT(29) /* Dual role device */ +#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */ +#define PDO_FIXED_EXTERNAL BIT(27) /* Externally powered */ +#define PDO_FIXED_COMM_CAP BIT(26) /* USB Communications Capable */ +#define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap command supported */ #define PDO_FIXED_PEAK_CURR () /* [21..20] Peak current */ #define PDO_FIXED_VOLT(mv) (((mv)/50) << 10) /* Voltage in 50mV units */ #define PDO_FIXED_CURR(ma) (((ma)/10) << 0) /* Max current in 10mA units */ @@ -114,10 +114,10 @@ enum pd_rx_errors { /* RDO : Request Data Object */ #define RDO_OBJ_POS(n) (((n) & 0x7) << 28) #define RDO_POS(rdo) (((rdo) >> 28) & 0x7) -#define RDO_GIVE_BACK (1 << 27) -#define RDO_CAP_MISMATCH (1 << 26) -#define RDO_COMM_CAP (1 << 25) -#define RDO_NO_SUSPEND (1 << 24) +#define RDO_GIVE_BACK BIT(27) +#define RDO_CAP_MISMATCH BIT(26) +#define RDO_COMM_CAP BIT(25) +#define RDO_NO_SUSPEND BIT(24) #define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10) #define RDO_FIXED_VAR_MAX_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) @@ -137,7 +137,7 @@ enum pd_rx_errors { /* BDO : BIST Data Object */ #define BDO_MODE_RECV (0 << 28) -#define BDO_MODE_TRANSMIT (1 << 28) +#define BDO_MODE_TRANSMIT BIT(28) #define BDO_MODE_COUNTERS (2 << 28) #define BDO_MODE_CARRIER0 (3 << 28) #define BDO_MODE_CARRIER1 (4 << 28) @@ -252,8 +252,8 @@ enum hpd_event { }; /* DisplayPort flags */ -#define DP_FLAGS_DP_ON (1 << 0) /* Display port mode is on */ -#define DP_FLAGS_HPD_HI_PENDING (1 << 1) /* Pending HPD_HI */ +#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */ +#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */ /* supported alternate modes */ enum pd_alternate_modes { @@ -306,7 +306,7 @@ struct pd_policy { ((type) << 15) | \ ((custom) & 0x7FFF)) -#define VDO_SVDM_TYPE (1 << 15) +#define VDO_SVDM_TYPE BIT(15) #define VDO_SVDM_VERS(x) (x << 13) #define VDO_OPOS(x) (x << 8) #define VDO_CMDT(x) (x << 6) @@ -321,7 +321,7 @@ struct pd_policy { /* reserved for SVDM ... for Google UVDM */ #define VDO_SRC_INITIATOR (0 << 5) -#define VDO_SRC_RESPONDER (1 << 5) +#define VDO_SRC_RESPONDER BIT(5) #define CMD_DISCOVER_IDENT 1 #define CMD_DISCOVER_SVID 2 @@ -698,23 +698,23 @@ enum pd_states { PD_STATE_COUNT, }; -#define PD_FLAGS_PING_ENABLED (1 << 0) /* SRC_READY pings enabled */ -#define PD_FLAGS_PARTNER_DR_POWER (1 << 1) /* port partner is dualrole power */ -#define PD_FLAGS_PARTNER_DR_DATA (1 << 2) /* port partner is dualrole data */ -#define PD_FLAGS_CHECK_IDENTITY (1 << 3) /* discover identity in READY */ -#define PD_FLAGS_SNK_CAP_RECVD (1 << 4) /* sink capabilities received */ -#define PD_FLAGS_TCPC_DRP_TOGGLE (1 << 5) /* TCPC-controlled DRP toggling */ -#define PD_FLAGS_EXPLICIT_CONTRACT (1 << 6) /* explicit pwr contract in place */ -#define PD_FLAGS_VBUS_NEVER_LOW (1 << 7) /* VBUS input has never been low */ -#define PD_FLAGS_PREVIOUS_PD_CONN (1 << 8) /* previously PD connected */ -#define PD_FLAGS_CHECK_PR_ROLE (1 << 9) /* check power role in READY */ -#define PD_FLAGS_CHECK_DR_ROLE (1 << 10)/* check data role in READY */ -#define PD_FLAGS_PARTNER_EXTPOWER (1 << 11)/* port partner has external pwr */ -#define PD_FLAGS_VCONN_ON (1 << 12)/* vconn is being sourced */ -#define PD_FLAGS_TRY_SRC (1 << 13)/* Try.SRC states are active */ -#define PD_FLAGS_PARTNER_USB_COMM (1 << 14)/* port partner is USB comms */ -#define PD_FLAGS_UPDATE_SRC_CAPS (1 << 15)/* send new source capabilities */ -#define PD_FLAGS_TS_DTS_PARTNER (1 << 16)/* partner has rp/rp or rd/rd */ +#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */ +#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */ +#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */ +#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */ +#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */ +#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */ +#define PD_FLAGS_EXPLICIT_CONTRACT BIT(6) /* explicit pwr contract in place */ +#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */ +#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */ +#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */ +#define PD_FLAGS_CHECK_DR_ROLE BIT(10)/* check data role in READY */ +#define PD_FLAGS_PARTNER_EXTPOWER BIT(11)/* port partner has external pwr */ +#define PD_FLAGS_VCONN_ON BIT(12)/* vconn is being sourced */ +#define PD_FLAGS_TRY_SRC BIT(13)/* Try.SRC states are active */ +#define PD_FLAGS_PARTNER_USB_COMM BIT(14)/* port partner is USB comms */ +#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15)/* send new source capabilities */ +#define PD_FLAGS_TS_DTS_PARTNER BIT(16)/* partner has rp/rp or rd/rd */ /* * These PD_FLAGS_LPM* flags track the software state (PD_LPM_FLAGS_REQUESTED) * and hardware state (PD_LPM_FLAGS_ENGAGED) of the TCPC low power mode. @@ -722,9 +722,9 @@ enum pd_states { * low power (when PD_LPM_FLAGS_ENGAGED is changing). */ #ifdef CONFIG_USB_PD_TCPC_LOW_POWER -#define PD_FLAGS_LPM_REQUESTED (1 << 17)/* Tracks SW LPM state */ -#define PD_FLAGS_LPM_ENGAGED (1 << 18)/* Tracks HW LPM state */ -#define PD_FLAGS_LPM_TRANSITION (1 << 19)/* Tracks HW LPM transition */ +#define PD_FLAGS_LPM_REQUESTED BIT(17)/* Tracks SW LPM state */ +#define PD_FLAGS_LPM_ENGAGED BIT(18)/* Tracks HW LPM state */ +#define PD_FLAGS_LPM_TRANSITION BIT(19)/* Tracks HW LPM transition */ #endif /* Flags to clear on a disconnect */ #define PD_FLAGS_RESET_ON_DISCONNECT_MASK (PD_FLAGS_PARTNER_DR_POWER | \ @@ -744,9 +744,9 @@ enum pd_states { PD_FLAGS_TS_DTS_PARTNER) /* Per-port battery backed RAM flags */ -#define PD_BBRMFLG_EXPLICIT_CONTRACT (1 << 0) -#define PD_BBRMFLG_POWER_ROLE (1 << 1) -#define PD_BBRMFLG_DATA_ROLE (1 << 2) +#define PD_BBRMFLG_EXPLICIT_CONTRACT BIT(0) +#define PD_BBRMFLG_POWER_ROLE BIT(1) +#define PD_BBRMFLG_DATA_ROLE BIT(2) enum pd_cc_states { PD_CC_NONE, @@ -830,10 +830,10 @@ enum pd_ctrl_msg_type { /* Battery Status Data Object fields for REV 3.0 */ #define BSDO_CAP_UNKNOWN 0xffff #define BSDO_CAP(n) (((n) & 0xffff) << 16) -#define BSDO_INVALID (1 << 8) -#define BSDO_PRESENT (1 << 9) -#define BSDO_DISCHARGING (1 << 10) -#define BSDO_IDLE (1 << 11) +#define BSDO_INVALID BIT(8) +#define BSDO_PRESENT BIT(9) +#define BSDO_DISCHARGING BIT(10) +#define BSDO_IDLE BIT(11) /* Get Battery Cap Message fields for REV 3.0 */ #define BATT_CAP_REF(n) (((n) >> 16) & 0xff) @@ -918,7 +918,7 @@ enum pd_data_msg_type { /* build extended message header */ /* All extended messages are chunked, so set bit 15 */ #define PD_EXT_HEADER(cnum, rchk, dsize) \ - ((1 << 15) | ((cnum) << 11) | \ + (BIT(15) | ((cnum) << 11) | \ ((rchk) << 10) | (dsize)) /* build message header */ @@ -1213,7 +1213,7 @@ void pd_update_contract(int port); /* Encode DTS status of port partner in current limit parameter */ typedef uint32_t typec_current_t; -#define TYPEC_CURRENT_DTS_MASK (1 << 31) +#define TYPEC_CURRENT_DTS_MASK BIT(31) #define TYPEC_CURRENT_ILIM_MASK (~TYPEC_CURRENT_DTS_MASK) /** diff --git a/test/motion_lid.c b/test/motion_lid.c index 3282812e86..c9c7570232 100644 --- a/test/motion_lid.c +++ b/test/motion_lid.c @@ -70,7 +70,7 @@ static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate, const int rnd) { - test_data_rate[s - motion_sensors] = rate | (rnd ? ROUND_UP_FLAG : 0); + test_data_rate[s - motion_sensors] = rate; return EC_SUCCESS; } @@ -186,7 +186,7 @@ static int test_lid_angle(void) hook_notify(HOOK_CHIPSET_RESUME); msleep(1000); TEST_ASSERT(sensor_active == SENSOR_ACTIVE_S0); - TEST_ASSERT(accel_get_data_rate(lid) == (119000 | ROUND_UP_FLAG)); + TEST_ASSERT(accel_get_data_rate(lid) == 119000); TEST_ASSERT(motion_interval == TEST_LID_EC_RATE); /* diff --git a/util/cbi-util.c b/util/cbi-util.c index f8abb4e64a..fbf0a6068b 100644 --- a/util/cbi-util.c +++ b/util/cbi-util.c @@ -20,11 +20,11 @@ #include "cros_board_info.h" #include "crc8.h" -#define ARGS_MASK_BOARD_VERSION (1 << 0) -#define ARGS_MASK_FILENAME (1 << 1) -#define ARGS_MASK_OEM_ID (1 << 2) -#define ARGS_MASK_SIZE (1 << 3) -#define ARGS_MASK_SKU_ID (1 << 4) +#define ARGS_MASK_BOARD_VERSION BIT(0) +#define ARGS_MASK_FILENAME BIT(1) +#define ARGS_MASK_OEM_ID BIT(2) +#define ARGS_MASK_SIZE BIT(3) +#define ARGS_MASK_SKU_ID BIT(4) /* TODO: Set it by macro */ const char cmd_name[] = "cbi-util"; diff --git a/util/comm-host.h b/util/comm-host.h index 11f81b4950..0bcd5cc7af 100644 --- a/util/comm-host.h +++ b/util/comm-host.h @@ -27,10 +27,10 @@ extern void *ec_inbuf; /* Interfaces to allow for comm_init() */ enum comm_interface { - COMM_DEV = (1 << 0), - COMM_LPC = (1 << 1), - COMM_I2C = (1 << 2), - COMM_SERVO = (1 << 3), + COMM_DEV = BIT(0), + COMM_LPC = BIT(1), + COMM_I2C = BIT(2), + COMM_SERVO = BIT(3), COMM_ALL = -1 }; diff --git a/util/ec_panicinfo.c b/util/ec_panicinfo.c index 47de4b2a4c..f614770619 100644 --- a/util/ec_panicinfo.c +++ b/util/ec_panicinfo.c @@ -5,6 +5,7 @@ #include <stdint.h> #include <stdio.h> +#include "compile_time_macros.h" #include "ec_panicinfo.h" static void print_panic_reg(int regnum, const uint32_t *regs, int index) diff --git a/util/iteflash.c b/util/iteflash.c index cc275d630c..d96464ccda 100644 --- a/util/iteflash.c +++ b/util/iteflash.c @@ -20,6 +20,7 @@ #include <time.h> #include <unistd.h> +#include "compile_time_macros.h" #include "usb_if.h" /* Default FTDI device : Servo v2. */ @@ -46,8 +47,8 @@ #define FTDI_I2C_FREQ 400000 /* I2C pins on the FTDI interface */ -#define SCL_BIT (1 << 0) -#define SDA_BIT (1 << 1) +#define SCL_BIT BIT(0) +#define SDA_BIT BIT(1) /* Chip ID register value */ #define CHIP_ID 0x8380 |