diff options
| -rw-r--r-- | chip/mec1322/lpc.c | 47 | ||||
| -rw-r--r-- | chip/npcx/lpc.c | 49 | ||||
| -rw-r--r-- | include/lpc.h | 3 | ||||
| -rw-r--r-- | power/intel_x86.c | 50 |
4 files changed, 48 insertions, 101 deletions
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 3ce2717222..e5eae508ae 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -618,50 +618,3 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, EC_VER_MASK(0)); - -#ifdef CONFIG_POWER_S0IX -static void lpc_clear_host_events(void) -{ - while (lpc_query_host_event_state() != 0); -} - -/* - * In AP S0 -> S3 & S0ix transitions, - * the chipset_suspend is called. - * - * The chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON) - * is used to detect the S0ix transition. - * - * During S0ix entry, the wake mask for lid open is enabled. - * - */ -void lpc_enable_wake_mask_for_lid_open(void) -{ - if ((chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) || - chipset_in_state(CHIPSET_STATE_STANDBY)) { - uint32_t mask = 0; - - mask = ((lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE)) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)); - - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask); -} } - -/* - * In AP S0ix & S3 -> S0 transitions, - * the chipset_resume hook is called. - * - * During S0ix exit, the wake mask for lid open is disabled. - * All pending events are cleared - * - */ -void lpc_disable_wake_mask_for_lid_open(void) -{ - if ((chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) || - chipset_in_state(CHIPSET_STATE_ON)) { - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); - lpc_clear_host_events(); - } -} - -#endif diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 15aa2298d0..e8b59f12d3 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -1148,52 +1148,3 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, EC_VER_MASK(0)); - -#ifdef CONFIG_POWER_S0IX -static void lpc_clear_host_events(void) -{ - while (lpc_query_host_event_state() != 0) - ; -} - -/* - * In AP S0 -> S3 & S0ix transitions, - * the chipset_suspend is called. - * - * The chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON) - * is used to detect the S0ix transiton. - * - * During S0ix entry, the wake mask for lid open is enabled. - */ -void lpc_enable_wake_mask_for_lid_open(void) -{ - if (chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) { - uint32_t mask; - - mask = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN); - - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask); - } -} - -/* - * In AP S0ix & S3 -> S0 transitions, - * the chipset_resume hook is called. - * - * During S0ix exit, the wake mask for lid open is disabled. - * All pending events are cleared - */ -void lpc_disable_wake_mask_for_lid_open(void) -{ - if (chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) { - uint32_t mask; - - mask = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE) & - ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN); - - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask); - lpc_clear_host_events(); - } -} -#endif diff --git a/include/lpc.h b/include/lpc.h index 4408b71327..03699dab35 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -124,7 +124,4 @@ void lpc_disable_acpi_interrupts(void); /* Enable LPC ACPI interrupts */ void lpc_enable_acpi_interrupts(void); -void lpc_enable_wake_mask_for_lid_open(void); - -void lpc_disable_wake_mask_for_lid_open(void); #endif /* __CROS_EC_LPC_H */ diff --git a/power/intel_x86.c b/power/intel_x86.c index 4932d4e655..ed43017f6b 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -90,6 +90,52 @@ static enum power_state power_wait_s5_rtc_reset(void) } #endif +#ifdef CONFIG_POWER_S0IX +/* + * In AP S0 -> S3 & S0ix transitions, + * the chipset_suspend is called. + * + * The chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON) + * is used to detect the S0ix transiton. + * + * During S0ix entry, the wake mask for lid open is enabled. + */ +static void s0ix_lpc_enable_wake_mask_for_lid_open(void) +{ + if (chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) { + uint32_t mask; + + mask = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN); + + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask); + } +} + +/* + * In AP S0ix & S3 -> S0 transitions, + * the chipset_resume hook is called. + * + * During S0ix exit, the wake mask for lid open is disabled. + * All pending events are cleared + */ +static void s0ix_lpc_disable_wake_mask_for_lid_open(void) +{ + if (chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) { + uint32_t mask; + + mask = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE) & + ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN); + + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask); + + /* clear host events */ + while (lpc_query_host_event_state() != 0) + ; + } +} +#endif + void chipset_throttle_cpu(int throttle) { if (chipset_in_state(CHIPSET_STATE_ON)) @@ -285,7 +331,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state) /* call hooks before standby */ hook_notify(HOOK_CHIPSET_SUSPEND); - lpc_enable_wake_mask_for_lid_open(); + s0ix_lpc_enable_wake_mask_for_lid_open(); /* * Enable idle task deep sleep. Allow the low power idle task @@ -297,7 +343,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state) case POWER_S0ixS0: - lpc_disable_wake_mask_for_lid_open(); + s0ix_lpc_disable_wake_mask_for_lid_open(); /* Call hooks now that rails are up */ hook_notify(HOOK_CHIPSET_RESUME); |