diff options
26 files changed, 1545 insertions, 5 deletions
diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md index 3405633132..39286e130d 100644 --- a/baseboard/intelrvp/README.md +++ b/baseboard/intelrvp/README.md @@ -10,13 +10,25 @@ baseboard code is applicable to Icelake and its successors only. Following hardware features are supported on MECC header by RVP and can be validated by software by MECC. +## MECC version 0.9 features + +1. Power to MECC is provided by RVP (battery + DC Jack + Type C) +2. Power control pins for Intel SOC are added +3. Servo V2 header need to be added by MECC +4. Google H1 chip need to be added by MECC (optional for EC vendors) +5. 2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) +6. 6 Temperature sensors +7. 4 ADC +8. 4 I2C Channels +9. 1 Fan control + ## MECC version 1.0 features 1. Power to MECC is provided by RVP (battery + DC Jack + Type C) 2. Power control pins for Intel SOC are added 3. Servo V2 header need to be added by MECC 4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 4 Type-C port support (SRC/SNK/MUX/Rerimer) as Add In Card (AIC) on +5. 4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on RVP 6. Optional 2 Type-C port routed to MECC for integrated TCPC support 7. 6 I2C Channels diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 0ab8ea2bc6..8f7d22350e 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -86,15 +86,25 @@ /* USB-A config */ +/* BC1.2 config */ +#ifdef HAS_TASK_USB_CHG_P0 + #define CONFIG_CHARGE_RAMP_HW +#endif + /* Enable USB-PD REV 3.0 */ #define CONFIG_USB_PD_REV30 #define CONFIG_USB_PID 0x8086 /* USB PD config */ -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_TCPM_MUX +#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1) + #define CONFIG_USB_PD_TCPMV1 + #define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 +#else + #define CONFIG_USB_DRP_ACC_TRYSRC + #define CONFIG_USB_PD_DECODE_SOP + #define CONFIG_USB_PD_TCPMV2 + #define CONFIG_USB_PD_TCPM_MUX +#endif #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_DUAL_ROLE diff --git a/baseboard/intelrvp/bc12.c b/baseboard/intelrvp/bc12.c new file mode 100644 index 0000000000..9f212fba4e --- /dev/null +++ b/baseboard/intelrvp/bc12.c @@ -0,0 +1,28 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel BASEBOARD-RVP BC1.2 specific configuration */ + +#include "common.h" +#include "max14637.h" + +/* BC1.2 chip Configuration */ +#ifdef CONFIG_BC12_DETECT_MAX14637 +const struct max14637_config_t max14637_config[] = { + [TYPE_C_PORT_0] = { + .chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL, + .chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L, + .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, + }, +#ifdef HAS_TASK_PD_C1 + [TYPE_C_PORT_1] = { + .chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL, + .chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L, + .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, + }, +#endif /* HAS_TASK_PD_C1 */ +}; +BUILD_ASSERT(ARRAY_SIZE(max14637_config) == CONFIG_USB_PD_PORT_MAX_COUNT); +#endif /* CONFIG_BC12_DETECT_MAX14637 */ diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk index 5679d327a0..6abf8bbe0c 100644 --- a/baseboard/intelrvp/build.mk +++ b/baseboard/intelrvp/build.mk @@ -12,6 +12,8 @@ baseboard-$(CONFIG_LED_COMMON)+=led.o led_states.o ifneq ($(CONFIG_USB_POWER_DELIVERY),) baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o +baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=chg_usb_pd_mecc_0_9.o +baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=usb_pd_policy_mecc_0_9.o baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o endif @@ -21,6 +23,9 @@ baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o +#BC1.2 specific files +baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o + #Common board specific files ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \ $(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX) \ diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c new file mode 100644 index 0000000000..fa9f1e147f --- /dev/null +++ b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c @@ -0,0 +1,120 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel-RVP family-specific configuration */ + +#include "console.h" +#include "hooks.h" +#include "tcpm/tcpci.h" +#include "system.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +/* Reset PD MCU */ +void board_reset_pd_mcu(void) +{ + /* Add code if TCPC chips need a reset */ +} + +int board_vbus_source_enabled(int port) +{ + int src_en = 0; + + /* Only Type-C ports can source VBUS */ + if (is_typec_port(port)) { + src_en = gpio_get_level(tcpc_gpios[port].src.pin); + + src_en = tcpc_gpios[port].src.pin_pol ? src_en : !src_en; + } + + return src_en; +} + +void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int ilim_en; + + /* Only Type-C ports can source VBUS */ + if (is_typec_port(port)) { + /* Enable SRC ILIM if rp is MAX single source current */ + ilim_en = (rp == TYPEC_RP_3A0 && + board_vbus_source_enabled(port)); + + gpio_set_level(tcpc_gpios[port].src_ilim.pin, + tcpc_gpios[port].src_ilim.pin_pol ? + ilim_en : !ilim_en); + } +} + +void board_charging_enable(int port, int enable) +{ + gpio_set_level(tcpc_gpios[port].snk.pin, + tcpc_gpios[port].snk.pin_pol ? enable : !enable); + +} + +void board_vbus_enable(int port, int enable) +{ + gpio_set_level(tcpc_gpios[port].src.pin, + tcpc_gpios[port].src.pin_pol ? enable : !enable); +} + +int pd_snk_is_vbus_provided(int port) +{ + int vbus_intr; + +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + if (port == DEDICATED_CHARGE_PORT) + return 1; +#endif + + vbus_intr = gpio_get_level(tcpc_gpios[port].vbus.pin); + + return tcpc_gpios[port].vbus.pin_pol ? vbus_intr : !vbus_intr; +} + +void tcpc_alert_event(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (tcpc_gpios[i].vbus.pin == signal) { + schedule_deferred_pd_interrupt(i); + break; + } + } +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int i; + + /* Check which port has the ALERT line set */ + for (i = 0; i < CHARGE_PORT_COUNT; i++) { + /* No alerts for embdeded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) + continue; + + /* Add TCPC alerts if present */ + } + + return status; +} + +void board_tcpc_init(void) +{ + int i; + + /* Only reset TCPC if not sysjump */ + if (!system_jumped_late()) + board_reset_pd_mcu(); + + /* Enable TCPCx interrupt */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + gpio_enable_interrupt(tcpc_gpios[i].vbus.pin); +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c new file mode 100644 index 0000000000..6d173fd032 --- /dev/null +++ b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c @@ -0,0 +1,57 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "charge_manager.h" +#include "console.h" +#include "gpio.h" +#include "system.h" +#include "usb_mux.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +int pd_set_power_supply_ready(int port) +{ + /* Disable charging */ + board_charging_enable(port, 0); + + /* Provide VBUS */ + board_vbus_enable(port, 1); + +#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT + /* Ensure we advertise the proper available current quota */ + charge_manager_source_port(port, 1); +#endif + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; /* we are ready */ +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + board_vbus_enable(port, 0); + +#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT + /* Give back the current quota we are no longer using */ + charge_manager_source_port(port, 0); +#endif + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_check_vconn_swap(int port) +{ + /* Only allow vconn swap if PP5000 rail is enabled */ + return gpio_get_level(GPIO_EN_PP5000); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + board_set_vbus_source_current_limit(port, rp); +} diff --git a/board/jslrvp_ite/battery.c b/board/jslrvp_ite/battery.c new file mode 100644 index 0000000000..908a02843f --- /dev/null +++ b/board/jslrvp_ite/battery.c @@ -0,0 +1,77 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery_fuel_gauge.h" +#include "battery_smart.h" +#include "common.h" +#include "util.h" + +const struct board_batt_params board_battery_info[] = { + /* + * Simplo Battery (SMP-HHP-408) Information + * Fuel gauge: BQ40Z50 + */ + [BATTERY_SIMPLO_SMP_HHP_408] = { + .fuel_gauge = { + .manuf_name = "SMP-HHP-408", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .reg_addr = SB_BATTERY_STATUS, + .reg_mask = STATUS_INITIALIZED, + .disconnect_val = 0x0, + } + }, + .batt_info = { + .voltage_max = 8700, /* mV */ + .voltage_normal = 7600, + .voltage_min = 6100, + .precharge_current = 204, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = 0, + .discharging_max_c = 60, + }, + }, + /* + * Simplo Battery (SMP-CA-445) Information + * Fuel gauge: BQ30Z554 + */ + [BATTERY_SIMPLO_SMP_CA_445] = { + .fuel_gauge = { + .manuf_name = "SMP-CA-445", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .reg_addr = SB_BATTERY_STATUS, + .reg_mask = STATUS_INITIALIZED, + .disconnect_val = 0x0, + } + }, + .batt_info = { + .voltage_max = 8700, /* mV */ + .voltage_normal = 7600, + .voltage_min = 6100, + .precharge_current = 150, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -20, + .discharging_max_c = 60, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_SMP_CA_445; diff --git a/board/jslrvp_ite/board.c b/board/jslrvp_ite/board.c new file mode 100644 index 0000000000..eb654140a6 --- /dev/null +++ b/board/jslrvp_ite/board.c @@ -0,0 +1,174 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel Jasperlake RVP with ITE EC board specific configuration */ + +#include "anx7440.h" +#include "button.h" +#include "charger.h" +#include "driver/charger/isl923x.h" +#include "extpower.h" +#include "i2c.h" +#include "intc.h" +#include "it83xx_pd.h" +#include "lid_switch.h" +#include "power.h" +#include "power/icelake.h" +#include "power_button.h" +#include "switch.h" +#include "system.h" +#include "tablet_mode.h" +#include "uart.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" + +#include "gpio_list.h" + +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) + +/* TCPC gpios */ +const struct tcpc_gpio_config_t tcpc_gpios[] = { + [TYPE_C_PORT_0] = { + .vbus = { + .pin = GPIO_USB_C0_VBUS_INT, + .pin_pol = 1, + }, + .src = { + .pin = GPIO_USB_C0_SRC_EN, + .pin_pol = 1, + }, + .snk = { + .pin = GPIO_USB_C0_SNK_EN_L, + .pin_pol = 0, + }, + }, + [TYPE_C_PORT_1] = { + .vbus = { + .pin = GPIO_USB_C1_VBUS_INT, + .pin_pol = 1, + }, + .src = { + .pin = GPIO_USB_C1_SRC_EN, + .pin_pol = 1, + }, + .snk = { + .pin = GPIO_USB_C1_SNK_EN_L, + .pin_pol = 0, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C TPCP Configuration */ +const struct tcpc_config_t tcpc_config[] = { + [TYPE_C_PORT_0] = { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it83xx_tcpm_drv, + }, + [TYPE_C_PORT_1] = { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it83xx_tcpm_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT); + +const struct usb_mux usb_muxes[] = { + [TYPE_C_PORT_0] = { + .usb_port = TYPE_C_PORT_0, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = I2C_ADDR_USB_MUX0_FLAGS, + .driver = &anx7440_usb_mux_driver, + }, + [TYPE_C_PORT_1] = { + .usb_port = TYPE_C_PORT_1, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = I2C_ADDR_USB_MUX1_FLAGS, + .driver = &anx7440_usb_mux_driver, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + /* Flash EC */ + [I2C_CHAN_FLASH] = { + .name = "chan-A", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA, + }, + /* + * Port-80 Display, Charger, Battery, IO-expanders, EEPROM, + * IMVP9, AUX-rail, power-monitor. + */ + [I2C_CHAN_BATT_CHG] = { + .name = "batt_chg", + .port = IT83XX_I2C_CH_B, + .kbps = 100, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA, + }, + /* Retimers, PDs */ + [I2C_CHAN_RETIMER] = { + .name = "retimer", + .port = IT83XX_I2C_CH_E, + .kbps = 100, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT); +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* Charger Chips */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = ISL923X_ADDR_FLAGS, + .drv = &isl923x_drv, + }, +}; + +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * On JSLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK + * signals are handled by the board. No EC control needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +/* + * Returns board information (board id[7:0] and Fab id[15:8]) on success + * -1 on error. + */ +int board_get_version(void) +{ + int fab_id; + int board_id; + int bom_id; + + if (ioexpander_read_intelrvp_version(&fab_id, &board_id)) + return -1; + /* + * Port0: bit 1:0 - FAB ID(1:0) + 1 + * Port1: bit 7:5 - BOM ID(2:0) + * bit 4:0 - BOARD ID(4:0) + */ + fab_id = (fab_id & 0x03) + 1; + bom_id = ((board_id & 0xE0) >> 5); + board_id &= 0x1F; + + CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id); + + return board_id | (fab_id << 8); +} diff --git a/board/jslrvp_ite/board.h b/board/jslrvp_ite/board.h new file mode 100644 index 0000000000..e733a30240 --- /dev/null +++ b/board/jslrvp_ite/board.h @@ -0,0 +1,99 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel Jasperlake RVP with ITE EC board specific configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* ITE EC variant */ +#define VARIANT_INTELRVP_EC_IT8320 + +/* MECC config */ +#define CONFIG_INTEL_RVP_MECC_VERSION_0_9 + +#define CONFIG_CHIPSET_JASPERLAKE +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L +#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L +#define GPIO_BAT_LED_RED_L GPIO_BAT_LED_GREEN_L +#define GPIO_PWR_LED_WHITE_L GPIO_AC_LED_GREEN_L + +/* Fan features */ +#define CONFIG_FANS 1 +#define BOARD_FAN_MIN_RPM 3000 +#define BOARD_FAN_MAX_RPM 10000 + +/* Temperature sensor */ +#define CONFIG_TEMP_SENSOR + +#include "baseboard.h" + +/* Charger */ +#define CONFIG_CHARGER_ISL9238 + +/* DC Jack charge ports */ +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 + +/* USB ports */ +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define DEDICATED_CHARGE_PORT 2 + +/* USB PD config */ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 +#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT + +/* USB MUX */ +#define CONFIG_USB_MUX_ANX7440 + +/* USB HPD */ +#define CONFIG_USB_PD_DP_HPD_GPIO + +/* Thermal configs */ + +/* I2C ports */ +#define CONFIG_IT83XX_SMCLK2_ON_GPC7 + +#define I2C_PORT_CHARGER IT83XX_I2C_CH_B +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B +#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B +#define I2C_PORT_PORT80 IT83XX_I2C_CH_B +#define I2C_PORT_USB_MUX IT83XX_I2C_CH_E + +#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 +#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS + +#ifndef __ASSEMBLER__ + +enum jslrvp_charge_ports { + TYPE_C_PORT_0, + TYPE_C_PORT_1, +}; + +enum jslrvp_i2c_channel { + I2C_CHAN_FLASH, + I2C_CHAN_BATT_CHG, + I2C_CHAN_RETIMER, + I2C_CHAN_COUNT, +}; + +enum battery_type { + BATTERY_SIMPLO_SMP_HHP_408, + BATTERY_SIMPLO_SMP_CA_445, + BATTERY_TYPE_COUNT, +}; + +/* Define max power */ +#define PD_MAX_POWER_MW 45000 + +int board_get_version(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/jslrvp_ite/build.mk b/board/jslrvp_ite/build.mk new file mode 100644 index 0000000000..4903661c30 --- /dev/null +++ b/board/jslrvp_ite/build.mk @@ -0,0 +1,16 @@ +# -*- makefile -*- +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Intel Jasperlake RVP with ITE EC board specific configuration +# + +#it8320 +CHIP:=it83xx +CHIP_FAMILY:=it8320 +CHIP_VARIANT:=it8320dx +BASEBOARD:=intelrvp + +board-y=board.o +board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/board/jslrvp_ite/ec.tasklist b/board/jslrvp_ite/ec.tasklist new file mode 100644 index 0000000000..768211c95f --- /dev/null +++ b/board/jslrvp_ite/ec.tasklist @@ -0,0 +1,23 @@ +/* + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel Jasperlake RVP with ITE EC board specific configuration. + * See CONFIG_TASK_LIST in config.h for details. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc new file mode 100644 index 0000000000..387020100e --- /dev/null +++ b/board/jslrvp_ite/gpio.inc @@ -0,0 +1,184 @@ +/* -*- mode:c -*- + * + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel Jasperlake RVP with ITE EC board specific configuration */ + +/* + * Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. + */ + +/* Power sequencing interrupts */ +GPIO_INT(PG_EC_DSW_PWROK, PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_SUS_L, PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(ALL_SYS_PWRGD, PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(RSMRST_L_PGOOD,PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PCH_SLP_S0_L, PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt) +#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +GPIO_INT(PCH_SLP_S3_L, PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt) +#endif +#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 +GPIO_INT(PCH_SLP_S4_L, PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt) +#endif + +/* Button interrupts */ +GPIO_INT(VOLUME_UP_L, PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(VOLUME_DOWN_L, PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(LID_OPEN, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt) +GPIO_INT(POWER_BUTTON_L,PIN(L, 3), GPIO_INT_BOTH, power_button_interrupt) + +GPIO_INT(AC_PRESENT, PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt) + +GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt) /* UART1 RX input */ + +GPIO_INT(WP_L, PIN(I, 4), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */ + +#ifdef CONFIG_HOST_INTERFACE_ESPI +/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */ +GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */ +#endif + +GPIO_INT(TABLET_MODE_L, PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr) + +/* DC Jack presence coming from +VADP_OUT */ +GPIO_INT(DC_JACK_PRESENT, PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) + +/* Type-C interrupts */ +GPIO_INT(USB_C0_VBUS_INT, PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event) +GPIO_INT(USB_C1_VBUS_INT, PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event) + +/* Power sequencing GPIOs */ +GPIO(CPU_PROCHOT, PIN(B, 2), GPIO_INPUT) +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) +GPIO(PCH_RSMRST_L, PIN(C, 6), GPIO_OUT_LOW) +GPIO(PCH_PWRBTN_L, PIN(D, 0), GPIO_ODR_HIGH) +GPIO(EC_SPI_OE_N, PIN(I, 2), GPIO_OUT_LOW) +/* + * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86 + * power sequencing expects that PCH_SYS_PWROK is an output and will drive + * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect + * so that state can be monitored using the console. + */ +GPIO(NC_PCH_SYS_PWROK, PIN(K, 4), GPIO_INPUT) +GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) +GPIO(EN_PP3300_A, PIN(C, 3), GPIO_OUT_LOW) +GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) + +UNIMPLEMENTED(EN_VCCIO_EXT) + +/* Host communication GPIOs */ +GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) +#ifndef CONFIG_HOST_INTERFACE_ESPI +GPIO(PCH_PLTRST_L, PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP) +#endif + +/* Battery present */ +GPIO(EC_BATT_PRES_L, PIN(K, 0), GPIO_INPUT) + +/* Type-C GPIOs */ +GPIO(USB_C0_SRC_EN, PIN(L, 1), GPIO_OUT_LOW) +GPIO(USB_C0_SNK_EN_L, PIN(H, 6), GPIO_ODR_LOW) +GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW) +GPIO(USB_C0_DP_HPD, PIN(E, 6), GPIO_OUT_LOW) +GPIO(USB_C0_FRS_EN, PIN(L, 7), GPIO_INPUT) + +GPIO(USB_C1_SRC_EN, PIN(G, 1), GPIO_OUT_LOW) +GPIO(USB_C1_SNK_EN_L, PIN(I, 5), GPIO_ODR_LOW) +GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW) +GPIO(USB_C1_DP_HPD, PIN(D, 3), GPIO_OUT_LOW) +GPIO(USB_C1_FRS_EN, PIN(K, 5), GPIO_INPUT) + +/* + * Type-C USB MUX GPIOs + * TODO(b/146683781): drive initial level to low and + * handle the low power mode + */ +GPIO(USB_C0_LS_EN, PIN(J, 1), GPIO_OUT_HIGH) +GPIO(USB_C1_LS_EN, PIN(C, 4), GPIO_OUT_HIGH) + +/* Type-C BC1.2 GPIOs */ +GPIO(USB_C0_BC12_CHG_DET_L, PIN(A, 1), GPIO_INPUT) +GPIO(USB_C0_BC12_VBUS_ON_ODL, PIN(H, 4), GPIO_ODR_HIGH) + +GPIO(USB_C1_BC12_CHG_DET_L, PIN(B, 7), GPIO_INPUT) +GPIO(USB_C1_BC12_VBUS_ON_ODL, PIN(J, 6), GPIO_ODR_HIGH) + +/* USB-A GPIOs */ +GPIO(USB_A_5V_EN, PIN(K, 3), GPIO_INPUT) + +/* LED */ +GPIO(BAT_LED_GREEN_L, PIN(A, 6), GPIO_OUT_HIGH) /* LED_2_L */ +GPIO(AC_LED_GREEN_L, PIN(A, 3), GPIO_OUT_HIGH) /* LED_1_L */ + +/* FAN control pins */ +GPIO(FAN_POWER_EN, PIN(K, 6), GPIO_OUT_LOW) + +/* H1 pins */ +GPIO(CCD_MODE_ODL, PIN(B, 5), GPIO_INPUT) +GPIO(ENTERING_RW, PIN(C, 5), GPIO_OUT_LOW) + +/* Used if Type-A ports have BC1.2 */ +GPIO(NC_USB_A_CHG_EN, PIN(D, 1), GPIO_INPUT) + +/* Used if dead battery LDO present */ +GPIO(NC_USBC_LDO_ENABLE, PIN(G, 2), GPIO_INPUT) + +/* Used with Discreate TBT and or with PD on RVP */ +GPIO(NC_TBT_C0_RESET_N, PIN(KSO_H, 7), GPIO_INPUT) +GPIO(NC_TBT_C1_RESET_N, PIN(K, 7), GPIO_INPUT) +GPIO(NC_USB_C0_RETIMER_ALRT, PIN(I, 7), GPIO_INPUT) +GPIO(NC_USB_C1_RETIMER_ALRT, PIN(G, 0), GPIO_INPUT) + +/* Used if PMIC is used */ +GPIO(NC_PMIC_EN, PIN(H, 3), GPIO_INPUT) + +/* Used if Base EC is present */ +GPIO(NC_EC_BASE_DET, PIN(I, 3), GPIO_INPUT) + +#ifndef CONFIG_HOST_INTERFACE_ESPI +GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INPUT) +#endif + +/* Unused pins */ +GPIO(NC_SUSWARN, PIN(E, 1), GPIO_INPUT) +GPIO(NC_SD_CARD_DETECT, PIN(E, 5), GPIO_INPUT) +GPIO(NC_BATT_DISABLE, PIN(H, 0), GPIO_INPUT) +GPIO(NC_SLP_S0_CS_N, PIN(I, 0), GPIO_INPUT) + +/* + * I2C pins should be configure as inputs until I2C module is + * initialized. This will avoid driving the lines unintentionally. + */ +GPIO(I2C_A_SCL, PIN(B, 3), GPIO_INPUT) +GPIO(I2C_A_SDA, PIN(B, 4), GPIO_INPUT) +GPIO(I2C_B_SCL, PIN(C, 1), GPIO_INPUT) +GPIO(I2C_B_SDA, PIN(C, 2), GPIO_INPUT) +GPIO(I2C_C_SCL, PIN(C, 7), GPIO_INPUT) +GPIO(I2C_C_SDA, PIN(F, 7), GPIO_INPUT) +GPIO(I2C_E_SCL, PIN(E, 0), GPIO_INPUT) +GPIO(I2C_E_SDA, PIN(E, 7), GPIO_INPUT) +GPIO(I2C_F_SCL, PIN(A, 4), GPIO_INPUT) +GPIO(I2C_F_SDA, PIN(A, 5), GPIO_INPUT) + +/* Alternate pins for I2C */ +ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C F SCL/SDA A4/A5 */ +ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C A SCL/SDA B3/B4 */ +ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C B SCL/SDA C1/C2 */ +ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C E SCL/SDA E0/E7 */ +ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C C SCL C7 */ +ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C C SDA F7 */ + +/* Alternate pins for UART */ +ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */ + +/* Alternate pins for ADC */ +ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE) /* ADC 1,6 -> I1,I6 */ +ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE) /* ADC 13,15 -> L0,L2 */ + +/* Alternate pins for FAN */ +ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* PWM2 A2 */ +ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* TACH1A D7 */ diff --git a/board/jslrvp_ite/vif_override.xml b/board/jslrvp_ite/vif_override.xml new file mode 100644 index 0000000000..32736caf64 --- /dev/null +++ b/board/jslrvp_ite/vif_override.xml @@ -0,0 +1,3 @@ +<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File + Definition from the USB-IF. +--> diff --git a/board/tglrvpu_ite/battery.c b/board/tglrvpu_ite/battery.c new file mode 100644 index 0000000000..d529f7677e --- /dev/null +++ b/board/tglrvpu_ite/battery.c @@ -0,0 +1,77 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery_fuel_gauge.h" +#include "battery_smart.h" +#include "common.h" +#include "util.h" + +const struct board_batt_params board_battery_info[] = { + /* + * Simplo Battery (SMP-HHP-408) Information + * Fuel gauge: BQ40Z50 + */ + [BATTERY_SIMPLO_SMP_HHP_408] = { + .fuel_gauge = { + .manuf_name = "SMP-HHP-408", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .reg_addr = SB_BATTERY_STATUS, + .reg_mask = STATUS_INITIALIZED, + .disconnect_val = 0x0, + } + }, + .batt_info = { + .voltage_max = 8700, /* mV */ + .voltage_normal = 7600, + .voltage_min = 6100, + .precharge_current = 204, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = 0, + .discharging_max_c = 60, + }, + }, + /* + * Simplo Battery (SMP-CA-445) Information + * Fuel gauge: BQ30Z554 + */ + [BATTERY_SIMPLO_SMP_CA_445] = { + .fuel_gauge = { + .manuf_name = "SMP-CA-445", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .reg_addr = SB_BATTERY_STATUS, + .reg_mask = STATUS_INITIALIZED, + .disconnect_val = 0x0, + } + }, + .batt_info = { + .voltage_max = 8700, /* mV */ + .voltage_normal = 7600, + .voltage_min = 6100, + .precharge_current = 150, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 45, + .discharging_min_c = -20, + .discharging_max_c = 60, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SIMPLO_SMP_HHP_408; diff --git a/board/tglrvpu_ite/board.c b/board/tglrvpu_ite/board.c new file mode 100644 index 0000000000..4c96576b28 --- /dev/null +++ b/board/tglrvpu_ite/board.c @@ -0,0 +1,272 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel TGL-U-RVP-ITE board-specific configuration */ + +#include "button.h" +#include "charger.h" +#include "driver/charger/isl9241.h" +#include "driver/retimer/bb_retimer_public.h" +#include "extpower.h" +#include "i2c.h" +#include "intc.h" +#include "it83xx_pd.h" +#include "lid_switch.h" +#include "power.h" +#include "power/icelake.h" +#include "power_button.h" +#include "switch.h" +#include "system.h" +#include "tablet_mode.h" +#include "uart.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" + +#include "gpio_list.h" + +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) + +/* Mutex for shared NVM access */ +static struct mutex bb_nvm_mutex; + +/* TCPC gpios */ +const struct tcpc_gpio_config_t tcpc_gpios[] = { + [TYPE_C_PORT_0] = { + .vbus = { + .pin = GPIO_USB_C0_VBUS_INT, + .pin_pol = 1, + }, + .src = { + .pin = GPIO_USB_C0_SRC_EN, + .pin_pol = 1, + }, + .snk = { + .pin = GPIO_USB_C0_SNK_EN_L, + .pin_pol = 0, + }, + .vconn = { + .cc1_pin = GPIO_USB_C0_CC1_VCONN_EN, + .cc2_pin = GPIO_USB_C0_CC2_VCONN_EN, + .pin_pol = 1, + }, + .src_ilim = { + .pin = GPIO_USB_C0_SRC_HI_ILIM, + .pin_pol = 1, + }, + }, + [TYPE_C_PORT_1] = { + .vbus = { + .pin = GPIO_USB_C1_VBUS_INT, + .pin_pol = 1, + }, + .src = { + .pin = GPIO_USB_C1_SRC_EN, + .pin_pol = 1, + }, + .snk = { + .pin = GPIO_USB_C1_SNK_EN_L, + .pin_pol = 0, + }, + .vconn = { + .cc1_pin = GPIO_USB_C1_CC1_VCONN_EN, + .cc2_pin = GPIO_USB_C1_CC2_VCONN_EN, + .pin_pol = 1, + }, + .src_ilim = { + .pin = GPIO_USB_C1_SRC_HI_ILIM, + .pin_pol = 1, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C TPCP Configuration */ +const struct tcpc_config_t tcpc_config[] = { + [TYPE_C_PORT_0] = { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it83xx_tcpm_drv, + }, + [TYPE_C_PORT_1] = { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it83xx_tcpm_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* BB Retimers configuration */ +const struct bb_usb_control bb_controls[] = { + [TYPE_C_PORT_0] = { + .usb_ls_en_gpio = GPIO_USB_C0_LS_EN, + .retimer_rst_gpio = GPIO_USB_C0_RETIMER_RST, + }, + [TYPE_C_PORT_1] = { + .usb_ls_en_gpio = GPIO_USB_C1_LS_EN, + .retimer_rst_gpio = GPIO_USB_C1_RETIMER_RST, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB retimer Configuration */ +struct usb_mux usbc0_tcss_usb_mux = { + .usb_port = TYPE_C_PORT_0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, +}; + +struct usb_mux usbc1_tcss_usb_mux = { + .usb_port = TYPE_C_PORT_1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, +}; + +/* USB muxes Configuration */ +const struct usb_mux usb_muxes[] = { + [TYPE_C_PORT_0] = { + .usb_port = TYPE_C_PORT_0, + .next_mux = &usbc0_tcss_usb_mux, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT0_BB_RETIMER, + .i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR, + }, + [TYPE_C_PORT_1] = { + .usb_port = TYPE_C_PORT_1, + .next_mux = &usbc1_tcss_usb_mux, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT1_BB_RETIMER, + .i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + /* Flash EC */ + [I2C_CHAN_FLASH] = { + .name = "chan-A", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA, + }, + /* + * Port-80 Display, Charger, Battery, IO-expanders, EEPROM, + * IMVP9, AUX-rail, power-monitor. + */ + [I2C_CHAN_BATT_CHG] = { + .name = "batt_chg", + .port = IT83XX_I2C_CH_B, + .kbps = 100, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA, + }, + /* Retimers, PDs */ + [I2C_CHAN_RETIMER] = { + .name = "retimer", + .port = IT83XX_I2C_CH_E, + .kbps = 100, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT); +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* Charger Chips */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = ISL9241_ADDR_FLAGS, + .drv = &isl9241_drv, + }, +}; + +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * On TGLRVP the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK + * signals are handled by the board. No EC control needed. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +/* + * Returns board information (board id[7:0] and Fab id[15:8]) on success + * -1 on error. + */ +int board_get_version(void) +{ + int port0, port1; + int fab_id, board_id, bom_id; + + if (ioexpander_read_intelrvp_version(&port0, &port1)) + return -1; + /* + * Port0: bit 0 - BOM ID(2) + * bit 2:1 - FAB ID(1:0) + 1 + * Port1: bit 7:6 - BOM ID(1:0) + * bit 5:0 - BOARD ID(5:0) + */ + bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2); + fab_id = ((port0 & 0x06) >> 1) + 1; + board_id = port1 & 0x3F; + + CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id); + + return board_id | (fab_id << 8); +} + +__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) +{ + const struct bb_usb_control *control = &bb_controls[me->usb_port]; + + /* + * LSx based F/W updating is a POR, however to avoid the rework on + * RVP retain the FORCE_PWR GPIO with EC. + */ + enum gpio_signal force_power_gpio = me->usb_port ? + GPIO_USB_C1_RETIMER_FORCE_PWR : GPIO_USB_C0_RETIMER_FORCE_PWR; + + /* handle retimer's power domain */ + if (enable) { + /* + * BB retimer NVM can be shared between multiple ports, hence + * lock enabling the retimer until the current retimer request + * is complete. + */ + mutex_lock(&bb_nvm_mutex); + + gpio_set_level(control->usb_ls_en_gpio, 1); + /* + * Tpw, minimum time from VCC to RESET_N de-assertion is 100us. + * For boards that don't provide a load switch control, the + * retimer_init() function ensures power is up before calling + * this function. + */ + msleep(1); + gpio_set_level(control->retimer_rst_gpio, 1); + msleep(10); + gpio_set_level(force_power_gpio, 1); + + /* Allow 20ms time for the retimer to be initialized. */ + msleep(20); + + mutex_unlock(&bb_nvm_mutex); + } else { + gpio_set_level(force_power_gpio, 0); + msleep(1); + gpio_set_level(control->retimer_rst_gpio, 0); + msleep(1); + gpio_set_level(control->usb_ls_en_gpio, 0); + } + return EC_SUCCESS; +} diff --git a/board/tglrvpu_ite/board.h b/board/tglrvpu_ite/board.h new file mode 100644 index 0000000000..9351fe5982 --- /dev/null +++ b/board/tglrvpu_ite/board.h @@ -0,0 +1,121 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel TGL-U-RVP-ITE board-specific configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* ITE EC variant */ +#define VARIANT_INTELRVP_EC_IT8320 + +/* MECC config */ +#define CONFIG_INTEL_RVP_MECC_VERSION_0_9 + +/* USB MUX */ +#define CONFIG_USB_MUX_VIRTUAL + +#define CONFIG_USBC_VCONN + +/* FAN configs */ +#define CONFIG_FANS 1 +#define BOARD_FAN_MIN_RPM 3000 +#define BOARD_FAN_MAX_RPM 10000 + +/* Temperature sensor */ +#define CONFIG_TEMP_SENSOR + +/* Support early firmware selection */ +#define CONFIG_VBOOT_EFS2 +#define GPIO_PACKET_MODE_EN GPIO_ME_G3_TO_ME_EC + +#include "baseboard.h" + +#define CONFIG_CHIPSET_TIGERLAKE +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L +#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L +#define GPIO_BAT_LED_RED_L GPIO_BAT_LED_GREEN_L +#define GPIO_PWR_LED_WHITE_L GPIO_AC_LED_GREEN_L + +/* Charger */ +#define CONFIG_CHARGER_ISL9241 + +/* DC Jack charge ports */ +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 + +/* USB ports */ +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define DEDICATED_CHARGE_PORT 2 + +/* USB PD config */ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 + +/* Config BB retimer */ +#define CONFIG_USBC_RETIMER_INTEL_BB + +/* Thermal configs */ + +/* I2C ports */ +#define CONFIG_IT83XX_SMCLK2_ON_GPC7 + +#define I2C_PORT_CHARGER IT83XX_I2C_CH_B +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B +#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B +#define I2C_PORT_PORT80 IT83XX_I2C_CH_B +#define I2C_PORT0_BB_RETIMER IT83XX_I2C_CH_E +#define I2C_PORT1_BB_RETIMER IT83XX_I2C_CH_E + +#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 +#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS +#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1) + #define I2C_PORT0_BB_RETIMER_ADDR 0x42 + #define I2C_PORT1_BB_RETIMER_ADDR 0x43 +#else /* BOARD_TGLRVPY_ITE */ + #define I2C_PORT0_BB_RETIMER_ADDR 0x42 + #define I2C_PORT1_BB_RETIMER_ADDR 0x41 +#endif /* BOARD_TGLRVPU_ITE */ + +/* Enabling SOP* communication */ +#define CONFIG_USB_PD_DECODE_SOP + +/* Enabling Thunderbolt-compatible mode */ +#define CONFIG_USB_PD_TBT_COMPAT_MODE + +/* Enabling USB4 mode */ +#define CONFIG_USB_PD_USB4 + +#ifndef __ASSEMBLER__ + +enum tglrvp_charge_ports { + TYPE_C_PORT_0, + TYPE_C_PORT_1, +}; + +enum tglrvp_i2c_channel { + I2C_CHAN_FLASH, + I2C_CHAN_BATT_CHG, + I2C_CHAN_RETIMER, + I2C_CHAN_COUNT, +}; + +enum battery_type { + BATTERY_SIMPLO_SMP_HHP_408, + BATTERY_SIMPLO_SMP_CA_445, + BATTERY_TYPE_COUNT, +}; + +/* Define max power */ +#define PD_MAX_POWER_MW 60000 + +int board_get_version(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/tglrvpu_ite/build.mk b/board/tglrvpu_ite/build.mk new file mode 100644 index 0000000000..4d8fd44fdf --- /dev/null +++ b/board/tglrvpu_ite/build.mk @@ -0,0 +1,16 @@ +# -*- makefile -*- +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Intel TGL-U-RVP-ITE board-specific configuration +# + +#it8320 +CHIP:=it83xx +CHIP_FAMILY:=it8320 +CHIP_VARIANT:=it8320dx +BASEBOARD:=intelrvp + +board-y=board.o +board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/board/tglrvpu_ite/ec.tasklist b/board/tglrvpu_ite/ec.tasklist new file mode 100644 index 0000000000..4e65a446e4 --- /dev/null +++ b/board/tglrvpu_ite/ec.tasklist @@ -0,0 +1,24 @@ +/* + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Intel TGL-U-RVP-ITE board-specific configuration. + * See CONFIG_TASK_LIST in config.h for details. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc new file mode 100644 index 0000000000..b84c92aac6 --- /dev/null +++ b/board/tglrvpu_ite/gpio.inc @@ -0,0 +1,209 @@ +/* -*- mode:c -*- + * + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel TGL-U-RVP-ITE board-specific configuration */ + +/* + * Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. + */ + +/* Power sequencing interrupts */ +GPIO_INT(PG_EC_DSW_PWROK, PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_SUS_L, PIN(C, 3), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(ALL_SYS_PWRGD, PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(RSMRST_L_PGOOD, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PCH_SLP_S0_L, PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt) +#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +GPIO_INT(PCH_SLP_S3_L, PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt) +#endif +#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 +GPIO_INT(PCH_SLP_S4_L, PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt) +#endif + +/* Button interrupts */ +GPIO_INT(VOLUME_UP_L, PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(VOLUME_DOWN_L, PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(LID_OPEN, PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt) +GPIO_INT(POWER_BUTTON_L,PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt) + +GPIO_INT(AC_PRESENT, PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt) + +GPIO_INT(UART1_RX, PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt) /* UART1 RX input */ + +GPIO_INT(WP_L, PIN(I, 4), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */ + +#ifdef CONFIG_HOST_INTERFACE_ESPI +/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */ +GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */ +#endif + +GPIO_INT(TABLET_MODE_L, PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr) + +/* DC Jack presence coming from +VADP_OUT */ +GPIO_INT(DC_JACK_PRESENT, PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt) + +/* Type-C interrupts */ +#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1) +GPIO_INT(USB_C0_VBUS_INT, PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event) +GPIO_INT(USB_C1_VBUS_INT, PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event) +#else /* BOARD_TGLRVPY_ITE */ +GPIO_INT(USB_C0_VBUS_INT, PIN(D, 4), GPIO_INT_BOTH, tcpc_alert_event) +GPIO_INT(USB_C1_VBUS_INT, PIN(L, 5), GPIO_INT_BOTH, tcpc_alert_event) +#endif /* BOARD_TGLRVPU_ITE */ + +/* Power sequencing GPIOs */ +GPIO(CPU_PROCHOT, PIN(B, 2), GPIO_INPUT) +GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) +GPIO(PCH_RSMRST_L, PIN(C, 6), GPIO_OUT_LOW) +GPIO(PCH_PWRBTN_L, PIN(D, 0), GPIO_ODR_HIGH) +GPIO(EC_SPI_OE_N, PIN(I, 2), GPIO_OUT_LOW) +/* + * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86 + * power sequencing expects that PCH_SYS_PWROK is an output and will drive + * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect + * so that state can be monitored using the console. + */ +GPIO(NC_PCH_SYS_PWROK, PIN(K, 4), GPIO_INPUT) +GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) +GPIO(EN_PP3300_A, PIN(K, 2), GPIO_OUT_LOW) +GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) + +/* Host communication GPIOs */ +GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) +#ifndef CONFIG_HOST_INTERFACE_ESPI +GPIO(PCH_PLTRST_L, PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP) +#endif + +/* Battery present */ +GPIO(EC_BATT_PRES_L, PIN(K, 0), GPIO_INPUT) + +/* Type-C GPIOs */ +#if defined(BOARD_TGLRVPU_ITE) || defined(BOARD_TGLRVPU_ITE_TCPMV1) +GPIO(USB_C0_SRC_EN, PIN(L, 1), GPIO_OUT_LOW) +GPIO(USB_C0_SNK_EN_L, PIN(H, 6), GPIO_ODR_LOW) +GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW) +GPIO(USB_C0_HPD, PIN(E, 6), GPIO_INPUT) +GPIO(USB_C0_FRS_EN, PIN(L, 7), GPIO_INPUT) + +GPIO(USB_C1_SRC_EN, PIN(G, 1), GPIO_OUT_LOW) +GPIO(USB_C1_SNK_EN_L, PIN(I, 5), GPIO_ODR_LOW) +GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW) +GPIO(USB_C1_HPD, PIN(D, 3), GPIO_INPUT) +GPIO(USB_C1_FRS_EN, PIN(K, 5), GPIO_INPUT) + +/* Retimer GPIOs */ +GPIO(USB_C0_LS_EN, PIN(J, 1), GPIO_OUT_LOW) +GPIO(USB_C0_RETIMER_RST, PIN(J, 5), GPIO_OUT_LOW) +GPIO(USB_C0_RETIMER_FORCE_PWR, PIN(J, 3), GPIO_OUT_LOW) + +GPIO(USB_C1_LS_EN, PIN(C, 4), GPIO_OUT_LOW) +GPIO(USB_C1_RETIMER_RST, PIN(J, 4), GPIO_OUT_LOW) +GPIO(USB_C1_RETIMER_FORCE_PWR, PIN(H, 5), GPIO_OUT_LOW) +#else /* BOARD_TGLRVPY_ITE */ +GPIO(USB_C0_SRC_EN, PIN(G, 1), GPIO_OUT_LOW) +GPIO(USB_C0_SNK_EN_L, PIN(I, 5), GPIO_ODR_LOW | GPIO_PULL_DOWN) +GPIO(USB_C0_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW) +GPIO(USB_C0_HPD, PIN(D, 3), GPIO_INPUT) +GPIO(USB_C0_FRS_EN, PIN(K, 5), GPIO_INPUT) + +GPIO(USB_C1_SRC_EN, PIN(L, 1), GPIO_OUT_LOW) +GPIO(USB_C1_SNK_EN_L, PIN(H, 6), GPIO_ODR_LOW | GPIO_PULL_DOWN) +GPIO(USB_C1_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW) +GPIO(USB_C1_HPD, PIN(E, 6), GPIO_INPUT) +GPIO(USB_C1_FRS_EN, PIN(L, 7), GPIO_INPUT) + +/* Retimer GPIOs */ +GPIO(USB_C0_LS_EN, PIN(C, 4), GPIO_OUT_LOW) +GPIO(USB_C0_RETIMER_RST, PIN(J, 4), GPIO_OUT_LOW) +GPIO(USB_C0_RETIMER_FORCE_PWR, PIN(H, 5), GPIO_OUT_LOW) + +GPIO(USB_C1_LS_EN, PIN(J, 1), GPIO_OUT_LOW) +GPIO(USB_C1_RETIMER_RST, PIN(J, 5), GPIO_OUT_LOW) +GPIO(USB_C1_RETIMER_FORCE_PWR, PIN(J, 3), GPIO_OUT_LOW) +#endif /* BOARD_TGLRVPU_ITE */ + +/* Type-C BC1.2 GPIOs */ +GPIO(USB_C0_BC12_CHG_DET_L, PIN(A, 1), GPIO_INPUT) +GPIO(USB_C0_BC12_VBUS_ON_ODL, PIN(H, 4), GPIO_ODR_HIGH) + +GPIO(USB_C1_BC12_CHG_DET_L, PIN(B, 7), GPIO_INPUT) +GPIO(USB_C1_BC12_VBUS_ON_ODL, PIN(J, 6), GPIO_ODR_HIGH) + +/* VCONN enable pins */ +GPIO(USB_C0_CC1_VCONN_EN, PIN(D, 1), GPIO_OUT_LOW) +GPIO(USB_C0_CC2_VCONN_EN, PIN(G, 2), GPIO_OUT_LOW) +GPIO(USB_C1_CC1_VCONN_EN, PIN(E, 5), GPIO_OUT_LOW) +GPIO(USB_C1_CC2_VCONN_EN, PIN(I, 0), GPIO_OUT_LOW) + +/* USB-A GPIOs */ +GPIO(USB_A_5V_EN, PIN(K, 3), GPIO_INPUT) + +/* LED */ +GPIO(BAT_LED_GREEN_L, PIN(A, 6), GPIO_OUT_HIGH) /* LED_2_L */ +GPIO(AC_LED_GREEN_L, PIN(A, 3), GPIO_OUT_HIGH) /* LED_1_L */ + +/* FAN control pins */ +GPIO(FAN_POWER_EN, PIN(K, 6), GPIO_OUT_LOW) + +/* H1 pins */ +GPIO(CCD_MODE_ODL, PIN(B, 5), GPIO_INPUT) +GPIO(ENTERING_RW, PIN(C, 5), GPIO_OUT_LOW) +/* ME_GE_TO_ME_EC pin is re-purposed for H1 Packet Mode indication */ +GPIO(ME_G3_TO_ME_EC, PIN(H, 3), GPIO_OUT_LOW) + +/* Used with Discrete TBT and or with PD on RVP */ +GPIO(NC_TBT_C0_RESET_N, PIN(KSO_H, 7), GPIO_INPUT) +GPIO(NC_TBT_C1_RESET_N, PIN(K, 7), GPIO_INPUT) +GPIO(NC_USB_C0_RETIMER_ALRT, PIN(I, 7), GPIO_INPUT) +GPIO(NC_USB_C1_RETIMER_ALRT, PIN(G, 0), GPIO_INPUT) + +/* Used if Base EC is present */ +GPIO(NC_EC_BASE_DET, PIN(I, 3), GPIO_INPUT) + +#ifndef CONFIG_HOST_INTERFACE_ESPI +GPIO_INT(ESPI_RESET_L, PIN(D, 2), GPIO_INPUT) +#endif + +/* Unused pins */ +GPIO(NC_SUSWARN, PIN(E, 1), GPIO_INPUT) +GPIO(NC_BATT_DISABLE, PIN(H, 0), GPIO_INPUT) +GPIO(NC_SMC_ONOFF_N, PIN(L, 3), GPIO_INPUT) /* Power button interrupt without H1 */ + +/* + * I2C pins should be configure as inputs until I2C module is + * initialized. This will avoid driving the lines unintentionally. + */ +GPIO(I2C_A_SCL, PIN(B, 3), GPIO_INPUT) +GPIO(I2C_A_SDA, PIN(B, 4), GPIO_INPUT) +GPIO(I2C_B_SCL, PIN(C, 1), GPIO_INPUT) +GPIO(I2C_B_SDA, PIN(C, 2), GPIO_INPUT) +GPIO(I2C_C_SCL, PIN(C, 7), GPIO_INPUT) +GPIO(I2C_C_SDA, PIN(F, 7), GPIO_INPUT) +GPIO(I2C_E_SCL, PIN(E, 0), GPIO_INPUT) +GPIO(I2C_E_SDA, PIN(E, 7), GPIO_INPUT) +GPIO(I2C_F_SCL, PIN(A, 4), GPIO_INPUT) +GPIO(I2C_F_SDA, PIN(A, 5), GPIO_INPUT) + +/* Alternate pins for I2C */ +ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C F SCL/SDA A4/A5 */ +ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C A SCL/SDA B3/B4 */ +ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C B SCL/SDA C1/C2 */ +ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C E SCL/SDA E0/E7 */ +ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C C SCL C7 */ +ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE) /* I2C C SDA F7 */ + +/* Alternate pins for UART */ +ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */ + +/* Alternate pins for ADC */ +ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE) /* ADC 1,6 -> I1,I6 */ +ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE) /* ADC 13,15 -> L0,L2 */ + +/* Alternate pins for FAN */ +ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* PWM2 A2 */ +ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE) /* TACH1A D7 */ diff --git a/board/tglrvpu_ite/vif_override.xml b/board/tglrvpu_ite/vif_override.xml new file mode 100644 index 0000000000..32736caf64 --- /dev/null +++ b/board/tglrvpu_ite/vif_override.xml @@ -0,0 +1,3 @@ +<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File + Definition from the USB-IF. +--> diff --git a/board/tglrvpu_ite_tcpmv1 b/board/tglrvpu_ite_tcpmv1 new file mode 120000 index 0000000000..05edd4d22f --- /dev/null +++ b/board/tglrvpu_ite_tcpmv1 @@ -0,0 +1 @@ +tglrvpu_ite
\ No newline at end of file diff --git a/board/tglrvpy_ite b/board/tglrvpy_ite new file mode 120000 index 0000000000..05edd4d22f --- /dev/null +++ b/board/tglrvpy_ite @@ -0,0 +1 @@ +tglrvpu_ite
\ No newline at end of file diff --git a/board/tglrvpy_ite_tcpmv1 b/board/tglrvpy_ite_tcpmv1 new file mode 120000 index 0000000000..560115c8ab --- /dev/null +++ b/board/tglrvpy_ite_tcpmv1 @@ -0,0 +1 @@ +tglrvpy_ite
\ No newline at end of file diff --git a/include/config.h b/include/config.h index 240ff19e53..1c5fcdcb93 100644 --- a/include/config.h +++ b/include/config.h @@ -4959,6 +4959,7 @@ * Intel Reference Validation Platform's (RVP) Modular Embedded Control * Card (MECC) versions */ +#undef CONFIG_INTEL_RVP_MECC_VERSION_0_9 #undef CONFIG_INTEL_RVP_MECC_VERSION_1_0 #undef CONFIG_INTEL_RVP_MECC_VERSION_1_1 diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 14929c2404..26a22ceb06 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -544,6 +544,7 @@ CONFIG_INA219 CONFIG_INA231 CONFIG_INA3221 CONFIG_INDUCTIVE_CHARGING +CONFIG_INTEL_RVP_MECC_VERSION_0_9 CONFIG_INTEL_RVP_MECC_VERSION_1_0 CONFIG_IO_EXPANDER CONFIG_IO_EXPANDER_CCGXXF diff --git a/util/flash_ec b/util/flash_ec index a63db70fc2..b0ef53e0c6 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -52,7 +52,12 @@ BOARDS_IT83XX=( adlrvpm_ite adlrvpp_ite it83xx_evb + jslrvp_ite reef_it8320 + tglrvpu_ite + tglrvpu_ite_tcpmv1 + tglrvpy_ite + tglrvpy_ite_tcpmv1 ) BOARDS_IT83XX_SPI_PROGRAMMING=( |