diff options
| -rw-r--r-- | Makefile.rules | 4 | ||||
| -rw-r--r-- | chip/ish/aontaskfw/ish_aon_share.h | 13 | ||||
| -rw-r--r-- | chip/ish/aontaskfw/ish_aontask.c | 252 | ||||
| -rw-r--r-- | chip/ish/aontaskfw/ish_aontask.ld.in | 4 | ||||
| -rw-r--r-- | chip/ish/build.mk | 1 | ||||
| -rw-r--r-- | chip/ish/config_chip.h | 4 | ||||
| -rw-r--r-- | chip/ish/power_mgt.c | 83 | ||||
| -rw-r--r-- | chip/ish/registers.h | 31 | ||||
| -rw-r--r-- | core/minute-ia/ec.lds.S | 13 | ||||
| -rw-r--r-- | core/minute-ia/init.S | 2 |
10 files changed, 383 insertions, 24 deletions
diff --git a/Makefile.rules b/Makefile.rules index c2144617eb..4a6cca7542 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -571,7 +571,9 @@ $(ish-aontask-fw-bin):$(out)/$(ish-aontask-fw).ld $(if $(V),,@echo ' EXTBIN ' $(subst $(out)/,,$@) ; ) -@ $(CC) $(CFLAGS) -MMD -MF $(out)/$(ish-aontask-fw).d -c $(ish-aontask-fw).c \ -o $(out)/$(ish-aontask-fw).o - -@ $(CC) $(out)/$(ish-aontask-fw).o $(LDFLAGS) \ + -@ $(CC) $(CFLAGS) -MMD -MF $(out)/$(ish-aontask-dma).d -c $(ish-aontask-dma).c \ + -o $(out)/$(ish-aontask-dma).o + -@ $(CC) $(out)/$(ish-aontask-fw).o $(out)/$(ish-aontask-dma).o $(LDFLAGS) \ -o $(out)/$(ish-aontask-fw).elf -Wl,-T,$(out)/$(ish-aontask-fw).ld \ -Wl,-Map,$(out)/$(ish-aontask-fw).map -@ $(OBJCOPY) -O binary $(out)/$(ish-aontask-fw).elf $@ diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h index 3a5c1bd06b..ee630a49bf 100644 --- a/chip/ish/aontaskfw/ish_aon_share.h +++ b/chip/ish/aontaskfw/ish_aon_share.h @@ -37,6 +37,19 @@ struct ish_aon_share { /* for store/restore main FW's IDT */ struct idt_header main_fw_idt_hdr; + /** + * main FW's read only code and data region in main SRAM, + * address need 64 bytes align due to DMA requirement + */ + uint32_t main_fw_ro_addr; + uint32_t main_fw_ro_size; + + /** + * main FW's read and write data region in main SRAM, + * address need 64 bytes align due to DMA requirement + */ + uint32_t main_fw_rw_addr; + uint32_t main_fw_rw_size; } __packed; #endif /* __CROS_EC_ISH_AON_SHARE_H */ diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index 3c1095a157..e9992ae904 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -46,6 +46,7 @@ #include <common.h> #include <ia_structs.h> #include "power_mgt.h" +#include "ish_dma.h" #include "ish_aon_share.h" /** @@ -273,26 +274,261 @@ struct ish_aon_share aon_share = { .aon_ldt_size = sizeof(aon_ldt), }; +/* In IMR DDR, ISH FW image has a manifest header */ +#define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000) + +/* simple count based delay */ +static inline void delay(uint32_t count) +{ + while (count) + count--; +} + +static int store_main_fw(void) +{ + int ret; + uint64_t imr_fw_addr; + uint64_t imr_fw_rw_addr; + + imr_fw_addr = ((uint64_t)SNOWBALL_UMA_BASE_HI << 32) + + SNOWBALL_UMA_BASE_LO + + SNOWBALL_FW_OFFSET + + ISH_FW_IMAGE_MANIFEST_HEADER_SIZE; + + imr_fw_rw_addr = imr_fw_addr + aon_share.main_fw_rw_addr - + CONFIG_ISH_SRAM_BASE_START; + + /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ + CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA; + + /* store main FW's read and write data region to IMR/UMA DDR */ + ret = ish_dma_copy( + PAGING_CHAN, + imr_fw_rw_addr, + aon_share.main_fw_rw_addr, + aon_share.main_fw_rw_size, + SRAM_TO_UMA + ); + + /* enable BCG for DMA, DMA can't be accessed now */ + CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA; + + if (ret != DMA_RC_OK) { + + aon_share.last_error = AON_ERROR_DMA_FAILED; + aon_share.error_count++; + + return AON_ERROR_DMA_FAILED; + } + + return AON_SUCCESS; +} + +static int restore_main_fw(void) +{ + int ret; + uint64_t imr_fw_addr; + uint64_t imr_fw_ro_addr; + uint64_t imr_fw_rw_addr; + + imr_fw_addr = ((uint64_t)SNOWBALL_UMA_BASE_HI << 32) + + SNOWBALL_UMA_BASE_LO + + SNOWBALL_FW_OFFSET + + ISH_FW_IMAGE_MANIFEST_HEADER_SIZE; + + imr_fw_ro_addr = imr_fw_addr + aon_share.main_fw_ro_addr - + CONFIG_ISH_SRAM_BASE_START; + + imr_fw_rw_addr = imr_fw_addr + aon_share.main_fw_rw_addr - + CONFIG_ISH_SRAM_BASE_START; + + /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ + CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA; + + /* restore main FW's read only code and data region from IMR/UMA DDR */ + ret = ish_dma_copy( + PAGING_CHAN, + aon_share.main_fw_ro_addr, + imr_fw_ro_addr, + aon_share.main_fw_ro_size, + UMA_TO_SRAM + ); + + if (ret != DMA_RC_OK) { + + aon_share.last_error = AON_ERROR_DMA_FAILED; + aon_share.error_count++; + + /* enable BCG for DMA, DMA can't be accessed now */ + CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA; + + return AON_ERROR_DMA_FAILED; + } + + /* restore main FW's read and write data region from IMR/UMA DDR */ + ret = ish_dma_copy( + PAGING_CHAN, + aon_share.main_fw_rw_addr, + imr_fw_rw_addr, + aon_share.main_fw_rw_size, + UMA_TO_SRAM + ); + + /* enable BCG for DMA, DMA can't be accessed now */ + CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA; + + if (ret != DMA_RC_OK) { + + aon_share.last_error = AON_ERROR_DMA_FAILED; + aon_share.error_count++; + + return AON_ERROR_DMA_FAILED; + } + + return AON_SUCCESS; +} + +#ifdef CHIP_FAMILY_ISH3 +/* on ISH3, need reserve last SRAM bank for AON use */ +#define SRAM_POWER_OFF_BANKS (CONFIG_ISH_SRAM_BANKS - 1) +#else +/* from ISH4, has seprated AON memory, can power off entire main SRAM */ +#define SRAM_POWER_OFF_BANKS CONFIG_ISH_SRAM_BANKS +#endif + +/** + * check SRAM bank i power gated status in PMU_SRAM_PG_EN register + * 1: power gated 0: not power gated + */ +#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i))) + +/* enable power gate of a SRAM bank */ +#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i))) + +/* disable power gate of a SRAM bank */ +#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i))) + +/** + * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register + * 1: disabled 0: enabled + */ +#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4))) + +/* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ +#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4))) + +/* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ +#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4))) + +/* SRAM needs time to warm up after power on */ +#define SRAM_WARM_UP_DELAY_CNT 10 + +/* SRAM needs time to enter retention mode */ +#define CYCLES_PER_US 100 +#define SRAM_RETENTION_US_DELAY 5 +#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) + +static void sram_power(int on) +{ + int i; + uint32_t bank_size; + uint32_t sram_addr; + uint32_t erase_cfg; + + bank_size = CONFIG_ISH_SRAM_BANK_SIZE; + sram_addr = CONFIG_ISH_SRAM_BASE_START; + + /** + * set erase size as one bank, erase control register using DWORD as + * size unit, and using 0 based length, i.e if set 0, will erase one + * DWORD + */ + erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1; + + for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) { + + if (on && (BANK_PG_STATUS(i) || BANK_DISABLE_STATUS(i))) { + + /* power on and enable a bank */ + BANK_PG_DISABLE(i); + + delay(SRAM_WARM_UP_DELAY_CNT); + + BANK_ENABLE(i); + + /* erase a bank */ + ISH_SRAM_CTRL_ERASE_ADDR = sram_addr + (i * bank_size); + ISH_SRAM_CTRL_ERASE_CTRL = erase_cfg; + + /* wait erase complete */ + while (ISH_SRAM_CTRL_ERASE_CTRL & 0x1) + continue; + + } else { + /* disable and power off a bank */ + BANK_DISABLE(i); + BANK_PG_ENABLE(i); + } + + /** + * clear interrupt status register, not allow generate SRAM + * interrupts. Bringup already masked all SRAM interrupts when + * booting ISH + */ + ISH_SRAM_CTRL_INTR = 0xFFFFFFFF; + + } +} + static void handle_d0i2(void) { - /* TODO set main SRAM into retention mode*/ + /* set main SRAM into retention mode*/ + PMU_LDO_CTRL = PMU_LDO_BIT_RETENTION_ON | PMU_LDO_BIT_ON; + + /* delay some cycles before halt */ + delay(SRAM_RETENTION_CYCLES_DELAY); - /* ish_halt(); */ + ish_halt(); /* wakeup from PMU interrupt */ - /* TODO set main SRAM intto normal mode */ + /* set main SRAM intto normal mode */ + PMU_LDO_CTRL = PMU_LDO_BIT_ON; + + /** + * poll LDO_READY status to make sure SRAM LDO is on + * (exited retention mode) + */ + while (!(PMU_LDO_CTRL & PMU_LDO_BIT_READY)) + continue; } static void handle_d0i3(void) { - /* TODO store main FW 's context to IMR DDR from main SRAM */ - /* TODO power off main SRAM */ + int ret; + + /* store main FW 's context to IMR DDR from main SRAM */ + ret = store_main_fw(); - /* ish_halt(); */ + /* if store main FW failed, then switch back to main FW */ + if (ret != AON_SUCCESS) + return; + + /* power off main SRAM */ + sram_power(0); + + ish_halt(); /* wakeup from PMU interrupt */ - /* TODO power on main SRAM */ - /* TODO restore main FW 's context to main SRAM from IMR DDR */ + /* power on main SRAM */ + sram_power(1); + + /* restore main FW 's context to main SRAM from IMR DDR */ + ret = restore_main_fw(); + + if (ret != AON_SUCCESS) { + /* we can't switch back to main FW now, reset ISH */ + handle_reset(); + } } static void handle_d3(void) diff --git a/chip/ish/aontaskfw/ish_aontask.ld.in b/chip/ish/aontaskfw/ish_aontask.ld.in index a45bbdb6a9..3525519d5b 100644 --- a/chip/ish/aontaskfw/ish_aontask.ld.in +++ b/chip/ish/aontaskfw/ish_aontask.ld.in @@ -31,7 +31,8 @@ ENTRY(ish_aon_main); MEMORY { /* leave STACK_SIZE bytes in the end of memory for stack */ - RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN } + RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN +} SECTIONS { @@ -64,5 +65,4 @@ SECTIONS KEEP(*(.stack_tag)) } > RAM - } diff --git a/chip/ish/build.mk b/chip/ish/build.mk index 2c242725d2..20c0ad9e6b 100644 --- a/chip/ish/build.mk +++ b/chip/ish/build.mk @@ -30,6 +30,7 @@ chip-$(CONFIG_LOW_POWER_IDLE)+=power_mgt.o ifeq ($(CONFIG_ISH_PM_AONTASK),y) ish-aontask-fw=chip/ish/aontaskfw/ish_aontask +ish-aontask-dma=chip/ish/dma ish-aontask-fw-bin=$(out)/$(ish-aontask-fw).bin PROJECT_EXTRA+=$(ish-aontask-fw-bin) endif diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 93cc527f6b..74432baca1 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -58,6 +58,10 @@ #define CONFIG_ISH_AON_SRAM_ROM_START (CONFIG_ISH_AON_SRAM_BASE_END - \ CONFIG_ISH_AON_SRAM_ROM_SIZE) +#define CONFIG_ISH_SRAM_BANK_SIZE 0x8000 +#define CONFIG_ISH_SRAM_BANKS (CONFIG_ISH_SRAM_SIZE / \ + CONFIG_ISH_SRAM_BANK_SIZE) + /* Required for panic_output */ #define CONFIG_RAM_SIZE CONFIG_ISH_SRAM_SIZE #define CONFIG_RAM_BASE CONFIG_ISH_SRAM_BASE_START diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c index da86bb7608..7cf2cdc383 100644 --- a/chip/ish/power_mgt.c +++ b/chip/ish/power_mgt.c @@ -12,6 +12,7 @@ #include "aontaskfw/ish_aon_share.h" #include "power_mgt.h" #include "watchdog.h" +#include "ish_dma.h" #ifdef CONFIG_ISH_PM_DEBUG #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) @@ -28,6 +29,12 @@ extern void watchdog_enable(void); extern void watchdog_disable(void); #endif +/* defined in link script: core/minute-ia/ec.lds.S */ +extern uint32_t __aon_ro_start; +extern uint32_t __aon_ro_end; +extern uint32_t __aon_rw_start; +extern uint32_t __aon_rw_end; + /* power management internal context data structure */ struct pm_context { /* aontask image valid flag */ @@ -168,6 +175,16 @@ static void init_aon_task(void) "movw $0x18, %ax;\n" "ltr %ax;\n" "pop %eax;"); + + aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start; + aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end - + (uint32_t)&__aon_ro_start; + + aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start; + aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end - + (uint32_t)&__aon_rw_start; + + ish_dma_init(); } static inline void check_aon_task_status(void) @@ -236,18 +253,29 @@ static void enter_d0i0(void) static void enter_d0i1(void) { - timestamp_t t0, t1; + uint64_t current_irq_map; + timestamp_t t0, t1; t0 = get_time(); pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I1; - /* TODO: enable Trunk Clock Gating (TCG) of ISH */ + /* only enable PMU wakeup interrupt */ + current_irq_map = disable_all_interrupts(); + task_enable_irq(ISH_PMU_WAKEUP_IRQ); + + /* enable Trunk Clock Gating (TCG) of ISH */ + CCU_TCG_EN = 1; /* halt ISH cpu, will wakeup from PMU wakeup interrupt */ ish_halt(); - /* TODO disable Trunk Clock Gating (TCG) of ISH */ + /* disable Trunk Clock Gating (TCG) of ISH */ + CCU_TCG_EN = 0; + + /* restore interrupts */ + task_disable_irq(ISH_PMU_WAKEUP_IRQ); + restore_interrupts(current_irq_map); pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0; @@ -262,21 +290,36 @@ static void enter_d0i1(void) static void enter_d0i2(void) { - timestamp_t t0, t1; + uint64_t current_irq_map; + timestamp_t t0, t1; t0 = get_time(); pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I2; - /* TODO: enable Trunk Clock Gating (TCG) of ISH */ + /* only enable PMU wakeup interrupt */ + current_irq_map = disable_all_interrupts(); + task_enable_irq(ISH_PMU_WAKEUP_IRQ); + + /* enable Trunk Clock Gating (TCG) of ISH */ + CCU_TCG_EN = 1; + + /* enable power gating of RF(Cache) and ROMs */ + PMU_RF_ROM_PWR_CTRL = 1; switch_to_aontask(); + /* returned from aontask */ - /* TODO just for test, will remove later */ - ish_halt(); + /* disable power gating of RF(Cache) and ROMs */ + PMU_RF_ROM_PWR_CTRL = 0; - /* TODO disable Trunk Clock Gating (TCG) of ISH */ + /* disable Trunk Clock Gating (TCG) of ISH */ + CCU_TCG_EN = 0; + + /* restore interrupts */ + task_disable_irq(ISH_PMU_WAKEUP_IRQ); + restore_interrupts(current_irq_map); t1 = get_time(); @@ -292,20 +335,36 @@ static void enter_d0i2(void) static void enter_d0i3(void) { + uint64_t current_irq_map; timestamp_t t0, t1; t0 = get_time(); pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I3; - /*TODO some preparing work for D0i3 */ + /* only enable PMU wakeup interrupt */ + current_irq_map = disable_all_interrupts(); + task_enable_irq(ISH_PMU_WAKEUP_IRQ); + + /* enable Trunk Clock Gating (TCG) of ISH */ + CCU_TCG_EN = 1; + + /* enable power gating of RF(Cache) and ROMs */ + PMU_RF_ROM_PWR_CTRL = 1; switch_to_aontask(); - /*TODO just for test, will remove later */ - ish_halt(); + /* returned from aontask */ + + /* disable power gating of RF(Cache) and ROMs */ + PMU_RF_ROM_PWR_CTRL = 0; + + /* disable Trunk Clock Gating (TCG) of ISH */ + CCU_TCG_EN = 0; - /*TODO some restore work for D0i3 */ + /* restore interrupts */ + task_disable_irq(ISH_PMU_WAKEUP_IRQ); + restore_interrupts(current_irq_map); t1 = get_time(); diff --git a/chip/ish/registers.h b/chip/ish/registers.h index e8e9477e13..fad24b7778 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -126,6 +126,8 @@ enum ish_i2c_port { #define IPC_HOST2ISH_DOORBELL (ISH_IPC_BASE + 0x48) #define IPC_HOST2ISH_MSG_REGS (ISH_IPC_BASE + 0xE0) #define IPC_ISH2HOST_DOORBELL (ISH_IPC_BASE + 0x54) +#define IPC_ISH2PMC_DOORBELL (ISH_IPC_BASE + 0x58) +#define IPC_ISH2PMC_MSG_REGS (ISH_IPC_BASE + 0x260) #define IPC_BUSY_CLEAR (ISH_IPC_BASE + 0x378) #define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) #define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) @@ -133,6 +135,7 @@ enum ish_i2c_port { #define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) /* PMU Registers */ +#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) #define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) #define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ @@ -281,4 +284,32 @@ enum ish_i2c_port { #define LAPIC_ERR_RECV_ILLEGAL BIT(6) #define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300) +/* SRAM control registers */ +#define ISH_SRAM_CTRL_BASE 0x00500000 +#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) +#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) +#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) +#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) +#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) +#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) + +/* Software defined registers */ + +#if defined(CHIP_FAMILY_ISH3) +/* on ISH3, reused ISH2PMC IPC message registers */ +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_REGS +#else +/* from ISH4, used reserved rom part of AON memory */ +#define SNOWBALL_BASE CONFIG_ISH_AON_SRAM_ROM_START +#endif + +/** + * registers about UMA/IMR DDR information and FW location in it + * ISH Bringup will set these registers' value at boot + */ +#define SNOWBALL_UMA_BASE_HI REG32(SNOWBALL_BASE + (4 * 28)) +#define SNOWBALL_UMA_BASE_LO REG32(SNOWBALL_BASE + (4 * 29)) +#define SNOWBALL_UMA_LIMIT REG32(SNOWBALL_BASE + (4 * 30)) +#define SNOWBALL_FW_OFFSET REG32(SNOWBALL_BASE + (4 * 31)) + #endif /* __CROS_EC_REGISTERS_H */ diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S index f08131092b..8087f7ce01 100644 --- a/core/minute-ia/ec.lds.S +++ b/core/minute-ia/ec.lds.S @@ -13,6 +13,8 @@ SECTIONS { . = CONFIG_ISH_BOOT_START; /* ISH SRAM (640KB) begins at 0xFF000000 */ + __aon_ro_start = .; + /* .init section should be first, since it contains the boot code */ .init : { *(.init*); } .text : { *(.text.*); } @@ -140,6 +142,15 @@ SECTIONS KEEP(*(.rodata.*)) } + /* + * ISH DMA need 64 bytes address align, in D0i3 low power state + * need copy RW part to IMR DDR via DMA + */ + . = ALIGN(64); + __aon_ro_end = .; + + __aon_rw_start = .; + .data : { __data_start = .; *(.data.*); @@ -178,6 +189,8 @@ SECTIONS __shared_mem_buf = .; } + __aon_rw_end = . + CONFIG_SHAREDMEM_MINIMUM_SIZE; + ASSERT((__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE) <= (CONFIG_RAM_BASE + CONFIG_RAM_SIZE), "Not enough space for shared memory.") diff --git a/core/minute-ia/init.S b/core/minute-ia/init.S index 66154b2c19..b8e51ccc91 100644 --- a/core/minute-ia/init.S +++ b/core/minute-ia/init.S @@ -21,7 +21,7 @@ # and hence the same segment selector .set code_seg, 0x8 -.section .text.vecttable +.section .data.vecttable # Macro that defines an interrupt descriptor .macro interrupt_descriptor |