diff options
| -rw-r--r-- | board/scarlet/board.c | 8 | ||||
| -rw-r--r-- | chip/stm32/adc-stm32f0.c | 10 | ||||
| -rw-r--r-- | chip/stm32/adc_chip.h | 3 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 1 |
4 files changed, 22 insertions, 0 deletions
diff --git a/board/scarlet/board.c b/board/scarlet/board.c index 4d55ebfee0..6734f92792 100644 --- a/board/scarlet/board.c +++ b/board/scarlet/board.c @@ -340,6 +340,14 @@ int board_get_version(void) } } + /* + * Disable ADC module after we detect the board version, + * since this is the only thing ADC module needs to do + * for this board. + */ + if (version != BOARD_VERSION_UNKNOWN) + adc_disable(); + return version; } diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index cffae10fd9..fd9711d44a 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -284,6 +284,16 @@ int adc_read_channel(enum adc_channel ch) return value * adc->factor_mul / adc->factor_div + adc->shift; } +void adc_disable(void) +{ + STM32_ADC_CR |= STM32_ADC_CR_ADDIS; + /* + * Note that the ADC is not in OFF state immediately. + * Once the ADC is effectively put into OFF state, + * STM32_ADC_CR_ADDIS bit will be cleared by hardware. + */ +} + static void adc_init(void) { /* diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h index 9d28b027a8..7b40535ac0 100644 --- a/chip/stm32/adc_chip.h +++ b/chip/stm32/adc_chip.h @@ -24,6 +24,9 @@ struct adc_t { */ extern const struct adc_t adc_channels[]; +/* Disable ADC module when we don't need it anymore. */ +void adc_disable(void); + /* Minimum and maximum values returned by adc_read_channel(). */ #define ADC_READ_MIN 0 #define ADC_READ_MAX 4095 diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index c6e8321c20..432fc9a221 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -2059,6 +2059,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) #define STM32_ADC_CR_ADEN (1 << 0) +#define STM32_ADC_CR_ADDIS (1 << 1) #define STM32_ADC_CR_ADCAL (1 << 31) #define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ |