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-rw-r--r--board/firefly/usb_pd_config.h8
-rw-r--r--board/fruitpie/usb_pd_config.h8
-rw-r--r--board/samus_pd/board.c284
-rw-r--r--board/samus_pd/board.h191
-rw-r--r--board/samus_pd/build.mk14
-rw-r--r--board/samus_pd/ec.tasklist22
-rw-r--r--board/samus_pd/usb_pd_config.h109
-rw-r--r--board/samus_pd/usb_pd_policy.c119
-rw-r--r--board/zinger/usb_pd_config.h8
-rw-r--r--common/usb_pd_protocol.c8
-rwxr-xr-xutil/flash_ec2
11 files changed, 768 insertions, 5 deletions
diff --git a/board/firefly/usb_pd_config.h b/board/firefly/usb_pd_config.h
index b6558bd878..8e3a3a4af7 100644
--- a/board/firefly/usb_pd_config.h
+++ b/board/firefly/usb_pd_config.h
@@ -88,6 +88,14 @@ static inline void pd_set_host_mode(int enable)
{
}
+static inline int pd_adc_read(int cc)
+{
+ if (cc == 0)
+ return adc_read_channel(ADC_CH_CC1_PD);
+ else
+ return adc_read_channel(ADC_CH_CC2_PD);
+}
+
/* Standard-current DFP : no-connect voltage is 1.55V */
#define PD_SRC_VNC 1550 /* mV */
diff --git a/board/fruitpie/usb_pd_config.h b/board/fruitpie/usb_pd_config.h
index e3a0ab2302..3c53d5e923 100644
--- a/board/fruitpie/usb_pd_config.h
+++ b/board/fruitpie/usb_pd_config.h
@@ -76,6 +76,14 @@ static inline void pd_set_host_mode(int enable)
gpio_set_level(GPIO_CC_HOST, enable);
}
+static inline int pd_adc_read(int cc)
+{
+ if (cc == 0)
+ return adc_read_channel(ADC_CH_CC1_PD);
+ else
+ return adc_read_channel(ADC_CH_CC2_PD);
+}
+
/* Standard-current DFP : no-connect voltage is 1.55V */
#define PD_SRC_VNC 1550 /* mV */
diff --git a/board/samus_pd/board.c b/board/samus_pd/board.c
new file mode 100644
index 0000000000..3e0c5ea69e
--- /dev/null
+++ b/board/samus_pd/board.c
@@ -0,0 +1,284 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* samus_pd board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "registers.h"
+#include "task.h"
+#include "usb_pd_config.h"
+#include "util.h"
+
+void vbus_evt(enum gpio_signal signal)
+{
+ ccprintf("VBUS %d!\n", signal);
+}
+
+void bc12_evt(enum gpio_signal signal)
+{
+ ccprintf("PERICOM %d!\n", signal);
+}
+
+void board_config_pre_init(void)
+{
+ /*
+ * the DMA mapping is :
+ * Chan 2 : TIM1_CH1 (C0 RX)
+ * Chan 3 : SPI1_TX (C0 TX)
+ * Chan 4 : USART1_TX
+ * Chan 5 : USART1_RX
+ * Chan 6 : TIM3_CH1 (C1_RX)
+ * Chan 7 : SPI2_TX (C1 TX)
+ */
+
+ /*
+ * Remap USART1 RX/TX DMA to match uart driver. Remap SPI2 RX/TX and
+ * TIM3_CH1 for unique DMA channels.
+ */
+ STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) | (1 << 24) | (1 << 30);
+}
+
+/* GPIO signal list. Must match order from enum gpio_signal. */
+const struct gpio_info gpio_list[] = {
+ /* Interrupts */
+ {"USB_C0_VBUS_WAKE", GPIO_E, (1<<6), GPIO_INT_BOTH, vbus_evt},
+ {"USB_C1_VBUS_WAKE", GPIO_F, (1<<2), GPIO_INT_BOTH, vbus_evt},
+ {"USB_C0_BC12_INT_L", GPIO_B, (1<<0), GPIO_INT_FALLING, bc12_evt},
+ {"USB_C1_BC12_INT_L", GPIO_C, (1<<1), GPIO_INT_FALLING, bc12_evt},
+
+ /* PD RX/TX */
+ {"USB_C0_CC1_PD", GPIO_A, (1<<0), GPIO_ANALOG, NULL},
+ {"USB_C0_REF", GPIO_A, (1<<1), GPIO_ANALOG, NULL},
+ {"USB_C1_CC1_PD", GPIO_A, (1<<2), GPIO_ANALOG, NULL},
+ {"USB_C1_REF", GPIO_A, (1<<3), GPIO_ANALOG, NULL},
+ {"USB_C0_CC2_PD", GPIO_A, (1<<4), GPIO_ANALOG, NULL},
+ {"USB_C1_CC2_PD", GPIO_A, (1<<5), GPIO_ANALOG, NULL},
+ {"USB_C0_REF_PD_ODL", GPIO_A, (1<<6), GPIO_ODR_LOW, NULL},
+ {"USB_C1_REF_PD_ODL", GPIO_A, (1<<7), GPIO_ODR_LOW, NULL},
+
+ {"USB_C_CC_EN", GPIO_C, (1<<10), GPIO_OUT_LOW, NULL},
+ {"USB_C0_CC1_TX_EN", GPIO_A, (1<<15), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_CC2_TX_EN", GPIO_E, (1<<12), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_CC1_TX_EN", GPIO_B, (1<<9), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_CC2_TX_EN", GPIO_B, (1<<12), GPIO_OUT_HIGH, NULL},
+
+#if 0
+ /* Alternate functions */
+ {"USB_C0_TX_CLKOUT", GPIO_B, (1<<1), GPIO_OUT_LOW, NULL},
+ {"USB_C1_TX_CLKOUT", GPIO_E, (1<<1), GPIO_OUT_LOW, NULL},
+ {"USB_C0_TX_CLKIN", GPIO_B, (1<<3), GPIO_OUT_LOW, NULL},
+ {"USB_C1_TX_CLKIN", GPIO_B, (1<<13), GPIO_OUT_LOW, NULL},
+
+ {"USB_C0_CC1_TX_DATA", GPIO_B, (1<<4), GPIO_OUT_LOW, NULL},
+ {"USB_C0_CC1_TX_DATA", GPIO_B, (1<<5), GPIO_INPUT, NULL},
+ {"USB_C1_CC1_TX_DATA", GPIO_B, (1<<14), GPIO_OUT_LOW, NULL},
+ {"USB_C1_CC1_TX_DATA", GPIO_B, (1<<15), GPIO_INPUT, NULL},
+ {"USB_C0_CC2_TX_DATA", GPIO_E, (1<<14), GPIO_OUT_LOW, NULL},
+ {"USB_C0_CC2_TX_DATA", GPIO_E, (1<<15), GPIO_INPUT, NULL},
+ {"USB_C1_CC2_TX_DATA", GPIO_D, (1<<3), GPIO_OUT_LOW, NULL},
+ {"USB_C1_CC2_TX_DATA", GPIO_D, (1<<4), GPIO_INPUT, NULL},
+#endif
+
+ /* Power and muxes control */
+ {"PP3300_USB_PD_EN", GPIO_A, (1<<8), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_CHARGE_EN_L", GPIO_D, (1<<12), GPIO_OUT_LOW, NULL},
+ {"USB_C1_CHARGE_EN_L", GPIO_D, (1<<13), GPIO_OUT_LOW, NULL},
+ {"USB_C0_5V_EN", GPIO_D, (1<<14), GPIO_OUT_LOW, NULL},
+ {"USB_C1_5V_EN", GPIO_D, (1<<15), GPIO_OUT_LOW, NULL},
+ {"USB_C0_CC1_VCONN1_EN_L", GPIO_D, (1<<8), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_CC2_VCONN1_EN_L", GPIO_D, (1<<9), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_CC1_VCONN1_EN_L", GPIO_D, (1<<10), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_CC2_VCONN1_EN_L", GPIO_D, (1<<11), GPIO_OUT_HIGH, NULL},
+
+ {"USB_C0_CC1_ODL", GPIO_B, (1<<8), GPIO_OUT_LOW, NULL},
+ {"USB_C0_CC2_ODL", GPIO_E, (1<<0), GPIO_OUT_LOW, NULL},
+ {"USB_C1_CC1_ODL", GPIO_F, (1<<9), GPIO_OUT_LOW, NULL},
+ {"USB_C1_CC2_ODL", GPIO_F, (1<<10), GPIO_OUT_LOW, NULL},
+
+ {"USB_C_BC12_SEL", GPIO_C, (1<<0), GPIO_OUT_LOW, NULL},
+ {"USB_C0_SS1_EN_L", GPIO_E, (1<<2), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_SS2_EN_L", GPIO_E, (1<<3), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_SS1_EN_L", GPIO_E, (1<<9), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_SS2_EN_L", GPIO_E, (1<<10), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_SS1_DP_MODE_L", GPIO_E, (1<<4), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_SS2_DP_MODE_L", GPIO_E, (1<<5), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_SS1_DP_MODE_L", GPIO_E, (1<<11), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_SS2_DP_MODE_L", GPIO_E, (1<<13), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_DP_MODE_L", GPIO_E, (1<<8), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_DP_MODE_L", GPIO_F, (1<<6), GPIO_OUT_HIGH, NULL},
+ {"USB_C0_DP_POLARITY_L", GPIO_E, (1<<7), GPIO_OUT_HIGH, NULL},
+ {"USB_C1_DP_POLARITY_L", GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL},
+
+#if 0
+ /* Alternate functions */
+ {"USB_DM", GPIO_A, (1<<11), GPIO_ANALOG, NULL},
+ {"USB_DP", GPIO_A, (1<<12), GPIO_ANALOG, NULL},
+ {"UART_TX", GPIO_A, (1<<9), GPIO_OUT_LOW, NULL},
+ {"UART_RX", GPIO_A, (1<<10), GPIO_OUT_LOW, NULL},
+ {"TP64_SWDIO", GPIO_A, (1<<13), GPIO_ODR_HIGH, NULL},
+ {"TP71_SWCLK", GPIO_A, (1<<14), GPIO_ODR_HIGH, NULL},
+#endif
+
+ /*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+ {"SLAVE_I2C_SCL", GPIO_B, (1<<6), GPIO_INPUT, NULL},
+ {"SLAVE_I2C_SDA", GPIO_B, (1<<7), GPIO_INPUT, NULL},
+ {"MASTER_I2C_SCL", GPIO_B, (1<<10), GPIO_INPUT, NULL},
+ {"MASTER_I2C_SDA", GPIO_B, (1<<11), GPIO_INPUT, NULL},
+
+ /* Test points */
+ {"TP60", GPIO_C, (1<<11), GPIO_ODR_HIGH, NULL},
+
+ /* Case closed debugging. */
+ {"SPI_FLASH_WP_L", GPIO_D, (1<<2), GPIO_INPUT, NULL},
+ {"EC_INT_L", GPIO_B, (1<<2), GPIO_ODR_HIGH, NULL},
+ {"EC_IN_RW", GPIO_C, (1<<12), GPIO_INPUT, NULL},
+ {"EC_RST_L", GPIO_C, (1<<13), GPIO_OUT_HIGH, NULL},
+ {"SPI_FLASH_CS_L", GPIO_D, (1<<0), GPIO_INPUT, NULL},
+ {"SPI_FLASH_CLK", GPIO_D, (1<<1), GPIO_INPUT, NULL},
+ {"SPI_FLASH_MOSI", GPIO_C, (1<<3), GPIO_INPUT, NULL},
+ {"SPI_FLASH_MISO", GPIO_C, (1<<2), GPIO_INPUT, NULL},
+ {"EC_JTAG_TMS", GPIO_C, (1<<6), GPIO_INPUT, NULL},
+ {"EC_JTAG_TCK", GPIO_C, (1<<7), GPIO_INPUT, NULL},
+ {"EC_JTAG_TDO", GPIO_C, (1<<8), GPIO_INPUT, NULL},
+ {"EC_JTAG_TDI", GPIO_C, (1<<9), GPIO_INPUT, NULL},
+#if 0
+ /* Alternate functions */
+ {"EC_UART_TX", GPIO_C, (1<<4), GPIO_OUT_LOW, NULL},
+ {"EC_UART_RX", GPIO_C, (1<<5), GPIO_INPUT, NULL},
+ {"AP_UART_TX", GPIO_D, (1<<5), GPIO_OUT_LOW, NULL},
+ {"AP_UART_RX", GPIO_D, (1<<6), GPIO_INPUT, NULL},
+#endif
+
+ /* Unimplemented signals which we need to emulate for now */
+ GPIO_SIGNAL_NOT_IMPLEMENTED("ENTERING_RW"),
+ GPIO_SIGNAL_NOT_IMPLEMENTED("WP_L"),
+};
+BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT);
+
+/* Initialize board. */
+static void board_init(void)
+{
+ /*
+ * Enable CC lines after all GPIO have been initialized. Note, it is
+ * important that this is enabled after the CC_ODL lines are set low
+ * to specify device mode.
+ */
+ gpio_set_level(GPIO_USB_C_CC_EN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* Pins with alternate functions */
+const struct gpio_alt_func gpio_alt_funcs[] = {
+ {GPIO_B, 0x0018, 0, MODULE_USB_PD},/* SPI1: MISO(PB4) SCK(PB3) */
+ {GPIO_B, 0x6000, 0, MODULE_USB_PD},/* SPI2: MISO(PB14) SCK(PB13) */
+ {GPIO_B, 0x0002, 0, MODULE_USB_PD},/* TIM14_CH1: PB1) */
+ {GPIO_E, 0x0002, 0, MODULE_USB_PD},/* TIM17_CH1: PE1) */
+ {GPIO_A, 0x0600, 1, MODULE_UART}, /* USART1: PA9/PA10 */
+ {GPIO_D, 0x0060, 0, MODULE_UART}, /* USART2: PD5/PD6 */
+ {GPIO_C, 0x0030, 1, MODULE_UART}, /* USART3: PC4/PC5 */
+ {GPIO_B, 0x0cc0, 1, MODULE_I2C}, /* I2C SLAVE:PB6/7 MASTER:PB10/11 */
+};
+const int gpio_alt_funcs_count = ARRAY_SIZE(gpio_alt_funcs);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+ /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+ [ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
+ [ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
+ [ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
+ [ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+ {"master", I2C_PORT_MASTER, 100,
+ GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+ {"slave", I2C_PORT_SLAVE, 100,
+ GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+void board_set_usb_mux(enum typec_mux mux)
+{
+ /* reset everything */
+ gpio_set_level(GPIO_USB_C0_SS1_EN_L, 1);
+ gpio_set_level(GPIO_USB_C0_SS2_EN_L, 1);
+ gpio_set_level(GPIO_USB_C0_DP_MODE_L, 1);
+ gpio_set_level(GPIO_USB_C0_SS1_DP_MODE_L, 1);
+ gpio_set_level(GPIO_USB_C0_SS2_DP_MODE_L, 1);
+ switch (mux) {
+ case TYPEC_MUX_NONE:
+ /* everything is already disabled, we can return */
+ return;
+ case TYPEC_MUX_USB1:
+ gpio_set_level(GPIO_USB_C0_SS1_DP_MODE_L, 0);
+ break;
+ case TYPEC_MUX_USB2:
+ gpio_set_level(GPIO_USB_C0_SS2_DP_MODE_L, 0);
+ break;
+ case TYPEC_MUX_DP1:
+ gpio_set_level(GPIO_USB_C0_DP_POLARITY_L, 1);
+ gpio_set_level(GPIO_USB_C0_DP_MODE_L, 0);
+ break;
+ case TYPEC_MUX_DP2:
+ gpio_set_level(GPIO_USB_C0_DP_POLARITY_L, 0);
+ gpio_set_level(GPIO_USB_C0_DP_MODE_L, 0);
+ break;
+ }
+ gpio_set_level(GPIO_USB_C0_SS1_EN_L, 0);
+ gpio_set_level(GPIO_USB_C0_SS2_EN_L, 0);
+}
+
+static int command_typec(int argc, char **argv)
+{
+ const char * const mux_name[] = {"none", "usb1", "usb2", "dp1", "dp2"};
+
+ if (argc < 2) {
+ /* dump current state */
+ ccprintf("CC1 %d mV CC2 %d mV\n",
+ pd_adc_read(0),
+ pd_adc_read(1));
+ ccprintf("DP %d Polarity %d\n",
+ !gpio_get_level(GPIO_USB_C0_DP_MODE_L),
+ !!gpio_get_level(GPIO_USB_C0_DP_POLARITY_L) + 1);
+ ccprintf("Superspeed %s\n",
+ gpio_get_level(GPIO_USB_C0_SS1_EN_L) ? "None" :
+ (!gpio_get_level(GPIO_USB_C0_DP_MODE_L) ? "DP" :
+ (!gpio_get_level(GPIO_USB_C0_SS1_DP_MODE_L) ?
+ "USB1" : "USB2")));
+ return EC_SUCCESS;
+ }
+
+ if (!strcasecmp(argv[1], "mux")) {
+ enum typec_mux mux = TYPEC_MUX_NONE;
+ int i;
+
+ if (argc < 3)
+ return EC_ERROR_PARAM2;
+
+ for (i = 0; i < ARRAY_SIZE(mux_name); i++)
+ if (!strcasecmp(argv[2], mux_name[i]))
+ mux = i;
+ board_set_usb_mux(mux);
+ return EC_SUCCESS;
+ } else {
+ return EC_ERROR_PARAM1;
+ }
+
+ return EC_ERROR_UNKNOWN;
+}
+DECLARE_CONSOLE_COMMAND(typec, command_typec,
+ "[mux none|usb1|usb2|dp1|d2]",
+ "Control type-C connector",
+ NULL);
diff --git a/board/samus_pd/board.h b/board/samus_pd/board.h
new file mode 100644
index 0000000000..fd6cccd819
--- /dev/null
+++ b/board/samus_pd/board.h
@@ -0,0 +1,191 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* samus_pd board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+
+/* Optional features */
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_INTERNAL_COMP
+#define CONFIG_ADC
+#define CONFIG_HW_CRC
+#define CONFIG_I2C
+#define CONFIG_BATTERY_SMART
+#define CONFIG_USB_SWITCH_TSU6721
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TASK_PROFILING
+
+/* I2C ports configuration */
+#define I2C_PORT_MASTER 1
+#define I2C_PORT_BATTERY I2C_PORT_MASTER
+#define I2C_PORT_CHARGER I2C_PORT_MASTER
+#define I2C_PORT_SLAVE 0
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC 3
+
+/* GPIO signal list */
+enum gpio_signal {
+ /* Inputs with interrupt handlers are first for efficiency */
+ GPIO_USB_C0_VBUS_WAKE = 0,
+ GPIO_USB_C1_VBUS_WAKE,
+ GPIO_USB_C0_BC12_INT_L,
+ GPIO_USB_C1_BC12_INT_L,
+
+ /* PD RX/TX */
+ GPIO_USB_C0_CC1_PD,
+ GPIO_USB_C0_REF,
+ GPIO_USB_C1_CC1_PD,
+ GPIO_USB_C1_REF,
+ GPIO_USB_C0_CC2_PD,
+ GPIO_USB_C1_CC2_PD,
+ GPIO_USB_C0_REF_PD_ODL,
+ GPIO_USB_C1_REF_PD_ODL,
+
+ GPIO_USB_C_CC_EN,
+ GPIO_USB_C0_CC1_TX_EN,
+ GPIO_USB_C0_CC2_TX_EN,
+ GPIO_USB_C1_CC1_TX_EN,
+ GPIO_USB_C1_CC2_TX_EN,
+
+#if 0
+ /* Alternate functions */
+ GPIO_USB_C0_TX_CLKOUT,
+ GPIO_USB_C1_TX_CLKOUT,
+ GPIO_USB_C0_TX_CLKIN,
+ GPIO_USB_C1_TX_CLKIN,
+
+ GPIO_USB_C0_CC1_TX_DATA,
+ GPIO_USB_C0_CC1_TX_DATA,
+ GPIO_USB_C1_CC1_TX_DATA,
+ GPIO_USB_C1_CC1_TX_DATA,
+ GPIO_USB_C0_CC2_TX_DATA,
+ GPIO_USB_C0_CC2_TX_DATA,
+ GPIO_USB_C1_CC2_TX_DATA,
+ GPIO_USB_C1_CC2_TX_DATA,
+#endif
+
+ /* Power and muxes control */
+ GPIO_PP3300_USB_PD_EN,
+ GPIO_USB_C0_CHARGE_EN_L,
+ GPIO_USB_C1_CHARGE_EN_L,
+ GPIO_USB_C0_5V_EN,
+ GPIO_USB_C1_5V_EN,
+ GPIO_USB_C0_VCONN1_EN,
+ GPIO_USB_C0_VCONN2_EN,
+ GPIO_USB_C1_VCONN1_EN,
+ GPIO_USB_C1_VCONN2_EN,
+
+ GPIO_USB_C0_CC1_ODL,
+ GPIO_USB_C0_CC2_ODL,
+ GPIO_USB_C1_CC1_ODL,
+ GPIO_USB_C1_CC2_ODL,
+
+ GPIO_USB_C_BC12_SEL,
+
+ GPIO_USB_C0_SS1_EN_L,
+ GPIO_USB_C0_SS2_EN_L,
+ GPIO_USB_C1_SS1_EN_L,
+ GPIO_USB_C1_SS2_EN_L,
+ GPIO_USB_C0_SS1_DP_MODE_L,
+ GPIO_USB_C0_SS2_DP_MODE_L,
+ GPIO_USB_C1_SS1_DP_MODE_L,
+ GPIO_USB_C1_SS2_DP_MODE_L,
+ GPIO_USB_C0_DP_MODE_L,
+ GPIO_USB_C1_DP_MODE_L,
+ GPIO_USB_C0_DP_POLARITY_L,
+ GPIO_USB_C1_DP_POLARITY_L,
+
+#if 0
+ /* Alternate functions */
+ GPIO_USB_DM,
+ GPIO_USB_DP,
+ GPIO_UART_TX,
+ GPIO_UART_RX,
+ GPIO_TP64,
+ GPIO_TP71,
+#endif
+
+ /* I2C busses */
+ GPIO_SLAVE_I2C_SCL,
+ GPIO_SLAVE_I2C_SDA,
+ GPIO_MASTER_I2C_SCL,
+ GPIO_MASTER_I2C_SDA,
+
+ /* Test points */
+ GPIO_TP60,
+
+ /* Case closed debugging */
+ GPIO_SPI_FLASH_WP_L,
+ GPIO_EC_INT_L,
+ GPIO_EC_IN_RW,
+ GPIO_EC_RST_L,
+ GPIO_SPI_FLASH_CS_L,
+ GPIO_SPI_FLASH_CSK,
+ GPIO_SPI_FLASH_MOSI,
+ GPIO_SPI_FLASH_MISO,
+ GPIO_EC_JTAG_TMS,
+ GPIO_EC_JTAG_TCK,
+ GPIO_EC_JTAG_TDO,
+ GPIO_EC_JTAT_TDI,
+#if 0
+ /* Alternate functions */
+ GPIO_EC_UART_TX,
+ GPIO_EC_UART_RX,
+ GPIO_AP_UART_TX,
+ GPIO_AP_UART_RX,
+#endif
+
+ /* Unimplemented signals we emulate */
+ GPIO_ENTERING_RW,
+ GPIO_WP_L,
+ /* Number of GPIOs; not an actual GPIO */
+ GPIO_COUNT
+};
+
+/* ADC signal */
+enum adc_channel {
+ ADC_C0_CC1_PD = 0,
+ ADC_C0_CC2_PD,
+ ADC_C1_CC1_PD,
+ ADC_C1_CC2_PD,
+ /* Number of ADC channels */
+ ADC_CH_COUNT
+};
+
+/* Muxing for the USB type C */
+enum typec_mux {
+ TYPEC_MUX_NONE,
+ TYPEC_MUX_USB1,
+ TYPEC_MUX_USB2,
+ TYPEC_MUX_DP1,
+ TYPEC_MUX_DP2,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/samus_pd/build.mk b/board/samus_pd/build.mk
new file mode 100644
index 0000000000..af7ff42076
--- /dev/null
+++ b/board/samus_pd/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F072VBH6
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/samus_pd/ec.tasklist b/board/samus_pd/ec.tasklist
new file mode 100644
index 0000000000..a8250d57c1
--- /dev/null
+++ b/board/samus_pd/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+ TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
+ TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+ TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE)
diff --git a/board/samus_pd/usb_pd_config.h b/board/samus_pd/usb_pd_config.h
new file mode 100644
index 0000000000..502ad3dfd9
--- /dev/null
+++ b/board/samus_pd/usb_pd_config.h
@@ -0,0 +1,109 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery board configuration */
+
+#ifndef __USB_PD_CONFIG_H
+#define __USB_PD_CONFIG_H
+
+/* Timer selection for baseband PD communication */
+#define TIM_CLOCK_PD_TX 14
+#define TIM_CLOCK_PD_RX 1
+
+/* use the hardware accelerator for CRC */
+#define CONFIG_HW_CRC
+
+/* TX is using SPI1 on PB3-5 */
+#define SPI_REGS STM32_SPI1_REGS
+#define DMAC_SPI_TX STM32_DMAC_CH3
+
+static inline void spi_enable_clock(void)
+{
+ STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+}
+
+/* RX is using COMP1 triggering TIM1 CH1 */
+#define DMAC_TIM_RX STM32_DMAC_CH2
+#define TIM_CCR_IDX 1
+#define TIM_CCR_CS 1
+#define EXTI_COMP_MASK (1 << 21)
+#define IRQ_COMP STM32_IRQ_COMP
+/* triggers packet detection on comparator falling edge */
+#define EXTI_XTSR STM32_EXTI_FTSR
+
+/* the pins used for communication need to be hi-speed */
+static inline void pd_set_pins_speed(void)
+{
+ /* 40 MHz pin speed on SPI PB3/4/5 */
+ STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000FC0;
+ /* 40 MHz pin speed on TIM14_CH1 (PB1) */
+ STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000000C0;
+}
+
+/* Drive the CC line from the TX block */
+static inline void pd_tx_enable(int polarity)
+{
+ gpio_set_level(GPIO_USB_C0_CC1_TX_EN, 1);
+ gpio_set_level(GPIO_USB_C0_CC2_TX_EN, 1);
+}
+
+/* Put the TX driver in Hi-Z state */
+static inline void pd_tx_disable(int polarity)
+{
+ gpio_set_level(GPIO_USB_C0_CC1_TX_EN, 0);
+ gpio_set_level(GPIO_USB_C0_CC2_TX_EN, 0);
+}
+
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int polarity)
+{
+ /* use the right comparator non inverted input for COMP1 */
+ STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
+ | STM32_COMP_CMP1EN
+ | (polarity ? STM32_COMP_CMP1INSEL_INM4
+ : STM32_COMP_CMP1INSEL_INM6);
+}
+
+/* Initialize pins used for TX and put them in Hi-Z */
+static inline void pd_tx_init(void)
+{
+ gpio_config_module(MODULE_USB_PD, 1);
+}
+
+static inline void pd_set_host_mode(int enable)
+{
+ if (enable) {
+ /* High-Z is used for host mode. */
+ gpio_set_flags(GPIO_USB_C0_CC1_ODL, GPIO_INPUT);
+ gpio_set_flags(GPIO_USB_C0_CC2_ODL, GPIO_INPUT);
+ } else {
+ /* Pull low for device mode. */
+ gpio_set_flags(GPIO_USB_C0_CC1_ODL, GPIO_OUT_LOW);
+ gpio_set_flags(GPIO_USB_C0_CC2_ODL, GPIO_OUT_LOW);
+ }
+
+}
+
+static inline int pd_adc_read(int cc)
+{
+ if (cc == 0)
+ return adc_read_channel(ADC_C0_CC1_PD);
+ else
+ return adc_read_channel(ADC_C0_CC2_PD);
+}
+
+/* Standard-current DFP : no-connect voltage is 1.55V */
+#define PD_SRC_VNC 1550 /* mV */
+
+/* UFP-side : threshold for DFP connection detection */
+#define PD_SNK_VA 200 /* mV */
+
+/* start as a sink in case we have no other power supply/battery */
+#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
+
+/* delay necessary for the voltage transition on the power supply */
+#define PD_POWER_SUPPLY_TRANSITION_DELAY 50000 /* us */
+
+#endif /* __USB_PD_CONFIG_H */
diff --git a/board/samus_pd/usb_pd_policy.c b/board/samus_pd/usb_pd_policy.c
new file mode 100644
index 0000000000..c4c75fe63a
--- /dev/null
+++ b/board/samus_pd/usb_pd_policy.c
@@ -0,0 +1,119 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "board.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+
+/* TODO(crossbug.com/p/28869): update source and sink tables to spec. */
+const uint32_t pd_src_pdo[] = {
+ PDO_FIXED(5000, 500, PDO_FIXED_EXTERNAL),
+ PDO_FIXED(5000, 900, 0),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+/* TODO(crossbug.com/p/28869): update source and sink tables to spec. */
+const uint32_t pd_snk_pdo[] = {
+ PDO_BATT(4500, 5500, 15000),
+ PDO_BATT(11500, 12500, 36000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+/* Cap on the max voltage requested as a sink (in millivolts) */
+static unsigned max_mv = -1; /* no cap */
+
+int pd_choose_voltage(int cnt, uint32_t *src_caps, uint32_t *rdo)
+{
+ int i;
+ int sel_mv;
+ int max_uw = 0;
+ int max_i = -1;
+
+ /* Get max power */
+ for (i = 0; i < cnt; i++) {
+ int uw;
+ int mv = ((src_caps[i] >> 10) & 0x3FF) * 50;
+ if ((src_caps[i] & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
+ uw = 250000 * (src_caps[i] & 0x3FF);
+ } else {
+ int ma = (src_caps[i] & 0x3FF) * 10;
+ uw = ma * mv;
+ }
+ if ((uw > max_uw) && (mv <= max_mv)) {
+ max_i = i;
+ max_uw = uw;
+ sel_mv = mv;
+ }
+ }
+ if (max_i < 0)
+ return -EC_ERROR_UNKNOWN;
+
+ /* request all the power ... */
+ if ((src_caps[max_i] & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
+ int uw = 250000 * (src_caps[i] & 0x3FF);
+ *rdo = RDO_BATT(max_i + 1, uw/2, uw, 0);
+ ccprintf("Request [%d] %dV %d/%d mW\n",
+ max_i, sel_mv/1000, uw/1000, uw/1000);
+ } else {
+ int ma = 10 * (src_caps[max_i] & 0x3FF);
+ *rdo = RDO_FIXED(max_i + 1, ma / 2, ma, 0);
+ ccprintf("Request [%d] %dV %d/%d mA\n",
+ max_i, sel_mv/1000, max_i, ma/2, ma);
+ }
+ return EC_SUCCESS;
+}
+
+void pd_set_max_voltage(unsigned mv)
+{
+ max_mv = mv;
+}
+
+int pd_request_voltage(uint32_t rdo)
+{
+ int op_ma = rdo & 0x3FF;
+ int max_ma = (rdo >> 10) & 0x3FF;
+ int idx = rdo >> 28;
+ uint32_t pdo;
+ uint32_t pdo_ma;
+
+ if (!idx || idx > pd_src_pdo_cnt)
+ return EC_ERROR_INVAL; /* Invalid index */
+
+ /* check current ... */
+ pdo = pd_src_pdo[idx - 1];
+ pdo_ma = (pdo & 0x3ff);
+ if (op_ma > pdo_ma)
+ return EC_ERROR_INVAL; /* too much op current */
+ if (max_ma > pdo_ma)
+ return EC_ERROR_INVAL; /* too much max current */
+
+ ccprintf("Switch to %d V %d mA (for %d/%d mA)\n",
+ ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
+ ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10);
+
+ return EC_SUCCESS;
+}
+
+int pd_set_power_supply_ready(void)
+{
+ return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(void)
+{
+}
+
+int pd_board_checks(void)
+{
+ return EC_SUCCESS;
+}
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index dac4bf2c63..4383e24e32 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -73,6 +73,14 @@ static inline void pd_tx_init(void)
/* Already done in hardware_init() */
}
+static inline int pd_adc_read(int cc)
+{
+ if (cc == 0)
+ return adc_read_channel(ADC_CH_CC1_PD);
+ else
+ return adc_read_channel(ADC_CH_CC2_PD);
+}
+
/* 3.0A DFP : no-connect voltage is 2.45V */
#define PD_SRC_VNC (2450 /*mV*/ * 4096 / 3300/* 12-bit ADC with 3.3V range */)
diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c
index 08381dcf2f..d9eb6259d6 100644
--- a/common/usb_pd_protocol.c
+++ b/common/usb_pd_protocol.c
@@ -669,8 +669,8 @@ void pd_task(void)
break;
case PD_STATE_SRC_DISCONNECTED:
/* Vnc monitoring */
- cc1_volt = adc_read_channel(ADC_CH_CC1_PD);
- cc2_volt = adc_read_channel(ADC_CH_CC2_PD);
+ cc1_volt = pd_adc_read(0);
+ cc2_volt = pd_adc_read(1);
if ((cc1_volt < PD_SRC_VNC) ||
(cc2_volt < PD_SRC_VNC)) {
pd_polarity = !(cc1_volt < PD_SRC_VNC);
@@ -726,8 +726,8 @@ void pd_task(void)
#ifdef CONFIG_USB_PD_DUAL_ROLE
case PD_STATE_SNK_DISCONNECTED:
/* Source connection monitoring */
- cc1_volt = adc_read_channel(ADC_CH_CC1_PD);
- cc2_volt = adc_read_channel(ADC_CH_CC2_PD);
+ cc1_volt = pd_adc_read(0);
+ cc2_volt = pd_adc_read(1);
if ((cc1_volt > PD_SNK_VA) ||
(cc2_volt > PD_SNK_VA)) {
pd_polarity = !(cc1_volt > PD_SNK_VA);
diff --git a/util/flash_ec b/util/flash_ec
index 1727b9120e..1a64ab409e 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -245,7 +245,7 @@ save="$(servo_save)"
case "${BOARD}" in
big | discovery | nyan | pit | snow | spring ) flash_stm32 ;;
- fruitpie | zinger | firefly) flash_stm32 ;;
+ fruitpie | zinger | firefly | samus_pd) flash_stm32 ;;
falco | peppy | rambi | samus | squawks ) flash_lm4 ;;
link ) flash_link ;;
*) die "board ${BOARD} not supported" ;;